Timing Margin Detecting Circuit, Timing Margin Detecting Method and Clock and Data Recovery System

Abstract

A timing margin detecting circuit is provided. The timing margin detecting circuit comprises a delay element, receiving a first data signal and a first clock signal, configured to generate a second data signal and a second clock signal, wherein the second clock signal has a delay relative to the second data signal; a controller, configured to generate the control signal to control the delay of the second clock signal relative to the second data signal; a sampler, coupled to the delay element, configured to generate a sampled data signal according to the second data signal and the second clock signal; and a bit error rate determination circuit, coupled to the sampler, configured to determine whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly; wherein the controller determines a timing margin according to the determination result.

Claims

1. A timing margin detecting circuit, coupled to a clock and data recovery (CDR) circuit, the timing margin detecting circuit comprising: a delay element, receiving a first data signal and a first clock signal, configured to generate a second data signal and a second clock signal according to a control signal, the first data signal and the first clock, wherein the second clock signal has a delay relative to the second data signal; a controller, configured to generate the control signal to control the delay of the second clock signal relative to the second data signal and determine a timing margin corresponding to a configuration of the CDR circuit that makes the CDR circuit operate in a corresponding bandwidth; a sampler, coupled to the delay element, configured to generate a sampled data signal according to the second data signal and the second clock signal; and a bit error rate determination circuit, coupled to the sampler, configured to determine whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly, wherein the determination result indicates either the sampled data signal is the same as the predefined test pattern or the sampled data signal is not the same as the predefined test pattern; wherein the controller determines the timing margin according to a plurality of determination results that the bit error rate determination circuit generates corresponding to a plurality of delays, and the controller adjusts the configuration of the CDR circuit to determine an another timing margin.

2. The timing margin detecting circuit of claim 1, wherein the second data signal is the original first data signal or a delayed version of the first data signal; the second clock signal is the original first clock signal or a delayed version of the first clock signal.

3. The timing margin detecting circuit of claim 1, wherein the sampler comprises a delay flip-flop (D flip-flop).

4. The timing margin detecting circuit of claim 1, wherein the bit error rate determination circuit comprises an exclusive or (XOR) gate.

5. The timing margin detecting circuit of claim 1, wherein the controller generates a plurality of control signals to the delay element, and the plurality of control signals is corresponding to the plurality of delays of the second clock signal relative to the second data signal; the sampler generates a plurality of sampled data signals corresponding to the plurality of delays; the bit error rate determination circuit generates the plurality of determination results corresponding to the plurality of delays according to the plurality of sampled data signals.

6. The timing margin detecting circuit of claim 1, wherein the controller obtains a first determination result corresponding to a first delay and the first determination result indicates that the sampled data signal is not the same as the predefined test pattern; the controller obtains a second determination result corresponding to a second delay and the second determination result indicates that the sampled data signal is not the same as the predefined test pattern; the controller obtains a third determination result corresponding to a third delay and the third determination result indicates that the sampled data signal is the same as the predefined test pattern, the third delay is larger than the first delay and smaller than the second delay; and the controller determines an eye width according to the first delay corresponding to the first determination result and the second delay corresponding to the second determination result.

7. The timing margin detecting circuit of claim 1, wherein the controller generates an initial control signal corresponding to an initial delay of the second clock signal relative to the second data signal, and the initial delay is the same as a delay of the first clock signal relative to the first data signal; the controller generates a plurality of control signals to the delay element, and the plurality of control signals is corresponding to a plurality of delays of the second clock signal relative to the second data signal.

8. The timing margin detecting circuit of claim 7, wherein the controller obtains a first determination result corresponding to a first delay and the first determination result indicates that the sampled data signal is not the same as the predefined test pattern; the controller determines a setup time according to the initial delay and the first delay corresponding to the first determination result.

9. The timing margin detecting circuit of claim 7, wherein the controller obtains a first determination result corresponding to a first delay and the first determination result indicates that the sampled data signal is not the same as the predefined test pattern; the controller determines a hold time according to the initial delay and the first delay corresponding to the first determination result.

10. A timing margin detecting method, applied in a timing margin detecting circuit coupled to a clock and data recovery (CDR) circuit, the method comprising: receiving a first data signal and a first clock signal and generating a second data signal and a second clock signal according to a control signal, the first data signal and the first clock signal, wherein the second clock signal has a delay relative to the second data signal; generating a sampled data signal according to the second data signal and the second clock signal; determining whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly, wherein the determination result indicates either the sampled data signal is the same as the predefined test pattern or the sampled data signal is not the same as the predefined test pattern; determining a timing margin corresponding to a configuration of the CDR circuit that makes the CDR circuit operate in a corresponding bandwidth; determining the timing margin according to a plurality of determination results corresponding to a plurality of delays; and adjusting the configuration of the CDR circuit to determine an another timing margin.

11. The timing margin detecting method of claim 10, further comprising: generating a plurality of control signals corresponding to the plurality of delays of the second clock signal relative to the second data signal; generating a plurality of sampled data signals corresponding to the plurality of delays; and generating the plurality of determination results corresponding to the plurality of delays according to the plurality of sampled data signals.

12. The timing margin detecting method of claim 10, further comprising: determining an eye width according to a first delay and a second delay when a first determination result corresponding to the first delay, a second determination result corresponding to the second delay and a third determination result corresponding to a third delay are obtained, wherein the first determination result and the second determination result indicates that the sampled data signal is not the same as the predefined test pattern, and the third determination result indicates that the sampled data signal is the same as the predefined test pattern; wherein the third delay is larger than the first delay and smaller than the second delay.

13. The timing margin detecting method of claim 10, further comprising: determining a setup time according to an initial delay and a first delay when a first determination result corresponding to the first delay is obtained and the first determination result indicates that the sampled data signal is not the same as the predefined test pattern; wherein the initial delay is the same as a delay of the first clock signal relative to the first data signal, and the initial delay is larger than the first delay.

14. The timing margin detecting method of claim 10, further comprising: determining a hold time according to an initial delay and a first delay when a first determination result corresponding to the first delay is obtained and the first determination result indicates that the sampled data signal is not the same as the predefined test pattern; wherein the initial delay is the same as a delay of the first clock signal relative to the first data signal, and the initial delay is smaller than the first delay.

15. A clock and data recovery (CDR) system, comprising: a CDR circuit; and a timing margin detecting circuit, coupled to the CDR circuit, comprising: a delay element, receiving a first data signal and a first clock signal, configured to generate a second data signal and a second clock signal according to a control signal, the first data signal and the first clock, wherein the second clock signal has a delay relative to the second data signal; a controller, configured to generate the control signal to control the delay of the second clock signal relative to the second data signal and determine a timing margin corresponding to a configuration of the CDR circuit that makes the CDR circuit operate in a corresponding bandwidth; a first sampler, coupled to the delay element, configured to generate a sampled data signal according to the second data signal and the second clock signal; and a bit error rate determination circuit, coupled to the sampler, configured to determine whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly, wherein the determination result indicates either the sampled data signal is the same as the predefined test pattern or the sampled data signal is not the same as the predefined test pattern; wherein the controller determines the timing margin according to a plurality of determination results that the bit error rate determination circuit generates corresponding to a plurality of delays, and the controller adjusts the configuration of the CDR circuit to determine an another timing margin.

16. The CDR system of claim 15, wherein the CDR circuit comprises a phase detector; a voltage control oscillator; a filter, coupled between the phase detector and the voltage control oscillator; and a second sampler, coupled to the phase detector.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a schematic diagram of a clock and data recovery (CDR) system according to an embodiment of the present application.

[0011] FIG. 2 is a schematic diagram of waveforms of a clock signal and a data signal according to an embodiment of the present application.

[0012] FIG. 3 is a schematic diagram of waveforms of a clock signal and a data signal according to an embodiment of the present application.

[0013] FIG. 4 is a schematic diagram of waveforms of a clock signal and a data signal according to an embodiment of the present application.

[0014] FIG. 5 is a schematic diagram of a process according to an embodiment of the present application.

[0015] FIG. 6 is a schematic diagram of a CDR system according to an embodiment of the present application.

DETAILED DESCRIPTION

[0016] FIG. 1 is a schematic diagram of a clock and data recovery (CDR) system 1 according to an embodiment of the present application. The CDR system 1 may be applied/disposed within a digital system, which receives a data signal and a clock signal. The CDR system 1 comprises a timing margin detecting circuit 10 and a CDR circuit 12. The CDR circuit 12 may comprise a phase detector, a charge pump (CP)/filter, a voltage control oscillator (VCO)/divider, and a sampler, where the sampler may be a delay flip-flop (D flip-flop, a.k.a., DFF). Note that, the CDR circuit 12 serves an example of (general) CDR circuit, which does not intend to preclude other CDR circuit topology. Various CDR circuits may be incorporated into the CDR system 1 of the present application, which is within the scope the present application.

[0017] The timing margin detecting circuit 10 is configured to obtain a timing margin of a first data signal D and a first clock signal CK of the CDR system 1. The timing margin, as known in the art, is usually referred to the time that the data eye (or, eye width) is valid for a device to be sampled as a logic “1” or a logic “0”. Physically, in the present application, the timing margin may be referred to a setup time or a hold time for the CDR system.

[0018] For example, FIG. 2 illustrates a schematic diagram of waveforms of the data signal D and the clock signal CK, demonstrating an illustration of a setup time T.sub.SU and a hold time T.sub.H. As known in the art, the setup time T.sub.SU is referred to a time interval (or an amount of time) for which the data signal D remains stable before an (active) edge of the clock signal CK; while the hold time T.sub.H is referred to a time interval for which the data signal D remains stable after the (active) edge of the clock signal CK. The timing margin detecting circuit 10 may be configured to obtain either the setup time T.sub.SU or the hold time T.sub.H (or both), as a timing margin T.sub.MG, corresponding to the data signal D and the clock signal CK of the CDR system 1.

[0019] The timing margin detecting circuit 10 comprises a delay element 102, a controller 104, a sampler 106 and a bit error rate (BER) determination circuit 108. The controller 104 is configured to generate a control signal ctrl to/for the delay element 104. The delay element 102 receives the (first) data signal D and the (first) clock signal CK. The delay element 102 is configured to generate a second data signal D′ and a second clock signal CK′, which are generated according to the data signal D, the clock signal CK and the control signal ctrl. The (second) data signal D′ may be the original (first) data signal D or a delayed version of the (first) data signal D; while the (second) clock signal CK′ may be the original (first) clock signal CK or a delayed version of the (first) clock signal CK. Between the data signal D′ and the clock signal CK′, a delay (or phase/time shift) d exists. That is, the clock signal CK′ has the delay d relative to the data signal D′. The length of the delay d is controlled by the controller 104 via the control signal ctrl.

[0020] In an embodiment, the delay d may be a time difference between an edge (e.g., a rising edge) of the clock signal CK′ and an edge (e.g., a rising edge) of the data signal D′, and not limited thereto.

[0021] In an embodiment, the sampler 106 may be a D flip-flop (DFF), which is illustrated in the upper right portion of FIG. 1. The sampler 106 is coupled to the delay element 102 to receive the data signal D′ and the clock signal CK′. The sampler 106 would generate a sampled data signal D.sub.S according to the data signal D′ and the clock signal CK′.

[0022] The BER determination circuit 108 is coupled to the sampler 106 and may be realized at least by one or more exclusive or gates (XOR). The BER determination circuit 108 is configured to compare the sampled data signal D.sub.S and a predefined test pattern D.sub.P so as to determine whether the sampled data signal D.sub.S is the same as a predefined test pattern D.sub.P, and generate a determination result DR. For illustrative purpose, the determination result DR may, indicates whether or not the sampled data signal D.sub.S is the same as a predefined test pattern D.sub.P, represented by a logic ‘1’ or ‘0’. The determination result DR as a logic ‘0’ may indicate that the sampled data signal D.sub.S is the same as the predefined test pattern D.sub.P; while the determination result DR as a logic ‘1’ may indicate that the sampled data signal D.sub.S is not the same as the predefined test pattern D.sub.P.

[0023] In an embodiment, a data signal D including a series of data bits same as the predefined test pattern Dp may be inputted to the delay element 102. The delay element 102 may generate the second data signals D′ with respect to the different delays d.sub.0-d.sub.N and a plurality of (second) clock signal CK.sub.0′-CK.sub.N′ corresponding to the delays d.sub.0-d.sub.N relative to the data signal D′. The sampler 106 may generate a plurality of sampled data signals D.sub.S,0-D.sub.S,N based on the data signal D′ corresponding to the plurality of delays d.sub.0-d.sub.N. The BER determination circuit 108 may generate a plurality of determination results DR_0-DR_N corresponding to the plurality of delays d.sub.0-d.sub.N according to the plurality of sampled data signals D.sub.S,0-D.sub.S,N, where a determination result DR_n indicates whether a sampled data signal D.sub.S,n is equal to the predefined test pattern D.sub.P, and the BER determination circuit 108 may feed to the determination results DR_0-DR_N to the controller 104. The controller 104 may generate a plurality of control signals ctrl_0-ctrl_N respectively corresponding to a plurality of delays d.sub.0-d.sub.N, to the delay element 102. The controller 104 would determine the timing margin T.sub.MG according to the plurality of determination results DR_0-DR_N corresponding to the plurality of delays d.sub.0-d.sub.N.

[0024] Take N=5 as an example, FIG. 3 illustrates a schematic diagram of waveforms of the (second) data signal D′ and a plurality of (second) clock signals CK.sub.0′-CK.sub.5′. In FIG. 3, the data signal D′ has a rising edge at a time t.sub.R. The clock signals CK.sub.0′-CK.sub.5′ are corresponding to delays d.sub.0-d.sub.5 and have rising edges at times t.sub.0-t.sub.5. The sampler 106 may produce sampled data signals D.sub.S,0-D.sub.S,5 corresponding to the delays d.sub.0-d.sub.5. A delay d.sub.n may be expressed as d.sub.n=t.sub.n−t.sub.R, while the index n herein ranges from 0 to 5. The sampled data signals D.sub.S,0-D.sub.S,5 are inputted to the BER determination circuit 108 for generating a plurality of determination results DR_0-DR_5 corresponding to the plurality of delays d.sub.0-d.sub.5.

[0025] In the embodiment shown in FIG. 3, the data signal D/D′ is supposed to be the same as the predefined test pattern D.sub.P, and in this circumstance, the determination results DR_0-DR_4 indicates that the sampled data signals D.sub.S,0-D.sub.S,4 may be equal to the predefined test pattern D.sub.P, r, and the determination result DR_5 indicates that the sampled data signal D.sub.S,5 may not be equal to the predefined test pattern D.sub.P. Hence, the controller 104 may obtain/approximate the setup time T.sub.SU according to the delays d.sub.0 and d.sub.5, or according to the delays d.sub.0 and d.sub.4.

[0026] Specifically, supposed that a first phase difference between the (first) data signal D and the (first) clock signal CK is equal to a second phase difference between the (second) data signal D′ and the (second) clock signal CK′, which is the delay d.sub.0. The delay d.sub.0 may be regarded as an initial delay, and the control signal ctrl_0 corresponding to the initial delay d.sub.0 may be regarded as initial control signal. In this case, the controller 104 may obtain/approximate the setup time T.sub.SU as T.sub.SU=d.sub.0−d.sub.5 or T.sub.SU=d.sub.0−d.sub.4. In other words, for all the delays d.sub.1-d.sub.5 being less than the initial delay d.sub.0 (i.e., d.sub.n<d.sub.0 ∀ for n=1, . . . ,5), the controller 104 may obtain/approximate the setup time T.sub.SU according to the initial delay d.sub.0 and the delay d.sub.5, the largest delay resulting in a wrong sampled data signal, or according to the initial delay d.sub.0 and the delay d.sub.4, the smallest delay resulting in an correct sampled data signal.

[0027] In addition, the controller 104 may use the same/similar rationale to obtain/approximate the hold time T.sub.H. FIG. 4 also illustrates a schematic diagram of waveforms of the (second) data signal D′ and a plurality of (second) clock signals CK.sub.0′-CK.sub.5′. In FIG. 4, the data signal D′ has a falling edge at a time t.sub.F. The clock signals CK.sub.0′-CK.sub.5′ illustrated in FIG. 4 are corresponding to delays d.sub.0 and d.sub.1′-d.sub.5′ and have rising edges at times t.sub.0 and t.sub.1′-t.sub.5′, where d.sub.n′=t.sub.n′−t.sub.R and t.sub.5′>t.sub.F. The sampled data signals D.sub.S,0 and D.sub.S,1′-D.sub.S,4′ sampled at the times t.sub.0 and t.sub.1′-t.sub.4′, respectively. Under the same circumstance as above, the determination results DR_0 and DR_1′-DR_4′ respectively indicate that the sampled data signals D.sub.S,0 and D.sub.S,1′-D.sub.S,4′ may be equal to the predefined test pattern D.sub.P, and the determination results DR_5′ indicates that the sampled data signal D.sub.S,5′ may not be equal to the predefined test pattern D. The controller 104 may obtain/approximate the hold time T.sub.H according to the delays d.sub.0 and d.sub.5′, or according to the delays d.sub.0 and d.sub.4′. That is, for all the delays d.sub.1′-d.sub.5′ being greater than the initial delay d.sub.0 (i.e., d.sub.n′>d.sub.0 for n=1, . . . ,5), the controller 104 may obtain/approximate the hold time T.sub.H according to the initial delay d.sub.0 and the delay d.sub.5′, the smallest delay resulting in a wrong sampled data signal, or according to the initial delay d.sub.0 and the delay d.sub.4′, the largest delay resulting in a correct sampled data signal.

[0028] From the embodiments in FIG. 3 and FIG. 4, the controller 104 may obtain an eye width T.sub.EW as T.sub.EW=T.sub.SU+T.sub.H, according to the delay d.sub.5 corresponding to the determination result DR_5 and the delay d.sub.5′ corresponding to the determination result DR_5′, for example. Note that, d.sub.5<d.sub.4, . . . ,d.sub.1, d.sub.0, d.sub.1′, . . . ,d.sub.4′<d.sub.5′.

[0029] Compared to the prior art, the timing margin detecting circuit 10 has low circuit complexity and consumes less power.

[0030] Operations of the timing margin detecting circuit 10 can be summarized as a process 50 (timing margin scanning process). As FIG. 5 shows, the process 50 comprises the following steps.

[0031] Step 502: Receive the first data signal D and the first clock signal CK and generate the second data signal D′ and the second clock signal CK′ according a control signal ctrl.

[0032] Step 504: Generate the sampled data signal D.sub.S according to the second data signal D′ and the second clock signal CK′.

[0033] Step 506: Determine whether the sampled data signal D.sub.S is the same as the predefined test pattern D.sub.P and generate the determination result DR accordingly.

[0034] Step 508: Determine the timing margin T.sub.MG according to the determination result DR.

[0035] Notably, the embodiments stated in the above are utilized for illustrating the concept of the present application. Those skilled in the art may make modifications and alterations accordingly, and not limited herein. For example, FIG. 6 is a schematic diagram of a CDR system 2 according to an embodiment of the present application. The CDR system 2 is similar to the CDR system 1, and thus, the same components are denoted by the same symbols. Different from the CDR system 1, the CDR system 2 comprises a timing margin detecting circuit 20 and further comprises a multiplexer 26. The multiplexer 26 would select one of signals, either from the sampler 106 within the timing margin detecting circuit 20, or from the sampler within the CDR circuit 12, and outputs it to a demultiplexer 24. The demultiplexer 24 would receive a clock signal with a reduced clock rate from the frequency divider within the CDR circuit 12. An output of the demultiplexer 24 is fed to the BER determination circuit 108, such that the BER determination circuit 108 may perform the determining operation, either on the result(s) from the data signal D′ and the clock CK′ corresponding to the timing margin detecting circuit 20, or on the result(s) from the data signal D and the clock CK corresponding to the CDR circuit 12, which is also within the scope of the present application.

[0036] Based on the delay d.sub.5 and the delay d.sub.5′, the controller 104 may also obtain information regarding to the timing margin is symmetrical or not, and may select a different bandwidth of the CDR circuit by adjusting the configuration of the equalizer or adjusting the configuration of the charge pump/filter of the CDR circuit 12. By repeatedly processing the timing margin scanning process under different configurations of the equalizer (or the charge pump/filter of the CDR circuit), the controller 104 may obtain different results of timing margin and whether it is symmetrical or not. As a result, the controller 104 may select the most proper configuration of the equalizer (or the charge pump/filter of the CDR circuit) that leads to the greatest timing margin.

[0037] In summary, the present application utilizes the controller to control the delay between the second data signal and the second clock signal. Furthermore, the controller scans over the eye width of the data signal, so as to obtain the timing margin. Compared to the prior art, the present application owns advantages of low circuit complexity and low power consumption.

[0038] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.