Transformer-based doherty power amplifier

Abstract

A transformer-based Doherty power amplifier includes a main power amplifier path and an auxiliary power amplifier path which are connected in parallel. The main power amplifier path includes a main power amplifier, and the auxiliary power amplifier path includes an auxiliary power amplifier. The transformer-based Doherty power amplifier further includes a first linear network circuit or a second linear network circuit. The first linear network circuit is arranged at an input of the main power amplifier and is used to compensate for variations of an input capacitance of the main power amplifier, so as to improve the linearity of the main power amplifier. The second linear network circuit is arranged at an input of the auxiliary power amplifier and is used to compensate for variations of an input capacitance of the auxiliary power amplifier, so as to improve the linearity of the auxiliary power amplifier.

Claims

1. A transformer-based Doherty power amplifier comprising a main power amplifier path and an auxiliary power amplifier path, wherein the main power amplifier path and the auxiliary power amplifier path are connected in parallel; the main power amplifier path comprises a main power amplifier, and the auxiliary power amplifier path comprises an auxiliary power amplifier; the Doherty power amplifier further comprises a first linear network circuit or a second linear network circuit; the first linear network circuit is arranged at an input of the main power amplifier and is used to compensate for variations of an input capacitance of the main power amplifier, so as to improve a linearity of the main power amplifier and accordingly improve a linearity of the Doherty power amplifier; and the second linear network circuit is arranged at an input of the auxiliary power amplifier and is used to compensate for variations of an input capacitance of the auxiliary power amplifier, so as to improve a linearity of the auxiliary power amplifier and accordingly improve the linearity of the Doherty power amplifier; the main power amplifier works in class AB, and the auxiliary power amplifier works in class C and the radio-frequency input signal is a differential signal; wherein the main power amplifier is a differential structure formed by connection of two symmetrical cascode amplifiers, each of the two symmetrical cascode amplifiers is formed by connection of two NMOS transistors, the first linear network circuit is formed by a PMOS transistor connected via a capacitor to the gate of one of the two NMOS transistors, and a gate capacitance of the NMOS transistors at the input of the main power amplifier and a gate capacitance of the PMOS transistors of the first linear network circuit are mutually compensated to stabilize the input capacitance of the main power amplifier; and two first resistors with identical resistances are connected between two differential inputs of the main power amplifier, and a bias voltage applied to a common node of the two first resistors biases the main power amplifier in class AB.

2. The transformer-based Doherty power amplifier according to claim 1, wherein the main power amplifier path further comprises a main driver amplifier, an output of the main driver amplifier is connected to the input of the main power amplifier, a first part of the radio-frequency input signal is accessed to an input of the main driver amplifier, and an output of the main power amplifier outputs a first part of a radio-frequency output signal.

3. The transformer-based Doherty power amplifier according to claim 2, wherein the auxiliary power amplifier path further comprises an auxiliary driver amplifier, an output of the auxiliary driver amplifier is connected to the input of the auxiliary power amplifier, a second part of the radio-frequency input signal is accessed to an input of the auxiliary driver amplifier, and an output of the auxiliary power amplifier outputs a second part of the radio-frequency output signal.

4. The transformer-based Doherty power amplifier according to claim 3, wherein the radio-frequency input signal is accessed to the input of the main driver amplifier via a first transformer.

5. The transformer-based Doherty power amplifier according to claim 4, wherein the output of the main power amplifier outputs the first part of the radio-frequency output signal via a second transformer.

6. The transformer-based Doherty power amplifier according to claim 4, wherein the output of the auxiliary power amplifier outputs the second part of the radio-frequency output signal via a third transformer.

7. The transformer-based Doherty power amplifier according to claim 1, wherein the auxiliary power amplifier is a differential structure formed by connection of two symmetrical cascode amplifiers, each cascode amplifier is formed by connection of two NMOS transistors.

8. The transformer-based Doherty power amplifier according to claim 7, the second linear network circuit is formed by one PMOS transistor to each of the two cascode amplifiers connected via a capacitor, and a gate capacitance of the NMOS transistors at the input of the auxiliary power amplifier and a gate capacitance of the PMOS transistors of the second linear network circuit are mutually compensated to stabilize the input capacitance of the auxiliary power amplifier.

9. The transformer-based Doherty power amplifier according to claim 7, wherein gates of the NMOS transistors, in common-gate connection, of the two cascode amplifiers of the main power amplifier are connected together and are connected to a corresponding bias voltage; and gates of the NMOS transistors, in common-gate connection, of the two cascode amplifiers of the auxiliary power amplifier are connected together and are connected to a corresponding bias voltage.

10. The transformer-based Doherty power amplifier according to claim 9, wherein a gate bias voltage of the NMOS transistors, in common-gate connection, of the cascode amplifiers of the main driver amplifier is equal to that of the NMOS transistors, in common-gate connection, of the cascade amplifiers of the auxiliary driver amplifier; and a first inductor is connected between two differential outputs of the main driver amplifier, a second inductor is connected between two differential outputs of the auxiliary driver amplifier, a center tap of the first inductor is connected to a first power voltage, and a center tap of the second inductor is connected to a second power voltage.

11. The transformer-based Doherty power amplifier according to claim 7, two second resistors with identical resistances are connected between two differential inputs of the auxiliary power amplifier, and a bias voltage applied to a common node of two second resistors biases the auxiliary power amplifier in class C.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) The invention is further expounded below with reference to accompanying drawings and specific embodiments.

(2) FIG. 1 is a structural view of an existing Doherty PA;

(3) FIG. 2 shows input power and output power curves of the structure in FIG. 1;

(4) FIG. 3 shows voltage and impedance curves of a main PA and an auxiliary PA of the structure in FIG. 1 as well as an efficiency curve of the whole Doherty PA;

(5) FIG. 4 shows comparison curves of the existing Doherty PA capable of improving the efficiency in the power back-off region;

(6) FIG. 5 is a structural view of an existing transformer-based Doherty PA;

(7) FIG. 6 is a circuit diagram of one specific implementation of the structure in FIG. 5;

(8) FIG. 7 shows a parasitic capacitance curve of the inputs of a main PA and an auxiliary PA of the circuit structure in FIG. 6;

(9) FIG. 8 is a structural view of a transformer-based Doherty PA in an embodiment of the invention;

(10) FIG. 9 is a structural view of a transformer-based Doherty PA in a preferred embodiment of the invention;

(11) FIG. 10 shows parasitic capacitance curves of the inputs of a main PA and an auxiliary PA of the circuit in the preferred embodiment of the invention in FIG. 9;

(12) FIG. 11 is a comparison diagram of amplitude modulation-phase modulation (AM-PM) distortion curves of the existing circuit structure in FIG. 6 and the circuit structure of the preferred embodiment of the invention in FIG. 9.

DETAILED DESCRIPTION OF THE INVENTION

(13) Existing Transformer-Based Doherty PA:

(14) FIG. 5 is a structural view of an existing transformer-based Doherty PA. As shown in FIG. 5, the existing transformer-based Doherty PA comprises a main PA path and an auxiliary PA path, wherein the main PA path and the auxiliary PA path are connected in parallel.

(15) The main PA path comprises a main PA 302, and the auxiliary PA path comprises an auxiliary PA 304.

(16) The main PA path further comprises a main driver amplifier 301, wherein an output of the main driver amplifier 301 is connected to an input of the main PA 302, a radio-frequency input signal RFIN is accessed to an input of the main driver amplifier 301, and an output of the main PA 302 outputs a radio-frequency output signal RFOUT.

(17) The auxiliary PA path further comprises an auxiliary driver amplifier 303, wherein an output of the auxiliary driver amplifier 303 is connected to an input of the auxiliary PA 304, an input of the auxiliary driver amplifier 303 is connected to the radio-frequency input signal RFIN, and an output of the auxiliary PA 304 outputs the radio-frequency output signal RFOUT.

(18) The main PA 302 works in class AB, and the auxiliary PA 304 works in class C.

(19) The radio-frequency input signal RFIN is accessed to the input of the main driver amplifier 301 via a first transformer T.sub.1. An input of the first transformer T.sub.1 is connected to a capacitor C.sub.1, and an output of the transformer T.sub.1 is connected with a capacitor C.sub.2.

(20) The output of the main PA 302 outputs the radio-frequency output signal RFOUT via a second transformer T.sub.2. An input of the second transformer T.sub.2 is connected to a capacitor C.sub.3.

(21) The output of the auxiliary PA 304 outputs the radio-frequency signal RFOUT via a third transformer T.sub.3. An input of the third transformer T.sub.3 is connected to a capacitor C.sub.4.

(22) The output of the second transformer T.sub.2 has two ports, and the output of the third transformer T.sub.3 also has two ports. One port at the output of the second transformer T.sub.2 is connected to one port at the output of the third transformer T.sub.3. The other port at the output of the second transformer T.sub.2 serves as an output port of the radio-frequency output signal RFOUT. The other port at the output of the third transformer T.sub.3 is grounded. A capacitor C.sub.5 is connected between the port, serving as the output port of the radio-frequency output signal RFOUT, at the output of the second transformer T.sub.2 and the grounded port at the output of the third transformer T.sub.3.

(23) The existing transformer-based Doherty PA shown in FIG. 5 is a novel structure coming into being in recent years, and the working mode of this transformer-based Doherty PA is similar to that of the classic Doherty PA shown in FIG. 1. In spite of the high efficiency in the 6 dB power back-off region, this transformer-based Doherty PA has a poor linearity in the saturated output power region and the power back-off region and thus needs to be optimized.

(24) FIG. 6 shows a circuit diagram of one specific implementation of the structure in FIG. 5. As shown in FIG. 6:

(25) The main PA 302 is a cascode amplifier formed by connection of two NMOS transistors.

(26) The auxiliary PA 304 is a cascode amplifier formed by connection of two NMOS transistors.

(27) The radio-frequency input signal RFIN is a differential signal. The main PA 302 is a differential structure formed by connection of two symmetrical cascode amplifiers. The two cascode amplifiers respectively correspond to a structure formed by connection of NMOS transistors MN.sub.5 and MN.sub.7 and a structure formed by connection of NMOS transistors MN.sub.6 and MN.sub.8.

(28) The auxiliary PA 304 is a differential structure formed by connection of two symmetrical cascode amplifiers. The two cascode amplifiers respectively correspond to a structure formed by connection of NMOS transistors MN.sub.13 and MN.sub.15 and a structure formed by connection of NMOS transistors MN.sub.14 and MN.sub.16.

(29) The main driver amplifier 301 is a differential structure formed by connection of two symmetrical cascode amplifiers.

(30) The auxiliary driver amplifier 303 is a differential structure formed by connection of two symmetrical cascode amplifiers.

(31) Each cascode amplifier of the main driver amplifier 301 is formed by connection of two NMOS transistors. The two cascode amplifiers of the main driver amplifier 301 respectively correspond to a structure formed by connection of NMOS transistors MN.sub.1 and MN.sub.3 and a structure formed by connection of NMOS transistors MN.sub.2 and MN.sub.4.

(32) Each cascode amplifier of the auxiliary driver amplifier 303 is formed by connection of two NMOS transistors. The two cascode amplifiers of the auxiliary driver amplifier 303 respectively correspond to a structure formed by connection of NMOS transistors MN.sub.9 and MN.sub.11 and a structure formed by connection of NMOS transistors MN.sub.10 and MN.sub.12.

(33) The gate bias voltage V.sub.B2 of the NMOS transistors MN.sub.3 and MN.sub.4, in common-gate connection, of the cascode amplifiers of the main driver amplifier 301 is equal to that of the NMOS transistors MN.sub.11 and MN.sub.12, in common-gate connection, of the cascode amplifiers of the auxiliary driver amplifier 303. The gate bias voltage V.sub.B2 is connected to gates of the NMOS transistors MN.sub.3 and MN.sub.4 through a corresponding resistor R.sub.B and is connected to gates of the NMOS transistors MN.sub.11 and MN.sub.12 through a corresponding resistor R.sub.B.

(34) A first inductor L.sub.1 is connected between two differential outputs of the main driver amplifier 301, a second inductor L.sub.2 is connected between two differential outputs of the auxiliary driver amplifier 303, a center tap of the first inductor L.sub.1 is connected to a first power voltage V.sub.DDL, and a center tap of the second inductor L2 is connected to a first power voltage V.sub.DDL.

(35) Two first resistors R.sub.B with identical resistances are connected between two different inputs of the main PA 302 in series, and a bias voltage V.sub.B_AB used to make the two cascode amplifiers of the main PA 302 work in class AB is applied to a joint of the two first resistors R.sub.B.

(36) Two second resistors R.sub.B with identical resistances are connected between two differential inputs of the auxiliary PA 304 in series, and a bias voltage V.sub.B_C used to make the two cascode amplifiers of the auxiliary PA 304 work in class C is applied to a joint of the two second resistors R.sub.B.

(37) Gates of the NMOS transistors MN.sub.7 and MN.sub.8, in common-gate connection, of the two cascode amplifiers of the main PA 302 are connected, and a corresponding bias voltage V.sub.B3 is connected to the gates of the NMOS transistors MN.sub.7 and MN.sub.8 via a corresponding resistor R.sub.B.

(38) Gates of the NMOS transistors MN.sub.15 and MN.sub.16, in common-gate connection, of the two cascode amplifiers of the auxiliary PA 304 are connected, and a corresponding bias voltage V.sub.B4 is connected to the gates of the NMOS transistors MN.sub.15 and MN.sub.16 via a corresponding resistor R.sub.B.

(39) A center tap of an output coil of the first transformer T.sub.1 is connected to a bias voltage V.sub.B1, a center tap of an input coil of the second transformer T.sub.2 is connected to a second power voltage V.sub.DDH, and a center tap of an input coil of the third transformer T.sub.3 is connected to a second power voltage V.sub.DDH.

(40) All resistors are represented by R.sub.B in FIG. 6. However, in practical use, resistance values of the resistors can be correspondingly set as needed.

(41) FIG. 7 shows a parasitic capacitance curve of the inputs of the main PA and the auxiliary PA of the circuit structure in FIG. 6. In FIG. 7, the X-axis refers to gate bias voltage, and the Y-axis refers to capacitance. As for the main PA 302 in FIG. 6, the input of the main PA 302 corresponds to gates of the NMOS transistors MN.sub.5 and MN.sub.6, the gate bias voltage of the main PA 302 corresponds to the bias voltage of the gates of the NMOS transistors MN.sub.5 and MN.sub.6, and the gate parasitic capacitance of the main PA 302 corresponds to the parasitic capacitance CggN of the gates of the NMOS transistors MN.sub.5 and MN.sub.6. Similarly, as for the auxiliary PA 304 in FIG. 6, the gate bias voltage of the auxiliary PA 304 corresponds to the bias voltage of gates of the NMOS transistors MN.sub.13 and MN.sub.14, and the gate parasitic capacitance of the auxiliary PA 304 corresponds to the parasitic capacitance of the gates of the NMOS transistors MN.sub.13 and MN.sub.14. In FIG. 7, curve 401 shows CggN variations of one NMOS transistor, and as can be seen from curve 401, CggN varies along with the variation of the gate bias voltage, and then an input capacitance varies along with the corresponding gate bias voltage. The variation of the input parasitic capacitance is the main factor causing AM-PM distortion, which in turn will directly lead to linearity deterioration.

(42) Transformer-Based Doherty PA in One Embodiment of the Invention:

(43) FIG. 8 is a structural view of a transformer-based Doherty PA in one embodiment of the invention. As shown in FIG. 8, the transformer-based Doherty PA in this embodiment comprises a main PA path and an auxiliary PA path, wherein the main PA path and the auxiliary PA path are connected in parallel.

(44) The main PA path comprises a main PA 302, and the auxiliary PA path comprises an auxiliary PA 304.

(45) The Doherty PA further comprises a first linear network circuit 305 or a second linear network circuit 306.

(46) The first linear network circuit 305 is arranged at an input of the main PA 302 and is used to compensate for variations of an input capacitance of the main PA 302, so as to improve the linearity of the main PA 302 and accordingly improve the linearity of the Doherty PA.

(47) The second linear network circuit 306 is arranged at an input of the auxiliary PA 304 and is used to compensate for variations of an input capacitance of the auxiliary PA 304, so as to improve the linearity of the auxiliary PA 304 and accordingly improve the linearity of the Doherty PA.

(48) Either the first linear network circuit 305 or the second linear network circuit 306 can improve the linearity of the Doherty PA. Preferably, both the first linear network circuit 305 and the second linear network circuit 306 are configured, so that the linearity of the Doherty PA is optimized.

(49) The main PA path further comprises a main driver amplifier 301, wherein an output of the main driver amplifier 301 is connected to the input of the main PA 302, a first part of a radio-frequency input signal RFIN.sub.1 is accessed to an input of the main driver amplifier 301, and an output of the main PA 302 outputs a first part of a radio-frequency output signal RFOUT.sub.1.

(50) The auxiliary PA path further comprises an auxiliary driver amplifier 303, wherein an output of the auxiliary driver amplifier 303 is connected to the input of the auxiliary PA 304, an input of the auxiliary driver amplifier 303 is connected to a second part of a radio-frequency input signal RFIN.sub.2, and an output of the auxiliary PA 304 outputs a second part of a radio-frequency output signal RFOUT.sub.2.

(51) The main PA 302 works in class AB, and the auxiliary PA 304 works in class C.

(52) The radio-frequency input signal RFIN is accessed to the input of the main driver amplifier 301 via a first transformer T.sub.1. An input of the first transformer T.sub.1 is connected to a capacitor C.sub.1, and an output of the first transformer T.sub.1 is connected to a capacitor C.sub.2.

(53) The output of the main PA 302 outputs the radio-frequency output signal RFOUT via a second transformer T.sub.2. An input of the second transformer T.sub.2 is connected to a capacitor C.sub.3.

(54) The output of the auxiliary PA 304 outputs the radio-frequency output signal RFOUT via a third transformer T.sub.3. An input of the third transformer T.sub.3 is connected to a capacitor C.sub.4.

(55) An output of the second transformer T.sub.2 has two ports, and an output of the third transformer T.sub.3 also has two ports. One port at the output of the second transformer T.sub.2 is connected to one port at the output of the third transformer T.sub.3. The other port at the output of the second transformer T.sub.2 serves as an output port of the radio-frequency output signal RFOUT. The other port at the output of the third transformer T.sub.3 is grounded. A capacitor C.sub.5 is connected between the port, serving as the output port of the radio-frequency output signal RFOUT, at the output of the second transformer T.sub.2 and the grounded port at the output of the third transformer T.sub.3.

(56) In this embodiment, the first linear network circuit 305 is arranged at the input of the main PA 302 or the second linear network circuit 306 is arranged at the input of the auxiliary PA 304 to compensate for the input capacitance of the input of the main PA 302 or to compensate for the input capacitance of the input of the auxiliary PA 304, so that the variation of the input capacitance is reduced when the input signal varies, that is to say, the input capacitance is kept stable, so that AM-PM distortion is reduced, and the linearity of the Doherty PA is improved.

(57) Transformer-Based Doherty PA in a Preferred Embodiment of the Invention:

(58) FIG. 9 is a structural view of a transformer-based Doherty PA in a preferred embodiment of the invention. The structure in FIG. 9 is obtained by further improvement on the structure in FIG. 8. In this preferred embodiment of the invention:

(59) The main PA 302 is a cascode amplifier formed by connection of two NMOS transistors. The first linear network circuit 305 is formed by PMOS transistors connected via a capacitor. The gate capacitance of the NMOS transistors at the input of the main PA 302 and the gate capacitance of the PMOS transistors of the first linear network circuit 305 are mutually compensated to stabilize the input capacitance of the main PA 302.

(60) The auxiliary PA 304 is a cascode amplifier formed by connection of two NMOS transistors. The second linear network circuit 306 is formed by PMOS transistors connected via a capacitor. The gate capacitance of the NMOS transistors at the input of the auxiliary PA 304 and the gate capacitance of the PMOS transistors of the second linear network circuit 306 are mutually compensated to stabilize the input capacitance of the auxiliary PA 304.

(61) The radio-frequency input signal RFIN is a differential signal. The main PA 302 is a differential structure formed by connection of two symmetrical cascode amplifiers. The two cascode amplifiers of the main PA 302 respectively correspond to a structure formed by connection of NMOS transistors MN.sub.5 and MN.sub.7 and a structure formed by connection of NMOS transistors MN.sub.6 and MN.sub.8. The first linear network circuit 305 comprises two PMOS transistors MP.sub.1 and MP.sub.2. Each PMOS transistor of the first linear network circuit 305 corresponds to the NMOS transistor at an input of one cascode amplifier of the main PA 302. Particularly, the PMOS transistor MP.sub.1 corresponds to the NMOS transistor MN.sub.5, and the PMOS transistor MP.sub.2 corresponds to the NMOS transistor MN.sub.6. A gate of the PMOS transistor MP.sub.1 is connected to a gate of the NMOS transistor MN.sub.5. A gate of the PMOS transistor MP.sub.2 is connected to a gate of the NMOS transistor MN.sub.6. A source and drain of the PMOS transistor MP.sub.1 as well as a source and drain of the PMOS transistor MP.sub.2 are connected to a voltage V.sub.PC1.

(62) The auxiliary PA 304 is a differential structure formed by connection of two symmetrical cascode amplifiers. The two cascode amplifiers of the auxiliary PA 304 respectively correspond to a structure formed by connection of NMOS transistors MN.sub.13 and MN.sub.15 and a structure formed by connection of NMOS transistors NM.sub.14 and MN.sub.16. The second linear network circuit 306 comprises two PMOS transistors MP.sub.3 and MP.sub.4. Each PMOS transistor of the second linear network circuit 306 corresponds to the NMOS transistor at an input of one cascode amplifier of the auxiliary PA 304. Particularly, the PMOS transistor MP.sub.3 corresponds to the NMOS transistor MN.sub.13, and the PMOS transistor MP.sub.4 corresponds to the NMOS transistor MN.sub.14. A gate of the PMOS transistor MP.sub.3 is connected to a gate of the NMOS transistor MN.sub.13. A gate of the PMOS transistor MP.sub.4 is connected to a gate of the NMOS transistor MN.sub.14. A source and drain of the PMOS transistor MP.sub.3 as well as a source and drain of the PMOS transistor MP.sub.4 are connected to a voltage V.sub.PC2.

(63) The main driver amplifier 301 is a differential structure formed by connection of two symmetrical cascode amplifiers.

(64) The auxiliary driver amplifier 303 is a differential structure formed by connection of two symmetrical cascode amplifiers.

(65) Each cascode amplifier of the main driver amplifier 301 is formed by connection of two NMOS transistors. The two cascode amplifiers of the main driver amplifier 301 respectively correspond to a structure formed by connection of NMOS transistors MN.sub.1 and MN.sub.3 and a structure formed by connection of NMOS transistors MN.sub.2 and MN.sub.4.

(66) Each cascode amplifier of the auxiliary driver amplifier 303 is formed by connection of two NMOS transistors. The two cascode amplifiers of the auxiliary driver amplifier 303 respectively correspond to a structure formed by connection of NMOS transistors MN.sub.9 and MN.sub.11 and a structure formed by connection of NMOS transistors MN.sub.10 and MN.sub.12.

(67) The gate bias voltage V.sub.B2 of the NMOS transistors MN.sub.3 and MN.sub.4, in common-gate connection, of the cascode amplifiers of the main driver amplifier 301 is equal to that of the NMOS transistors MN.sub.11 and MN.sub.12, in common-gate connection, of the cascode amplifiers of the auxiliary driver amplifier 303. The gate bias voltage V.sub.B2 is connected to gates of the NMOS transistors MN.sub.3 and MN.sub.4 via a corresponding resistor R.sub.B and is connected to gates of the NMOS transistors MN.sub.11 and MN.sub.12 via a corresponding resistor R.sub.B.

(68) A first inductor L.sub.1 is connected between two differential outputs of the main driver amplifier 301. A second inductor L.sub.2 is connected between two differential outputs of the auxiliary driver amplifier 303. A center tap of the first inductor L.sub.1 is connected to a first power voltage V.sub.DDL. A center tap of the second inductor L.sub.2 is connected to a first power voltage V.sub.DDL.

(69) Two first resistors R.sub.B with identical resistances are connected between two differential inputs of the main PA 302 in series, and a bias voltage V.sub.B_AB used to make the two cascode amplifiers of the main PA 302 work in class AB is applied to a joint of the two first resistors R.sub.B.

(70) Two second resistors R.sub.B with identical resistances are connected between two differential inputs of the auxiliary PA 304 in series, and a bias voltage V.sub.B_C used to make the two cascode amplifiers of the auxiliary PA 304 work in class C is applied to a joint of the two second resistors R.sub.B.

(71) Gates of the NMOS transistors MN.sub.7 and MN.sub.8, in common-gate connection, of the two cascode amplifiers of the main PA 302 are connected, and a corresponding bias voltage V.sub.B3 is connected to the gates of the NMOS transistors MN.sub.7 and MN.sub.8 via a corresponding resistor R.sub.B.

(72) Gates of the NMOS transistors MN.sub.15 and MN.sub.16, in common-gate connection, of the two cascode amplifiers of the auxiliary PA 304 are connected, and a corresponding bias voltage V.sub.B4 is connected to the gates of the NMOS transistors MN.sub.15 and MN.sub.16 via a corresponding resistor R.sub.B.

(73) A center tap of an output coil of the first transformer T.sub.1 is connected to a bias voltage V.sub.B1. A center tap of an input coil of the second transformer T.sub.2 is connected to a second power voltage V.sub.DDH. A center tap of an input coil of the third transformer T.sub.3 is connected to a second power voltage V.sub.DDH.

(74) All resistors are represented by R.sub.B in FIG. 9. In practical use, resistance values of the resistors can be correspondingly set as needed.

(75) FIG. 8 is obtained by further improvement on FIG. 5, and in FIG. 5 and FIG. 8, identical components are represented by identical reference signs. FIG. 9 is obtained by further improvement on FIG. 6, and in FIG. 6 and FIG. 9, identical components are represented by identical reference signs.

(76) FIG. 10 shows parasitic capacitance curves of the inputs of the main PA and the auxiliary PA of the circuit in the preferred embodiment of the invention shown in FIG. 9. In FIG. 10, the X-axis refers to gate bias voltage, and the Y-axis refers to capacitance. Similar to curve 401 in FIG. 6, curve 502 is about CggN variations of one NMOS transistor. Curve 501 is a variation curve of the gate parasitic capacitance CggP of one of the PMOS transistors MP.sub.1, MP.sub.2, MP.sub.3 and MP.sub.4. Curve 503 is formed by superposition of curve 501 and curve 502, namely curve 503 is a variation curve of the overall input capacitance obtained by superposition of CggP and CggN. As can be seen from FIG. 10, the variation of CggP and the variation of CggN are compensated by each other. Curve 503 is kept stable, and the overall input capacitance will not drastically fluctuate when the gate bias voltage varies. Therefore, the transformer-based Doherty PA in this preferred embodiment of the invention can reduce AM-PM distortion, thus, improving the linearity of circuits.

(77) FIG. 11 is a comparison diagram of AM-PM distortion curves of the existing circuit structure in FIG. 6 and the circuit structure of the preferred embodiment of the invention in FIG. 9, wherein curve 601 is an AM-PM distortion curve of the circuit structure in this preferred embodiment of the invention, and curve 602 is an AM-PM distortion curve of the existing circuit structure. As can be seen from FIG. 11, the transformer-based Doherty PA in this preferred embodiment of the invention can reduce AM-PM distortion.

(78) The invention is detailed above with reference to specific embodiments, but these specific embodiments are not intended to limit the invention. Various transformations and improvements can be made by those skilled in this field without deviating from the principle of the invention, and all these transformations and improvements should also fall within the protection scope of the invention.