Power-on-reset circuit and corresponding electronic device

Abstract

An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

Claims

1. A power-on-reset (POR) circuit, comprising: a power supply input configured to receive a power supply voltage; a proportional to absolute temperature (PTAT) stage having a left branch and a right branch and configured to generate a current equilibrium condition between currents circulating in the left and right branches upon the power supply voltage reaching a POR detection level; an output stage, coupled to the PTAT stage and configured to generate a reset signal with a value switching at an occurrence of the current equilibrium condition for the PTAT stage; and a detection-level generation stage, coupled to the PTAT stage as a central branch thereof and configured to define the value of the POR detection level.

2. The POR circuit according to claim 1, wherein the detection-level generation stage is configured to generate the value of the POR detection level, switching between a high and a low level, both higher than a bandgap reference voltage, upon switching of the reset signal.

3. The POR circuit according to claim 1, wherein the detection-level generation stage comprises a central resistor element coupled between the power supply input and a central node, a semiconductor-junction element coupled in series to the central resistor element and a current-injection resistor element coupled in parallel to the semiconductor-junction element so that, during operation, a semiconductor junction voltage is applied thereon; and wherein the detection-level generation stage is configured to define the value of the POR detection level based on a voltage drop on the central resistor element due to a sum of an equilibrium current in the left and right branches of the PTAT stage at the current equilibrium condition and of a further current configured to be injected in the central resistor element through the current-injection resistor element.

4. The POR circuit according to claim 3, wherein the detection-level generation stage is configured to define the value of the POR detection level as a sum of the voltage drop on the central resistor element and of the semiconductor junction voltage.

5. The POR circuit according to claim 3, wherein the central resistor element and the current-injection resistor element have respective resistance values that are variable based on the value of the reset signal, and wherein switching of the value of the reset signal determines switching of the resistance values of the central resistor element and the current-injection resistor element from a respective first value to a respective second value, different from the respective first value.

6. The POR circuit according to claim 3, wherein the left branch of the PTAT stage comprises: a first current-mirror transistor, coupled between the power supply input and a first internal node and arranged in a diode configuration, wherein a left-branch current flows through the first current-mirror transistor at the first internal node; and a bipolar load transistor coupled between the first internal node and a reference terminal; and wherein the right branch of the PTAT stage comprises: a respective current-mirror transistor, coupled between the power supply input and a respective first internal node and having a gate terminal coupled to a gate terminal of the first current-mirror transistor, wherein a right-branch current flows through the respective current-mirror transistor at the respective first internal node; and a bipolar respective load transistor having a collector terminal coupled to the respective first internal node, a base terminal coupled to a base terminal of the load transistor of the left branch, and an emitter terminal coupled to the reference terminal through a load resistor element; wherein the respective load transistor of the right branch has a form-factor that is n-times higher than that of the load transistor of the left branch, with n being higher than one.

7. The POR circuit according to claim 6, wherein the semiconductor-junction element of the detection-level generation stage is a bipolar transistor element in a diode-configuration having a collector terminal coupled to the central resistor element and a base terminal coupled to the current-injection resistor element and to the base terminals of the load transistors of the left and right branches; and wherein the semiconductor junction voltage is the voltage drop between the base and emitter terminals of the bipolar transistor element and the further current configured to be injected in the central resistor element through the current-injection resistor element is given by V.sub.BE/R.sub.x, where V.sub.BE is the semiconductor junction voltage and R.sub.x the resistance value of the current-injection resistor element.

8. The POR circuit according to claim 7, wherein the bipolar transistor element of the detection-level generation stage has a respective form-factor that is m-times higher than that of the load transistor of the left branch, with m being higher than one.

9. The POR circuit according to claim 6, wherein the load resistor element has a respective resistance value which is variable based on the value of the reset signal, and wherein switching of the value of the reset signal determines switching of the resistance value of the load resistor element from a respective first value to a respective second value, different from the respective first value.

10. The POR circuit according to claim 6, wherein the PTAT stage further comprises a compensation capacitor coupled between a collector terminal of the load transistor of the left branch and the central node of the detection-level generation stage.

11. The POR circuit according to claim 6, wherein the PTAT stage comprises, both in the left branch and in the right branch, a respective cascode transistor, coupled between the respective first internal node and the collector terminal of the respective load transistor, wherein the cascode transistors have gate terminals coupled together and to the central node of the detection-level generation stage.

12. The POR circuit according to claim 6, wherein the output stage comprises a comparator unit having a first comparison input coupled to the right branch of the PTAT stage and configured to receive a right-branch voltage and a second comparison input coupled to the left branch of the PTAT stage and configured to receive a left-branch voltage; and wherein the left-branch voltage and the right-branch voltage are configured to have a same value at the current equilibrium condition of the PTAT stage.

13. The POR circuit according to claim 12, wherein the gate terminal of the respective current-mirror transistor of the right branch of the PTAT stage is configured to receive a biasing voltage; and wherein the second comparison input of the comparator unit is coupled to the first internal node of the left branch of the PTAT stage to receive the biasing voltage as the left-branch voltage, and the first comparison input of the comparator unit is coupled to the first internal node of the right branch of the PTAT stage to receive a PTAT output voltage as the right-branch voltage.

14. The POR circuit according to claim 12, wherein the output stage further comprises a Schmitt trigger unit coupled at an output terminal of the comparator unit and configured to provide the reset signal as a function of an output voltage of the comparator unit.

15. The POR circuit according to claim 12, wherein the comparator unit comprises: a PMOS first comparator transistor coupled between the power supply input and an output terminal and having a gate terminal coupled to the second comparison input; a PMOS second comparator transistor coupled between the power supply input and a comparator internal node and having a gate terminal coupled to the first comparison input; an NMOS third comparator transistor coupled between the output terminal and the reference terminal, with a gate terminal coupled to the comparator internal node; and an NMOS fourth comparator transistor coupled between the comparator internal node and the reference terminal, with a gate terminal coupled to the same comparator internal node, thus being arranged in a diode-configuration.

16. An electronic device comprising: a power supply generator configured to provide a power supply voltage; a power-on-reset (POR) circuit comprising: a power supply input configured to receive the power supply voltage; a proportional to absolute temperature (PTAT) stage having a left branch and a right branch and configured to generate a current equilibrium condition between currents circulating in the left and right branches upon the power supply voltage reaching a POR detection level; an output stage, coupled to the PTAT stage and configured to generate a reset signal with a value switching at an occurrence of the current equilibrium condition for the PTAT stage; and a detection-level generation stage, coupled to the PTAT stage as a central branch thereof and configured to define the value of the POR detection level; and electronic circuitry, coupled to the POR circuit and configured to: receive the reset signal; activate a power-on sequence of operations when the reset signal switches to a first value; and stop operations when the reset signal switches to a second value.

17. The electronic device according to claim 16, wherein the electronic device is a stand-alone memory device.

18. The electronic device according to claim 16, wherein the detection-level generation stage is configured to generate the value of the POR detection level, switching between a high and a low level, both higher than a bandgap reference voltage, upon switching of the reset signal.

19. The electronic device according to claim 16, wherein the detection-level generation stage comprises a central resistor element coupled between the power supply input and a central node, a semiconductor-junction element coupled in series to the central resistor element and a current-injection resistor element coupled in parallel to the semiconductor-junction element so that, during operation, a semiconductor junction voltage is applied thereon; and wherein the detection-level generation stage is configured to define the value of the POR detection level based on a voltage drop on the central resistor element due to a sum of an equilibrium current in the left and right branches of the PTAT stage at the current equilibrium condition and of a further current configured to be injected in the central resistor element through the current-injection resistor element.

20. The electronic device according to claim 19, wherein the left branch of the PTAT stage comprises: a first current-mirror transistor, coupled between the power supply input and a first internal node and arranged in a diode configuration, wherein a left-branch current flows through the first current-mirror transistor at the first internal node; and a bipolar load transistor coupled between the first internal node and a reference terminal; and wherein the right branch of the PTAT stage comprises: a respective current-mirror transistor, coupled between the power supply input and a respective first internal node and having a gate terminal coupled to a gate terminal of the first current-mirror transistor, wherein a right-branch current flows through the respective current-mirror transistor at the respective first internal node; and a bipolar respective load transistor having a collector terminal coupled to the respective first internal node, a base terminal coupled to a base terminal of the load transistor of the left branch, and an emitter terminal coupled to the reference terminal through a load resistor element; wherein the respective load transistor of the right branch has a form-factor that is n-times higher than that of the load transistor of the left branch, with n being higher than one.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:

(2) FIG. 1 shows a circuit diagram of a power-on-reset circuit, according to an embodiment of the present solution;

(3) FIGS. 2A-2B show plots of a power supply provided to the circuit of FIG. 1 and of a POR signal generated at the output of the same circuit of FIG. 1;

(4) FIG. 3 is a schematic block diagram of the POR circuit 1 of FIG. 1; and

(5) FIG. 4 is a schematic block diagram of an electronic device, comprising the circuit of FIG. 1.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(6) As will be discussed in detail in the following, an embodiment of the present solution provides a power-on-reset circuit based on a PTAT (Proportional To Absolute Temperature) stage, being configured to achieve POR detection levels higher than the bandgap voltage of silicon, envisaging minimum static power consumption and a high response speed.

(7) The POR circuit may for example be used in stand-alone memory devices, such as Flash non-volatile memories.

(8) As shown in FIG. 1, the POR circuit, generally denoted with 1, comprises a PTAT generator stage 2, having a power supply input 3 coupled to a power supply unit (here not shown), providing a power supply voltage V.sub.cc having an extended range of variability (e.g., in the range comprised between 1.6 V and 3.6 V).

(9) The PTAT stage 2 is based on the principle of equilibrium of currents between a left branch 4a and a right branch 4b thereof, the left branch 4a including: a current-mirror transistor 5a, of the PMOS type, coupled between the power supply input 3 and a first internal node 6a and arranged in a diode configuration, i.e. having the gate terminal coupled to the drain terminal thereof (both terminals being coupled to the first internal node 6a), wherein a left-branch current I.sub.C1 flows through the current-mirror transistor 5a at the first internal node 6a; a cascode transistor 7a, of the NMOS type, coupled between the first internal node 6a and a second internal node 8a; and a load transistor 9a, of the bipolar type, coupled between the second internal node 8a and a reference terminal (in particular a ground terminal, GND).

(10) The right branch 4b of the PTAT stage 2 includes: a respective current-mirror transistor 5b, of the PMOS type, coupled between the power supply input 3 and a respective first internal node 6b (representing an output node of the PTAT generator stage 2, providing a PTAT output voltage V.sub.pout) and having the gate terminal coupled to the gate terminal of the current-mirror transistor 5a, wherein a right-branch current I.sub.C2 flows through the current-mirror transistor 5b at the respective first internal node 6b; a respective cascode transistor 7b, of the NMOS type, coupled between the respective first internal node 6b and a respective second internal node 8b and having the gate terminal coupled to the gate terminal of the cascode transistor 7a; a respective load transistor 9b, of the bipolar type, having the collector terminal coupled to the respective second internal node 8b and having the base terminal coupled to the base terminal of load transistor 9a; and, moreover, a load resistor 10, having a resistance R.sub.E, coupled between the emitter terminal of the load transistor 9b and the reference terminal GND.

(11) In particular, load transistor 9b of the second branch 4b has a form-factor, which is n-times higher than that of load transistor 9a of the first branch 4a, with n higher than one (in a possible implementation, load transistor 9b is constituted by the parallel of n unitary transistors with same form factor as the load transistor 9a); a biasing voltage V.sub.a1 is present at gate terminals of current-mirror transistors 5a, 5b; and a cascode voltage V.sub.c is present at gate terminals of the cascode transistors 7a, 7b.

(12) The POR circuit 1 further comprises an output comparator 12, having: a first comparison input 12a, coupled to the output terminal of the PTAT stage 2 (i.e. to the respective first terminal 6b of the second branch 4b) and receiving the PTAT output voltage V.sub.pout; a second comparison input 12b, coupled to the gate terminals of the current-mirror transistors 5a, 5b (i.e. to the first terminal 6a of the first branch 4a) and receiving the biasing voltage V.sub.a1; and an output terminal 12C providing an output detection voltage V.sub.det, dependent on the values of the PTAT output voltage V.sub.pout and the biasing voltage V.sub.a1 (in particular on the difference thereof).

(13) The output comparator 12 comprises: a first comparator transistor 14a, of the PMOS type, coupled between the power supply input 3 and the output terminal 12C and having gate terminal coupled to the second comparison input 12b and receiving the biasing voltage V.sub.a1; a second comparator transistor 14b, of the PMOS type, coupled between the power supply input 3 and a comparator internal node 15 and having gate terminal coupled to the first comparison input 12a and receiving the PTAT output voltage V.sub.pout; a third comparator transistor 14c, of the NMOS type, coupled between the output terminal 12C and the reference terminal GND, with gate terminal coupled to the comparator internal node 15; and a fourth comparator transistor 14d, of the NMOS type, coupled between the comparator internal node 15 and the reference terminal GND, with gate terminal coupled to the same comparator internal node 15 (the fourth comparator transistor 14d being arranged in a diode-configuration).

(14) In the embodiment shown in FIG. 1, the POR circuit 1 moreover comprises an output Schmitt trigger 16, having an input coupled to the output terminal 12C of the output comparator 12 and receiving the output detection voltage V.sub.det and an output providing a reset signal POR, of a pulse type, switching between a first, e.g., low, to a second, e.g., high, value (the reset signal POR being provided, in a manner here not shown, to external circuitry of an associated electronic device, e.g., to perform operations according to a power-on sequence).

(15) According to a particular aspect of the present solution, the POR circuit 1 further comprises a POR-detection-level generation branch, which constitutes a central branch for the above PTAT stage 2 (thus referred to in the following as central branch 20), between the left branch 4a and the right branch 4b.

(16) In particular, the central branch 20 comprises: a central resistor 22, having resistance R.sub.C, coupled between the power supply input 3 (and the collector terminals of the current-mirror transistors 5a, 5b) and a central node 23 (which is also coupled to the gate terminals of the cascode transistors 7a, 7b), with a central-branch current I.sub.O flowing through the central resistor 22; and a central transistor 24, of the bipolar type and in a diode-configuration (with base terminal connected to the collector terminal thereof), coupled in series to the central resistor 22, between the central node 23 and the reference terminal GND, having base terminal coupled to the respective base terminals of load transistors 9a, 9b of the left and right branches 4a, 4b.

(17) In particular, central transistor 24 has a form-factor, which is m-times higher than that of load transistor 9a (with m higher than one); in a possible implementation, central transistor 24 is constituted by the parallel of m unitary transistors (with same form factor as the load transistor 9a).

(18) The POR circuit 1 further comprises: a compensation capacitor 26, arranged between the second internal node 8a of the left branch 4a of the PTAT stage 2 and the central node 23 of central branch 20 (and the base terminals of load transistors 9a, 9b and central transistor 24); and, according to a particular aspect of the present solution, a current-injection resistor 28, with resistance R.sub.X, coupled between the same central node 23 (and the base terminal of the central transistor 24) and the reference terminal GND, therefore being arranged in parallel to the base-emitter semiconductor junction of the central transistor 24.

(19) According to a further aspect of the present solution, the load resistor 10, the central resistor 22 and the current-injection resistor 28 have respective resistance values R.sub.E, R.sub.C and R.sub.X, which are variable based on the value of the reset signal POR. In other words, switching of the value of the reset signal POR from a first (e.g., high) to a second (e.g., low) value determines switching of the resistance values R.sub.E, R.sub.C and R.sub.X from a respective first value to a respective second value, different from the respective first value.

(20) General operation of the POR circuit 1 envisages generation of the reset signal POR based on the current equilibrium condition of the PTAT stage 2, i.e. I.sub.C1=I.sub.C2=I.sub.C (in particular, switching of the same reset signal POR at the occurrence of the equilibrium condition), and definition of the desired high and low POR detection levels V.sub.PORH, V.sub.PORL of the POR detection voltage V.sub.POR (both higher than the semiconductor bandgap voltage) exploiting the injection of a further current in the central branch 20 through the current-injection resistor 28, wherein the above current equilibrium condition is designed to occur when the power supply V.sub.cc crosses the high or low POR detection levels V.sub.PORH, V.sub.PORL.

(21) Upon power-on, when the power supply voltage V.sub.cc starts to increase, as schematically shown in FIG. 2A at t.sub.o, the central-branch current I.sub.O flowing through the central resistor 22 also starts increasing, as a function of the same power supply voltage V.sub.cc, generating the base-emitter polarization V.sub.BE in the central transistor 24.

(22) This increase continues until the detection point of the PTAT stage 2, when the current equilibrium condition I.sub.c1=I.sub.c2=I.sub.C occurs; at this moment, again due to the PTAT equilibrium condition, it is also verified the equilibrium of voltages at the first internal nodes 6a, 6b of the left and right branches 4a, 4b, i.e. V.sub.a1=V.sub.pout (the biasing voltage V.sub.a1 being substantially equal to the PTAT output voltage V.sub.pout), causing the output detection voltage V.sub.det provided by the output comparator 12 to switch its value (for example, from a previous high value to a low value). This consequently triggers the output Schmitt trigger 16, which provides at the output the reset signal POR (as shown in FIG. 2B: in the example, the reset signal POR switches from a low to a high value, when the power supply voltage crosses the high POR detection level V.sub.PORH).

(23) Triggering of the reset signal POR also causes switching of the resistance values R.sub.E, R.sub.C and R.sub.X of the load resistor 10, the central resistor 22 and the current-injection resistor 28 from the respective first value to the respective second value, determining a corresponding shift of the POR detection level to the low level V.sub.PORL. It is therefore underlined that, when the reset signal POR has yet to switch, the above resistances are sized to achieve the high POR detection level V.sub.PORH and when the reset signal POR has already switched, the same resistances are set to achieve the low POR detection level V.sub.PORL.

(24) Afterwards (and again as shown in FIGS. 2A, 2B), only when the power supply voltage V.sub.cc moves below the same low POR detection level V.sub.PORL, the output detection voltage V.sub.det provided by the output comparator 12 switches again its value (in particular, from the previous low value to the high value) consequently triggering the output Schmitt trigger 16 and causing the reset signal POR to switch back to the low level.

(25) It is noted that hysteresis on the POR detection level is generated always assuring temperature compensation, i.e. the high and low POR detection levels V.sub.PORH and V.sub.PORL are both compensated in temperature (both being based on the PTAT equilibrium condition of the PTAT stage 2).

(26) It is furthermore noted that the role of cascode transistors 7a, 7b is to increase the comparator gain, the cascode operation allowing generation of well defined threshold points for POR detection.

(27) Moreover, compensation capacitor 26 allows balancing the Miller effect at the start of the operation; in particular, during ramp-up of power supply voltage V.sub.cc, the presence of the compensation capacitor 26 guarantees a systematic high value for the POR detection level (and thus a secure commutation of the POR detection level for any V.sub.cc slope).

(28) A more detailed disclosure of the operation of the POR circuit 1 is now presented, first considering basic known bipolar equations for the bipolar transistors:

(29) $I_C={\beta }_F.Math.I_B;$$I_E=I_C.Math.\frac{{\beta }_F}{1+{\beta }_F};$$I_C=I_S.Math.e^{\frac{V_{\mathrm{BE}}}{V_T}},I_S\sim A_E\left(\mathrm{emitter}\mathrm{area}\right);$$V_T=\frac{K.Math.T}{q}\approx 25\mathrm{mV}\mathrm{at}{25}^{\circ }C.$

(30) The POR detection voltage V.sub.POR, i.e. the voltage at the the power supply input 3, can be expressed as:
V.sub.POR−I.sub.O.Math.R.sub.C+V.sub.BE  (1)

(31) considering the voltage drop on the central resistor 22 due to the central-branch current I.sub.O and also the base emitter voltage V.sub.BE of the central transistor 24 (it is noted that most of the consumption of the POR circuit 1 is conveyed in the central branch 20, due to the same central-branch current I.sub.O).

(32) Considering the currents at central node 23 and that the equilibrium condition I.sub.C1=I.sub.C2=I.sub.C (I.sub.C being the equilibrium current) is equivalent to I.sub.B1=I.sub.B2=I.sub.B (where I.sub.B1 and I.sub.B2 are the base currents of load transistors 9a, 9b, which therefore operate base on a same base current), it may be shown that:

(33) $\begin{array}{cc}{I}_O=m.Math.I_C+\left(m+2\right).Math.I_B+\frac{V_{\mathrm{BE}}}{R_x}.fwdarw.I_O=I_C.Math.B+\frac{V_{\mathrm{BE}}}{R_x}& \left(2\right)\end{array}$
wherein:

(34) $\begin{array}{cc}B=\left(m+\frac{m+2}{{\beta }_F}\right)& \left(3\right)\end{array}$

(35) Central-branch current I.sub.O therefore is given by the sum of two factors, one due to the equilibrium current I.sub.C (which is a function of the power supply voltage V.sub.cc) and the other due to the further current injected through the current-injection resistor 28.

(36) Accordingly, the above expression (i) can be rewritten as:

(37) $\begin{array}{cc}{V}_{\mathrm{POR}}=\left(I_C.Math.B+\frac{V_{\mathrm{BE}}}{R_x}\right).Math.R_C+V_{\mathrm{BE}}& \left(4\right)\end{array}$

(38) Moreover, from the PTAT equilibrium condition it follows that:

(39) $\begin{array}{cc}{I}_C=\frac{V_{\mathrm{BE}1}-V_{\mathrm{BE}2}}{R_E}=\frac{\Delta V_{\mathrm{BE}}}{R_E}=\frac{V_T}{R_E}.Math.\left(\ln \frac{I_{S2}}{I_{S1}}\right)=\frac{V_T}{R_E}.Math.\ln n& \left(5\right)\end{array}$

(40) (where V.sub.BE1 and V.sub.BE are the respective base-emitter voltages of load transistors 9a, 9b and ΔV.sub.BE the difference between the same respective base-emitter voltages).

(41) Setting M=In n, it follows that:

(42) $\begin{array}{cc}{I}_C=\frac{V_T}{R_E}.Math.M& \left(6\right)\end{array}$
and therefore, rewriting expression (4):

(43) $\begin{array}{cc}{V}_{\mathrm{POR}}=V_T.Math.\frac{R_C}{R_E}.Math.M.Math.B+V_{\mathrm{BE}}.Math.\left(\frac{R_C}{R_X}+1\right)& \left(7\right)\end{array}$

(44) From the above expression (7) it is clear that the V.sub.BE value (i.e. the bandgap voltage of the semiconductor material ˜1.25 V) is amplified by a resistive ratio (R.sub.C/R.sub.x+1), allowing POR detection values above the bandgap voltage to be obtained (which are dependent on the resistance values R.sub.E, R.sub.C and R.sub.X of the load resistor 10, the central resistor 22 and the current-injection resistor 28).

(45) It is again noted that the POR detection level shift above the bandgap voltage is obtained thanks to the injection of the current V.sub.BE/R.sub.X in the central resistor 22 (via the current-injection resistor 28); moreover, from the above expression (7), it is clear that the two components associated with V.sub.T (the thermal voltage) and V.sub.BE (the base emitter voltage) can be combined through independent coefficients, thanks to the presence of the same current-injection resistor 28, in order to jointly provide the POR detection voltage V.sub.POR.

(46) A condition of independency from temperature (∂V.sub.pOR/∂T=O) may now be imposed in expression (7), also considering the following expressions:

(47) $V_T=\frac{K.Math.T}{q}=h.Math.T,\mathrm{with}h\sim 0.087\mathrm{mV}/°K$$\frac{\partial V_{\mathrm{BE}}}{\partial T}=-2\mathrm{mV}/°K=b$

(48) Starting from the above expression (7) and considering the hypothesis ∂B/∂T˜0, the following is obtained:

(49) $\begin{array}{cc}\frac{\partial V_{\mathrm{POR}}}{\partial T}=h.Math.\frac{R_C}{R_E}.Math.M.Math.B+\left(\frac{R_C}{R_X}+1\right).Math.b=0\left(\frac{R_C}{R_X}+1\right)=-\frac{h.Math.M.Math.B}{b}.Math.\frac{R_C}{R_E}& \left(8\right)\end{array}$

(50) This expression (8) may be replaced in the above expression (7), obtaining:

(51) 0$\begin{array}{cc}{V}_{\mathrm{POR}}=V_T.Math.\frac{R_C}{R_E}.Math.M.Math.B-V_{\mathrm{BE}}.Math.\frac{h.Math.M.Math.B}{b}.Math.\frac{R_C}{R_E}=\frac{R_C}{R_E}.Math.M.Math.B\left(V_T-V_{\mathrm{BE}}.Math.\frac{h}{b}\right)& \left(9\right)\end{array}$
and thus:

(52) $\begin{array}{cc}\frac{R_C}{R_E}.Math.M.Math.B=\frac{V_{\mathrm{POR}}}{\left(V_T-V_{\mathrm{BE}}.Math.\frac{h}{b}\right)}& \left(10\right)\end{array}$

(53) As will be discussed in the following, the above expression (10) may be used for designing the POR circuit (1) and in particular, for determining the R.sub.C/R.sub.E resistance ratio value, also taking into account the consumption of the POR circuit 1.

(54) Combining above expressions (8) and (10), it also follows:

(55) $\begin{array}{cc}\left(\frac{R_C}{R_X}+1\right)=\frac{V_{\mathrm{POR}}}{\left(-V_T.Math.\frac{b}{h}+V_{\mathrm{BE}}\right)}& \left(11\right)\end{array}$

(56) from which it is clear that the ratio R.sub.C/R.sub.x is determined by the value of the POR detection levels.

(57) Further design considerations derive from the power consumption of the POR circuit 1.

(58) In this regard, it is noted that the static consumption IT at the switching point is determined by summing the currents in the three branches of the POR circuit 1 (left branch 4a, central branch 22 and right branch 4b):
I.sub.T=I.sub.O+2.Math.I.sub.C=(B+2).Math.I.sub.CB
so that:

(59) $\begin{array}{cc}B=\frac{I_T}{I_C}-2& \left(12\right)\end{array}$

(60) The selection of parameter B (and so of m, see above expression 3) is thus strictly related with the global static consumption IT.

(61) In particular, selection of parameter m is linked with two contrasting requirements: the speed of the POR detection versus the global consumption (the lower m, the higher the speed at the switching point due to a higher current circulating in the left and right branches 4a, 4b); the positive slope compensation of the POR detection level versus temperature (the higher m, the lower the positive compensation coefficient in the above expression (9) for the POR detection level).

(62) When the power supply voltage V.sub.cc is well above the POR switching point (i.e. well above the high POR detection level V.sub.PORH), the current consumption I.sub.CC is mostly determined by the central resistor 22 and the left branch 4a of the PTAT stage 2 with the load transistor 9a (the right branch 4b is instead limited in current and its contribution can thus be neglected); moreover, the output comparator 12 (with comparator transistors 14a-14d) is in this case off, with no current flowing through the same transistors.

(63) As an approximation, the following expression applies for current consumption I.sub.CC, in this operating phase:

(64) $\begin{array}{cc}{I}_{\mathrm{CC}}\sim \frac{\left(V_{\mathrm{CC}}-V_{\mathrm{BE}}\right)}{R_C}.Math.\frac{m+1}{m}& \left(13\right)\end{array}$

(65) Selection of M (and consequently n, being M=In n) takes into account area occupation, due to the size of load resistor 10 with resistance R.sub.E, and circuit speed, since higher M means higher n (i.e. a higher number of bipolar transistors in parallel in load transistor 9b). On the other hand, M cannot be too much low, otherwise it is difficult to balance the negative slope in the above expression (9) for the POR detection level; for example, n=.sub.4 can be a starting point for designing the POR circuit 1.

(66) The value and size of central resistor 22 is basically determined by the target current consumption I.sub.CC, according to formula (13) for the same current consumption I.sub.CC.

(67) After the selection of n, m and R.sub.C, all the other parameters are determined accordingly: in particular, resistance R.sub.E can be deduced from above expression (10); resistance R.sub.x can be deduced from the above expression (11).

(68) It is underlined that two different and distinct values for resistances R.sub.C, R.sub.E, and R.sub.X are determined, one for each of the high and low POR detection levels (V.sub.PORH and V.sub.PORL).

(69) In particular, it is noted that proper choice of the resistance values allows to achieve a high response speed at the high POR detection level V.sub.PORH (in particular with a lower value for resistances R.sub.E and R.sub.C and a higher current circulating in the circuit branches), when a high reactivity is needed to start the power-on sequence; and a lower consumption (with a corresponding lower reactivity, but this is not an issue for the correct operation of the circuit and the associated electronic device) at the low POR detection level V.sub.PORL (in particular with a higher value for resistances R.sub.E and R.sub.C when the consumption is induced by the value of R.sub.C, as seen above for expression (13)).

(70) FIG. 3 shows a schematic block diagram representative of the general operation of the POR circuit 1, as discussed above (it is noted that in this diagram base currents in the load transistors 9a, 9b and central transistor 24 are not considered, for sake of simplicity).

(71) In particular, as shown at block 30, POR detection voltage V.sub.POR (at the high or low POR detection level V.sub.PORH, V.sub.PORL) is generated as the sum of the base-emitter voltage V.sub.BE in the central transistor 24 (block 31) and the voltage drop (I.sub.o−R.sub.c) on the central resistor 22 (block 32), due to the central-branch current I.sub.O.

(72) As shown at block 33, the central-branch current I.sub.O is given by the sum of the equilibrium current I.sub.C, which is a function of the power supply voltage V.sub.cc (block 34), and of the further current V.sub.BE/R.sub.x injected via the current-injection resistor 28 (block 35).

(73) Moreover, at block 36, the current equilibrium detection condition of the PTAT stage 2 is shown, with equal currents I.sub.C1=I.sub.C2=I.sub.C (the equilibrium current I.sub.C being given by ΔV.sub.BE/R.sub.E as shown in block 37) circulating in the left and right branches 4a, 4b, upon the power supply voltage V.sub.cc crossing the POR detection voltage V.sub.POR; PTAT detection causes switching of the reset signal POR at the output.

(74) As shown in the same FIG. 3, hysteresis in the POR detection is achieved by modification, at the equilibrium condition of the PTAT stage 2, of the resistance values values R.sub.E, R.sub.C and R.sub.X of load resistor 10, central resistor 22 and current-injection resistor 28.

(75) FIG. 4 schematically shows an electronic device 40, e.g., a stand-alone non-volatile memory device (such as a Flash memory), including a power supply generator 42, providing the power supply V.sub.CC; the disclosed POR circuit 1, receiving the power supply V.sub.CC and configured to generate the reset signal POR based on the value of the same power supply V.sub.CC crossing the high and low POR detection levels V.sub.PORH, V.sub.PORL; and electronic circuitry 44, coupled to the POR circuit 1 to receive the reset signal POR, in order to activate a power-on sequence of operations (when the same reset signal POR switches to a first value, e.g., a high value) or to stop operations (when the reset signal POR switches to a second value, e.g., a low value).

(76) The advantages of the proposed solution are clear from the foregoing description.

(77) In any case, it is again underlined that the proposed solution allows to achieve the following advantages versus known solutions: a full control in temperature for both POR detection thresholds (high and low POR detection levels V.sub.PORH, V.sub.PORL); a very low consumption in all operating conditions; a high speed at the V.sub.PORH threshold; a high noise immunity; the possibility to finely tune the high and low POR detection levels V.sub.PORH, V.sub.PORL at any desired level above the bandgap level.

(78) Moreover, as previously underlined, the speed of POR answer during V.sub.PORH transition is not limited by the consumption; this allows to increase the consumption above the static target before crossing of the high POR detection level V.sub.PORH and to achieve good speed performances even for very high V.sub.CC slopes.

(79) Simulations and tests made by the present Applicant have shown the possibility for the disclosed POR circuit 1 to achieve improved electrical performances, both for static and dynamic operations.

(80) In particular, static performance includes: a high hysteresis range of about ˜70 mV between the high and low POR detection levels; immunity to disturbs during slow V.sub.CC slopes; high and low POR detection levels compensated in a wide temperature range (e.g., from −40° C. to 125° C.), with minimum variations (e.g., lower than 10 mV) in the whole temperature range, and tunable above the bandgap native voltage (˜1.25V), for example with values of V.sub.PORH˜1.42V, V.sub.PORL˜1.35V; low sensitivity to (global and/or mismatch) process variation, for example V.sub.PORL˜1.35+/−100 mV (at 3σ); low static consumption, for example I.sub.CC<1 μA in worst case conditions (with a power supply voltage V.sub.CC of 1.8V, T=150° C., +/−3G) and I.sub.cc<2 μA in worst case conditions (with a power supply voltage V.sub.CC of 3.6V, T=150° C., +/−3σ).

(81) Dynamic performance includes: T.sub.PORH<4 μs in a worst case condition (T.sub.PORH being the delay in the reset signal POR switching with respect to the power supply V.sub.CC crossing the high POR detection level V.sub.PORH); T.sub.PORL<10 μs in a worst case condition (T.sub.PORL being the delay in the reset signal POR switching with respect to the power supply V.sub.CC crossing the low POR detection level V.sub.PORL); immunity to V.sub.CC spikes induced by I/O commutation.

(82) Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.

(83) In particular, it is noted that the POR circuit 1 may not include the output Schmitt trigger 16, coupled to the output comparator 12 (in this case, the output of the same output comparator 12 providing the reset signal POR).

(84) Moreover, it is again underlined that the disclosed POR circuit 1 may be used advantageously in any kind of electronic device, wherein a reset signal is required for device start-up, when the power supply reaches a suitable high threshold, and for device deactivation, when the power supply drops below a certain low threshold.

(85) While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.