LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THAT

Abstract

A liquid crystal display device includes a first substrate, a first alignment film formed over the first substrate, a second substrate, a second alignment film formed over the second substrate, a liquid crystal layer sandwiched between the first alignment film and the second alignment film, and a projecting portion formed over the second substrate. The first alignment film is a photo alignment film ,and a thickness “d2” of the second alignment film over the projecting portion and a film thickness “d1” of a portion of the first alignment film facing the projecting portion satisfy formula (2),

d2<d1   (2).

Claims

1. A liquid crystal display device comprising: a first substrate; a second substrate opposed to the first substrate; a first projection and a second projection provided between the first substrate and the second substrate; alignment films provided on the first substrate and the second substrate; and a liquid crystal layer provided between the alignment films, wherein the alignment films have a first alignment film provided on the first substrate and a second alignment film provided on the second substrate, wherein the first projection is covered by either the first alignment film or the second alignment film, wherein the second projection is covered by either the first alignment film or the second alignment film, wherein a height of the first projection is higher than a height of the second projection, wherein a top surface of the first projection is a flat surface, wherein a thickness of one of the alignment films on the top surface of the first projection is thicker than a thickness of one of the alignment films other than the top surface of the first projection, wherein a thickness of one of the alignment films on the top surface of the second projection is thicker than a thickness of one of the alignment films other than the top surface of the second projection, and wherein the thickness of one of the alignment films other than the top surface of the first projection is equal to the thickness of one of the alignment films other than the top surface of the second projection.

2. The liquid crystal display device according to claim 1, further comprising a thin film transistor including a gate electrode provided on the first substrate; a first insulation film provided on the thin film transistor; a first electrode provided on the first insulation film; a second insulation film provided on the first electrode and the first insulation film; and a second electrode provided on the second insulation film, wherein first alignment film is provided on the second insulation film and the second electrode.

3. The liquid crystal display device according to claim wherein one of the first electrode and the second electrode is connected to the thin film transistor.

4. The liquid crystal display device according to claim 2, wherein the second projection is provided on the first substrate.

5. The liquid crystal display device according to claim 1, further comprising a light shielding layer provided on the second substrate, wherein the second alignment film provided on the light shielding layer.

6. The liquid crystal display device according to claim 5, wherein the first projection provided on the second substrate.

7. The liquid crystal display device according to claim 6, wherein the first projection provided on the light shielding layer.

8. The liquid crystal display device according to claim 1, wherein the first alignment film and the second alignment film are a photo alignment film.

9. A liquid crystal display device comprising: a first substrate: a thin film transistor including a source electrode provided on the first substrate; a first insulation film provided on the thin film transistor; a first alignment film provided on the first insulation film; a first electrode and a second electrode provided between the first substrate and the first alignment film in a pixel region; a second substrate; a light shielding layer provided on the second substrate; a projection provided on the light shielding layer; a second alignment film provided on the light shielding layer and the projection; and a liquid crystal layer provided between the first substrate and the second substrate, wherein one of the first electrode and the second electrode is connected to the source electrode of the thin film transistor, wherein top surface of the projection is a flat surface, wherein a total thickness “b” of the first alignment film and the second alignment film between the projection and the second insulation film satisfies formula (1), wherein a thickness of the first alignment film other than between the projection and the first insulation film is equal to a thickness of the second alignment film other than between the projection and the first insulation film,
0 nm<b<30 nm   (1).

10. The liquid crystal display device according to claim 9, wherein the first alignment film and the second alignment film are a photo alignment film.

11. The liquid crystal display device according to claim 9, wherein the second alignment film does not on a top surface of the projection.

12. The liquid crystal display device according to claim 9, wherein the thickness of the first alignment film other than between the projection and the first insulation film is a thickness of the first alignment film in the pixel region.

13. The liquid crystal display device according to claim 9, wherein the thickness of the second alignment film other than between the projection and the first insulation film is a thickness of the second alignment film on the light shielding layer adjacent to the projection.

14. A liquid crystal display device comprising: a first substrate: a thin film transistor including a source electrode provided on the first substrate; a first insulation film provided on the thin film transistor; a first alignment film provided on the first insulation film; a first electrode and a second electrode provided between the first substrate and the first alignment film in a pixel region; a second substrate a light shielding layer provided on the second substrate; a projection provided on the light shielding layer; a second alignment film provided on the light shielding layer and the projection; and a liquid crystal layer provided between the first substrate and the second substrate, wherein one of the first electrode and the second electrode is connected to the source electrode of the thin film transistor, wherein the first alignment film and the second alignment film are a photo alignment film, wherein a total thickness “b” of the first alignment film and the second alignment film between the projection and the second insulation film satisfies formula (1), wherein a thickness of the first alignment film other than between the projection and the first insulation film is equal to a thickness of the second alignment film other than between the projection and the first insulation film,
0 nm<b<30 nm   (1).

15. The liquid crystal display device according to claim 14, wherein a top surface of the projection is a flat surface.

16. The liquid crystal display device according to claim 14, wherein the second alignment film does not on a top surface of the projection.

17. The liquid crystal display device according to claim 14, wherein the thickness of the first alignment film other than between the projection and the first insulation film is a thickness of the first alignment film in the pixel region.

18. The liquid crystal display device according to claim 14, wherein the thickness of the second alignment film other than between the projection and the first insulation film is a thickness of the second alignment film on the light shielding layer adjacent to the projection.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG. 1 is a cross-sectional view of an essential part showing an embodiment 1 of a liquid crystal display device according to the present invention;

[0047] FIG. 2 is a table showing constitutional members of the liquid crystal display device shown in FIG. 1 and film thicknesses of these constitutional members;

[0048] FIG. 3 is a table showing the manufacture of alignment films in the liquid crystal display device shown in FIG. 1, and film thicknesses of the alignment films obtained by the manufacture;

[0049] FIG. 4 is a cross-sectional view of an essential part showing an embodiment 2 of a liquid crystal display device according to the present invention;

[0050] FIG. 5 is a table showing constitutional members of the liquid crystal display device shown in FIG. 4 and film thicknesses of these constitutional members;

[0051] FIG. 6 is a table showing the manufacture of alignment films in the liquid crystal display device shown in FIG. 4, and film thicknesses of the alignment films obtained by the manufacture;

[0052] FIG. 7 is a cross-sectional view of an essential part showing an embodiment 3 of a liquid crystal display device according to the present invention;

[0053] FIG. 8 is a table showing the manufacture of alignment films in the liquid crystal display device shown in FIG. 7, and film thicknesses of the alignment films obtained by the manufacture;

[0054] FIG. 9 is a cross-sectional view of an essential part showing an example of a liquid crystal display device which constitutes a comparison example;

[0055] FIG. 10 is a table showing the manufacture of alignment films in the liquid crystal display device shown in FIG. 9, and film thicknesses of the alignment films obtained by the manufacture;

[0056] FIG. 11 is a table showing a bright-spot-generation withstand voltage level in the above-mentioned respective embodiments;

[0057] FIG. 12 is a table describing a content of references for determining the above-mentioned bright-spot-generation withstand voltage level; and

[0058] FIG. 13 is a view showing a graph which is obtained by converting the table shown in FIG. 11.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059] Embodiments of the present invention are explained in conjunction with drawings. In respective drawings and respective embodiments the identical or similar constitutional elements are given same symbols and their explanation is omitted.

Embodiment 1

(Constitution)

[0060] FIG. 1 shows a cross section of a liquid crystal display device (panel) of the present invention. FIG. 1 shows a portion of the liquid crystal display device where a pillar-shaped spacer and a spacer pedestal are formed and a periphery of such a portion. FIG. 1 shows the constitution of the liquid crystal display device correspondingto the examples 1 to 4.

[0061] In FIG. 1, a so-called electrode substrate and a so-called counter substrate are arranged to face each other in an opposed manner with a liquid crystal layer LC sandwiched therebetween.

[0062] The electrode substrate has following constitution for example. First of all, the electrode substrate includes a substrate SUB1. On a liquid-crystal-layer-LC-side surface of the substrate SUB1, gate electrodes GT and counter electrodes CT are formed. The gate electrode GT constitutes a gate electrode of a thin film transistor TFT described later, and a scanning signal is supplied to the gate electrode GT from a gate signal line not shown in the drawing. The counter eiectrode CT is an electrode which is provided for generating an electric field in the liquid crystal layer LC in corporation with a pixel electrode PX described later. The counter electrode CT is a planar electrode formed of an ITO (Indium Tin Oxide) film, for example, which is formed over the substantially whole region of the pixel.

[0063] On a surface substrate SUB1, an insulation film GI is formed so as to also cover the gate electrodes GT and the counter electrodes CT. The gate insulation film GI functions as a gate insulation film in a region where the thin film transistor TFT is formed.

[0064] A semiconductor layer AS is formed on the gate insulation film GI so as to overlap with the gate electrode GT, and a drain electrode SD and a source electrode SD are formed on an upper surface of the semiconductor layer AS thus constituting a

film transistor TFT. A video signal is supplied to one electrode out of the drain electrode SD and the source electrode SD via a drain signal line not shown in the drawing. Further, another electrode out of the drain electrode SD and the source electrode SD extends to the outside of a region where the thin film transistor TFT is formed, and is electrically connected with the pixel electrode PX described later.

[0065] Then, in a region outside the region where the thin film transistor TFT is formed (for example, a region which overlaps with the gate signal line), a stacked body constituted of a semiconductor layer SC and a metal layer ML is formed. The semiconductor layer SG is formed simultaneously with the formation of the semiconductor layer AS, while the metal layer ML is formed simultaneously with the formation of the drain electrode SD and the source electrode SD. The stacked body constituted of the semiconductor layer SC and the metal layer ML forms a spacer pedestal SS together with a protective film PAS described later.

[0066] On a surface of the substrate SUB1, the protective film PAS is formed so as to also cover the thin film transistor TFT and the stacked body constituted of the semiconductor layer SC and the metal layer ML. The protective film PAS is provided for obviating a direct contact between the thin film transistor TFT and the liquid crystal, and is formed of an inorganic insulation film, for example. On a portion of the protective film PAS where the stacked body constituted of the semiconductor layer SC and the metal layer ML is formed, a projecting portion which projects than a periphery thereof is formed, and the projecting portion functions as the spacer pedestal SS.

[0067] A pixel electrode PX which is constituted of a plurality of linear electrodes arranged parallel to each other is formed on an upper surface of the protective film PAS in a region where the pixel electrode PX overlaps with the counter electrode CT. The pixel electrode PX is formed of an ITO (Indium Tin Oxide) film, for example. The pixel electrode PX is electrically connected with another electrode out of the drain electrode SD and the source electrode SD of the thin film transistor TFT via a through hole formed in the protective film PAS at a position not shown in the drawing.

[0068] An alignment film ORI1 made of a photo-decomposition-type material is formed on a liquid-crystal-LC-side surface of the substrate SUB1 so as to also cover the pixel electrodes PX. The film thickness “b” of the alignment film ORI1 on a top surface of the spacer pedestal SS is set smaller than the film thickness “a” of the alignment film ORI1 in a region other than the top surface of the spacer pedestal SS (for example, above the pixel electrode PX), or the film thickness “b” is set to zero. The film thickness “b” of the alignment film ORI1 on the top surface of the spacer pedestal SS is set to a value of not more than 30 nm. Here, the film thickness of the alignment film ORI1 above the pixel electrode PX, for example, is set to 110 nm, for example. A manufacturing method of the alignment film ORI1 is explained in detail later.

[0069] On the other hand, the counter substrate is constituted as follows, for example. First of all, a substrate SUB2 is provided. A black matrix BM and color filters FIL are formed on a liquid-crystal-LC-side surface of the substrate SUB2. The black matrix BM is formed between neighboring pixel regions, and the color filter FIL is formed so as to cover each pixel region.

[0070] On an upper surface of the black matrix BM and upper surfaces of the color filters FIL, an overcoat film OC formed of a resin film, for example, is formed. The overcoat film OC may be omitted in this embodiment.

[0071] Pillar-shaped spacers PS are formed on an upper surface of the overcoat film CC at positions where the pillar-shaped spacers PS face the spacer pedestals SS in an opposed manner. The pillar-shaped spacer PS is formed with a height and an area which are respectively larger than a height and an area of the spacer pedestal SS. The pillar-shaped spacers PS are formed by selectively etching a resin film applied to the upper surface of the overcoat film OC by coating, and the pillar-shaped spacer PS has a flat top surface.

[0072] Then, an alignment file ORI2 is formed on a liquid-crystal-LC-side surface of the substrate SUB2. The film thickness of the alignment film ORI2 on a top surface of the pillar-shaped spacer PS is set smaller then a film thickness “c” of the alignment film ORI2 in a region other than the top surface of the pillar-shaped spacer PS (for example, above the black matrix BM), or the film thickness of the alignment film ORI2 on the top surface of the pillar-shaped spacer PS is set to zero. The reduction of the film thickness of the alignment film ORI2 on the top surface of the pillar-shaped spacer can be realized by applying an alignment film material to liquid-crystal-LC-side surface of the substrate SUB2 and, thereafter, by performing time-prolonged leveling corresponding to viscosity by prolonging a leveling time.

[0073] With respect to the liquid crystal display device having such constitution, materials and film thicknesses of the above-mentioned respective members are described in tables shown in FIG. 2. The upper table shown in FIG. 2 describes the members on the counter substrate, wherein from a substrate SUB2 side to a liquid crystal layer LC side, sequentially, the black matrix BM (indicated by BM in the table), the color filter FIL (indicated by color pixel layer in the table), the overcoat film OC (indicated by overcoat in the table), the pillar-shaped spacer (indicated by pillar-shaped spacer in the table), and the alignment film ORI2 (indicated by alignment film (film thickness: “c”)) are listed. Here, the film thickness of the alignment film ORI2 indicates a film thickness at a portion where the film thickness is set to the film thickness “c” in FIG. 1, and a value of the film thickness is described separately (see FIG. 3). The lower table shown in FIG. 2 describes the members formed on the electrode substrate, wherein from the liquid crystal layer LC side to the substrate SUB1 side, sequentially, the alignment film ORI1 (indicated by alignment film (film thickness: “a”) in the table), the pixel electrode PX (indicated by pixel electrode in the table), the protective film PAS (indicated by protective flim in the table), the source electrode and the drain electrode (indicated by source/drain in the table), the semiconductor device AS (indicated by a-Si in the table), the insulation film GI (indicated by gate insulation film in the table), the gate electrode (indicated by gate in the table), and the counter electrode (indicated by common ITO in the table) are listed. Here, the film thickness of the alignment film ORI1 indicates a film thickness at a portion where the film thickness is set to the film thickness “a” in FIG. 1. The value of the film thickness is described separately (see FIG. 3).

(Manufacturing Method)

[0074] Next, one embodiment of a manufacturing method of the above-mentioned alignment film ORI1 and a manufacturing method of the alignment film ORI2 respectively is described. Although the explanation made hereinafter is directed to the manufacturing method of the alignment film ORI1, the alignment film ORI2 is manufactured substantially in the same manner.

[0075] First of all, an alignment film material is printed on the protective film PAS formed on the electrode substrate by a printer, for example, such that the alignment film material also covers the spacer pedestals SS. The alignment film material is made of a material having a skeleton formed of cyclobutane tetracarboxylic acid-diamine phenyl ether, for example. Here, solution concentration and solution viscosity of the alignment film material are made different corresponding to a plurality of examples. That is, as described in the table shown in FIG. 3, solution concentration and solution viscosity of the alignment film material are respectively set to 7 wt % , 30 mPa.Math.s (example 1), 7 wt %, 25 mPa.Math.s (example), 8 wt %, 20 mPa.Math.s (example 3), and 7 wt %, 35 mPa.Math.s (example 4). Here, in all examples, solution viscosity is set to a value smaller than 35 mPa.Math.s.

[0076] Then, the electrode substrate is heated on a hot plate at a temperature of 80° C. for 3 minutes and, thereafter, is baked at a temperature of 220° C. for 60 minutes. Here, the film thickness of the alignment film material at the portion where the film thickness assumes the film thickness “a”, the portion where the film thickness assumes the film thickness “b” and the portion where the film thickness assumes the film thickness “c” in FIG. 1 is described for the above-mentioned respective examples 1 to 4 in the table shown in FIG. 3 (item: before radiation of light).

[0077] Thereafter, on the hot plate held at a temperature of 200° C. light (polarization light containing ultraviolet rays) generated by a low pressure mercury lamp (integrated illuminance 5 mW/cm2 at 230 to 330 nm) is radiated for 1000 seconds (integrated radiation quantity 5 J/cm2). Here, the film thickness of the alignment film material at the portion where the film thickness assumes the film thickness “a”, the portion where the film thickness assumes the film thickness “b” and the portion where the film thickness assumes the film thickness “c” in FIG. 1 is described for the above-mentioned respective examples 1 to 4 in the table shown in FIG. 3 (item: after radiation of light). As can be clearly understood from this table, in all embodiments, the film thickness of the alignment film ORI1 on the top surface of the spacer pedestal SS can be set to a value of not more than 30 nm. That is, the film thickness of the alignment film ORI1 on the top surface of the spacer pedestal SS is set to 13 nm in the example 1, 10 nm in the example 2, 8 nm in the example 3 and 30 nm in the example 4. On the other hand, the film thickness of the alignment film ORI1 in other region except for the top surface of the spacer pedestal SS (the region above the pixel electrode PX) is set to 110 nm in the example 1, 100 nm in the example 2, 110 nm in the example 3 and 120 nm in the example 4.

[0078] Further, the film thickness of the alignment film ORI2 on the counter substrate side is set, at a portion in FIG. 1 where the film thickness assumes the film thickness “c” , to 110 nm in the example 1, 100 nm in the example 2, 110 nm in the example 3 and 120 nm in the example 4, while the film thickness of the alignment film ORI2 assumes a value which, is substantially zero on the top surface of the pillar-shaped spacer PS although not shown in FIG. 3.

[0079] In FIG. 3, for a comparison purpose, comparison examples 1 to 3 are also described. FIG. 3 shows a case where solution concentration and solution viscosity of the alignment film material are respectively set to 6 wt %, 50 mPa.Math.s (comparison example 1), 5 wt %, 45 mPa.Math.s (comparison example 2), and 6 wt %, 40 mPa.Math.s (comparison example 3), wherein solution viscosity is set to a value larger than 35 mPa.Math.s. In the table shown in FIG. 3, the film thickness of the alignment film before radiation of light and the film thickness of the alignment film after radiation of light are described in association with the above-mentioned examples. Here, it is found that the film thickness of the alignment film ORI1 on the top surface of the spacer pedestal SS becomes larger than 30 nm.

Embodiment 2

(Constitution)

[0080] FIG. 4 shows the constitution of a liquid crystal display device corresponding to the examples 5 to 8, and corresponds to FIG. 1.

[0081] The constitution which makes the liquid crystal display device shown in FIG. 4 different from the liquid crystal display device shown in FIG. 1 lies in that, first of all, the pillar-shaped spacers PS, are formed on an electrode substrate side, and spacer pedestals SS are formed on the counter electrode side. Further, the spacer pedestals SS are formed on an upper surface of an overcoat film OC as a resin layer, for example.

[0082] Also in this case, the file thickness “b” of an alignment ORI2 on a top surface of the spacer pedestal SS is set smaller than a film thickness “c” the alignment film ORI2 in a iegion other than the top surface of the spacer pedestal SS (for example, above a black matrix BM), or the film thickness “b” is set to zero. The film thickness “b” of the alignment film ORI2 on the top surface of the spacer pedestal SS is set to a value of not more than 30 nm. Here, the film thickness “c,” of the alignment film ORI2 on the black matrix BM, for example, is set to 110 nm, for example.

[0083] With respect to the liquid crystal display device having such constitution, materials and film thicknesses of the above-mendoned respective members are described in tables shown in FIG. 5. The upper table shown in FIG. 5 describes the members on the counter substrate, wherein from a substrate SUB2 side to a liquid crystal layer LC side, sequentially, the black matrix BM (indicated by BM in the table), the color filter (indicated by color pixel layer in the table), the overcoat film OC (indicated by overcoat in the table), the spacer pedestal (indicated by pedestal in the table) and the alignment film ORI2 (indicated by alignment film (film thickness: “c”) in the table) are listed. Here, the film thickness of the alignment film ORI2 indicates a film thickness at a portion where the film thickness is set to the film thickness “c” in FIG. 4. The value of the film thickness is described separately (see FIG. 6). The lower table shown in FIG. 5 describes the members formed on the electrode substrate, wherein from the liquid crystal layer LC side to the substrate SUB1 side, sequentially, the alignment film ORI1 (indicated by alignment film (film thickness: “a”) in the table) the pillar-shaped spacer PS (indicated by pillar-shaped spacer in the table), the pixel electrode PX (indicated by pixel electrode in the table), the protective film PAS (indicated by protective film in the table), the source electrode and the drain electrode (indicated by source/drain in the table), the semiconductor device AS (indicated by a-Si in the table), the insulation film GI (indicated by gate insulation film in the table), the gate electrode (indicated by gate in the table), and the counter electrode CT (indicated by common ITO in the table) are listed. Here, the film thickness of the alignment film ORI1 indicates a film thickness at a portion where the film thickness is set to the the thickness “a” in FIG. 1. The value of the film thickness is described separately (see FIG. 6).

(Manufacturing Method)

[0084] The manufacturing method of the alignment film ORI1 and the manufacturing method of the alignment film ORI2 are substantially equal to the corresponding manufacturing methods described in the embodiment 1.

[0085] Solution concentration and solution viscosity of the alignment film material are made different corresponding to a plurality of examples. That is, as described in the table shown in FIG. 6, solution concentration and solution viscosity of the alignment film material are respectively set to 7 wt %, mPa.Math.s (example 5), 7 wt %, 25 mP.Math.s (example 6), 8 wt %, 25 mPa.Math.s (example and 7 wy %, 35 mPa.Math.s (example 8). Here, in all examples, solution viscosity is set to a value smaller than 35 mPa.Math.s.

[0086] Here, the film thickness of the alignment film material at the portion where the film thickness assumes the film thickness “a”, the portion where the film thickness assumes the film thickn “b” and the portion where the film thickness assumes the film thickness “c” in FIG. 4 is described for the above-mentioned respective examples 5 to 8 in the table shown in FIG. 4 (item: after radiation of light). As can be clearly understood from this table, in all embodiments, the film thickness of the alignment film ORI1 on the top surface of the spacer pedestal SS can be set to a value of not more than 30 nm. That is, the film thickness of the alignment film ORI1 on the top surface of the spacer pedestal SS is set to 13 nm in the example 5, 10 nm in the example 6, 8 nm in the example 7 and 30 nm in the example 8. On the other hand, the film thickness “c” of the alignment film ORI2 in other region except for the top surface of the spacer pedestal SS (the region above the black matrix BM) is set to 110 nm in the example 5, 100 nm in the example 6, 110 nm in the example 7, and 120 nm in the example 8.

[0087] Further, the film thickness of the alignment film ORI1 on the counter substrate side is set, at a portion in FIG. 4 where the film thickness assumes the film thickness “a”, to 110 nm in the example 5, 100 nm in the example 6, 110 nm in the example 7 and 12 nm in the example 8, while the film thickness of the alignment film ORI1 assumes a value which is approximately zero on the top surface of the pillar-shaped spacer PS although not shown in FIG. 6.

[0088] In FIG. 6, for a comparison purpose, comparison examples 4 to 6 are also described. FIG. 6 shows a case where solution concentration and solution viscosity of the alignment film material are respectively set to 6 wt % 50 mPa.Math.s. (comparison example 4), 5 wt % , 45 mPa.Math.s (comparison example 5), and 6 wt %, 40 mPa.Math.s (comparison example 6). In the table shown in FIG. 6, the film thickness of the alignment film before radiation of light and the film thickness of the alignment film after radiation of light are described in association with the above-mentioned examples. Here, it is found that the film thickness of the alignment film ORI1 on the top surface of the spacer pedestal SS becomes larger than 30 nm.

Embodiment 3

(Constitution)

[0089] FIG. 7 shows the constitution of a liquid crystal display device corresponding to examples 9 to 11 and corresponds to FIG. 1.

[0090] The constitution which makes this embodiment different from the embodiment shown in FIG. 1 lies in that the spacer pedestal SS shown in FIG. 1 is not particularly necessary in this embodiment and a portion where a thin film transistor TFT is formed to function as a spacer pedestal. It is because that a drain electrode SD and a source electrode SD of the thin film transistor TFT are formed as projecting portions higher than a periphery of these portions and hence, these portions can be also used as a spacer pedestal SS.

[0091] Also in this case, a film thickness of an alignment film ORI1 on an upper surface of the thin film transistor TFT is set smaller than a film thickness “a” of the alignment film ORI1 in a region other than the upper surface of the thin film transistor TFT (for example, above a pixel electrode PX), or the film thickness “b” is set to zero. The film thickness of the alignment film ORI1 on the upper surface of the thin film transistor TFT is set to a value of not more than 30 nm. Here, the film thickness of the “a” of the alignment film ORI1 on the pixel electrode PX, for example, is set to 110 nm, for example.

[0092] In such constitution, materials and film thicknesses of respective members of the embodiment 2 are substantially equal to the materials and the film thicknesses of the respective corresponding members described in the embodiment 1. That is, materials and film thicknesses of respective members have values substantially equal to values in the table shown in FIG. 2.

(Manufacturing Method)

[0093] The manufacturing rm iod of the alignment film ORI1 and the manufacturing method of the alignment film ORI2 are substantially equal to the corresponding manufacturing methods described in the embodiment 1.

[0094] Solution concentration and viscosity of the alignment film material are made different corresponding to a plurality of examples. That is, as described in the table shown in FIG. 8, solution concentration and solution viscosity of the alignment film material are respectively set to 7 wt %, 30 mPa.Math.s (example 9), 7 wt %, 25 mPa.Math.s (example 10), and 8 wt %, 25 mPa.Math.s (example 11), Here, in all examples, solution viscosity is set to a value smaller than 35 mPa.Math.s.

[0095] Here, the film thickness of the alignment film material at the portion where the film thickness assumes the film thickness “a” the portion where the film thickness assumes the film thickness “b” and the portion where the film thickness assumes the film thickness “c” is described for the above-mentioned respective examples 9 to 11 in the table shown in FIG. 8 (item: after radiation of light). As can be clearly understood from this table, in all embodiments, the film thicknes of the alignment film ORI1 on the upper surface of the thin film transistor TFT can be set to a value of not more than 30 nm. That is, the film thickness of the alignment film ORI1 on the upper surface of the thin film transistor TFT is set to 21 nm in the example 9, 18 nm in the example 10, and 14 nm in the example 11. On the other hand, the film thickness of the alignment film ORI1 in other region except for the upper surface of the thin film transistor TFT (the region above the pixel electrode PX) is set to 110 nm in the example 9, 100 nm in the example 10, and 110 nm in the example 11.

[0096] Further, the film thickness of the alignment film ORI2 on the counter substrate side is set, at a portion in FIG. 7 where the film thickness assumes the film thickness “c”, to 110 nm in the example 9, 100 nm in the example 10, and 110 nm in the example 11, while the film thickness of the alignment film ORI2 assumes a value which is approximately zero on the top surface of the pillar-shaped spacer PS although not shown in FIG. 8.

[0097] In FIG. 8, for a comparison purpose, comparison examples 7 to 9 are also described. FIG. 8 shows a case where solution concentration and solution viscosity of the alignment film material are respectively set to 6 wt %, 50 mPa.Math.s (comparison example 7). 5 wt %, 45 mPa.Math.s (comparison example 8), and 6 wt %, 40 mPa.Math.s (comparison example 9). In the table shown in FIG. 8, the film thickness of the alignment film before radiation of light and the film thickness of the alignment film after radiation of light are described in association with the above-mentioned examples. Here, it is found that the film thickness of the alignment film ORI1 on the top surface of the spacer pedestal SS becomes larger than 30 nm.

Comparison Example 10

[0098] FIG. 9 shows the constitution in which a spacer pedestal (or a part which replaces the spacer pedestal such as the above-mentioned thin film transistor TFT) is not provided at a position which faces a pillar-shaped spacer PS. That is, FIG. 9 shows a comparison example which facilitates the understanding of advantageous effects of the above-mentioned respective examples in terms of quantity.

[0099] FIG. 9 corresponds to FIG. 1 and shows the constitution where the pillar-shaped spacer PS on a counter substrate side faces an alignment film ORI1 on an electrode substrate at an intersecting position of a gate signal line GL and a drain signal line DL.

[0100] In this case, a manufacturing method of the alignment film ORI1 is substantially equal to the manufacturing method of the alignment film ORI1 explained in conjunction with the embodiment 1, wherein solution concentration and solution viscosity of an alignment film material are set to 7 wt % and 30 mPa.Math.s, for example, as shown in FIG. 10. Further, in a table shown in FIG. 10, a film thickness of the alignment film material at positions where the film thickness is set to a film thickness “a” a film thickness “b” and a film thickness “c” in FIG. 9 is described with respect to a case before radiation of light and a case after radiation of light respectively. In this case, the film thickness “b” of the alignment film ORI1 which faces the pillar-shaped spacer PS after the radiation of light becomes 100 nm so that the film thickness “P” of the alignment film ORI1 largely exceeds 30 nm.

[0101] That is, on a liquid-crystal-layer-LC-side surface of the electrode substrate which faces the pillar-shaped spacer PS in an opposed manner, the liquid-crystal-layer-LC-side surface of the electrode substrate is only 300 nm which is a film thickness of the gate signal line GL and the alignment film ORI1 is brought into contact with the top surface over an area larger than an area of the top surface of the pillar-shaped spacer PS and hence, the film thickness “b” of the alignment film ORI1 is largely increased to 100 nm even after the radiation of light.

[0102] FIG. 11 shows a result of inspection of respective bright-spot-generation withstand voltage levels with respect to the examples 1 to 4, the comparison examples 1 to 3 the examples 5 to 8, the comparison examples 4 to 6, examples 9 to 11, and the comparison examples to 10.

[0103] FIG. 11 shows the respective bright-spot-generation withstand voltage levels with respect to the film thickness “b” of the alignment film which faces the pillar-shaped spacer PS after radiation of light in the respective examples and the respective comparison examples.

[0104] Here, the bright-spot-generation withstand voltage level is classified into 7 stages consisting of 0 to 6. As shown in FIG. 12, the bright-spot-generation withstand voltage level is evaluated based on the presence or the non-presence of the generation of bright spots at the time of completion of the liquid crystal display device, the presence or the non-presence of the abrasion of the surface alignment film at the time of disassembling the liquid crystal display device, the presence the non-presence of the generation of bright spots after a vibration test (3G), the presence or the non-presence of the abrasion of the surface alignment film after the vibration test (3G), the presence or the non-presence of generation of bright spots after a vibration test (5G), and the presence or the non-presence of the abrasion of the surface alignment film after the vibration test (5G). Here, with respect to the abrasion of the surface alignment film, there exists a possibility that even when the abrasion of the surface alignment film is not found in the observation carried out immediately after the test, an abraded portion which is concealed by a light blocking portion (a black matrix or the like, for example) appears on a display area due to a change with time and hence, such abrasion is also subject to the evaluation.

[0105] FIG. 13 is a graph converted from the table shown in FIG. 11, wherein alignment film thickness (nm) is taken on an abscissa, and the bright-spot-generation withstand voltage level is taken on an ordinate. An allowable range is set such that it is sufficient for a liquid crystal display device that no abrasion of the surface alignment film occurs in the vibration test (3G) and a liquid crystal display device whose bright-spot-generation withstand voltage leual is up to 2 is rendered acceptable. In this case, it is understood that the film thickness “b” of the alignment film which faces the pillar-shaped spacer PS after the radiation of light is set to a value of not more than 30 nm.