Pulsed source for driving non-linear current dependent loads

Abstract

A pulsed current source comprises a power source, a discharge capacitor, and an inductive element. The discharge capacitor is selectively coupled to either of the power source or the inductive element. When coupled to the power source, the discharge capacitor is charged. The inductive element can be connected to a load. The load can have a current-dependent impedance. When the discharge capacitor is coupled to the inductive element, the discharge capacitor discharges through the inductive element and the load. The discharge capacitor and the inductive element are configured so that the current through the load exhibits a substantially linear rise in a linear operational region. The inductive element is configured to saturate during discharge of the capacitor through the load, so that the saturation of the inductive element causes the current through the load to continue to rise in a substantially linear fashion.

Claims

1. A circuit, comprising: a load, wherein the load has an impedance that rises as an amount of current delivered to the load rises: an inductive element connected in series with the load; a capacitor; and a discharge switch connected between the capacitor and the inductive element, wherein responsive to the discharge switch closing, the capacitor discharges a current that passes through the load, the inductive element and the capacitor configured such that the current causes the inductive element to saturate, wherein responsive to saturating, the inductive element causes the current through the load to linearly increase.

2. The circuit of claim 1, wherein the load is a detonator.

3. The circuit of claim 1, wherein the load is a flash lamp.

4. The circuit of claim 3, wherein the flash lamp is configured to optically pump a pulsed laser source.

5. The circuit of claim 1, wherein the inductive element has an inductance of less than or equal to 1 milli-Henry.

6. The circuit of claim 5, wherein the inductive element has an inductance of less than or equal to 100 nano-Henries.

7. The circuit of claim 1, wherein the discharge capacitor has a capacitance of between 0.01 micro-Farads and 10 micro-Farads.

8. The circuit of claim 1, wherein the inductive element is a strip line inductive element.

9. The circuit of claim 1, wherein the inductive element saturates within 100 nanoseconds of the discharge switch being closed.

10. The circuit of claim 1, further comprising a power source, wherein the power source is selectively coupled to the capacitor and configured to charge the capacitor when coupled to the capacitor.

11. The circuit of claim 10, wherein the discharge switch is further connected between the capacitor and the power source, wherein when the discharge switch is closed in a first position the capacitor discharges the current, and when the discharge switch is closed in a second position the power source charges the capacitor.

12. The circuit of claim 10, further comprising a charging switch connected between the capacitor and the power source, such that when the charging switch is closed, the power source charges the capacitor.

13. The circuit of claim 12, wherein the charging switch and the discharge switch are configured such that only one of the charging switch or the discharge switch is closed at a time.

14. The circuit of claim 1, wherein the current through the load has a peak of greater than or equal to 1500 amperes.

15. The circuit of claim 1, wherein a discharge time of the circuit is less than or equal to 500 nanoseconds.

16. A method, comprising: providing a circuit that comprises: a power source; a capacitor; a charging switch; a load that has an impedance that is based upon an amount of current delivered to the load such that as the amount of the current that is delivered to the load rises, the impedance of the load rises; an inductive element connected in series with the load; and a discharge switch connected between the capacitor and the inductive element; closing the charging switch such that the power source charges the capacitor; and closing the discharge switch such that the capacitor discharges current through the inductive element to the load, wherein discharge of the current through the inductive element causes the inductive element to saturate, and further wherein the amount of current delivered to the load linearly increases for a time window subsequent to the inductive element becoming saturated.

17. The method of claim 16, wherein the load is a flash lamp that is configured to pump an optical gain medium.

18. The method of claim 16, wherein the load is a bridge wire detonator.

19. A detonation system, comprising: a detonator, wherein the detonator has an impedance that increases as an amount of current delivered to the detonator increases; an inductive element connected to the detonator; a capacitor; and a discharge switch connected between the capacitor and the inductive element, wherein responsive to the discharge switch closing, the capacitor discharges a current that passes through the inductive element and is provided to the detonator, the inductive element and the capacitor configured such that the current causes the inductive element to saturate, wherein responsive to saturating, the inductive element causes the current through the detonator to linearly increase.

20. The detonation system of claim 19, wherein the current through the detonator linearly increases prior to the current causing the inductive element to saturate, and further wherein the current through the detonator continues to linearly increase after the current causes the inductive element to saturate due to the inductive element becoming saturated.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit schematic of an exemplary high-inertia current source.

(2) FIG. 2 depicts exemplary plots of load current over time for the circuit depicted in FIG. 1 and a modified current source.

(3) FIG. 3 is a functional block diagram of an exemplary detonator system that incorporates a high-inertia current source.

(4) FIG. 4 is a functional block diagram of an exemplary laser system that incorporates a high-inertia current source.

(5) FIG. 5 is a flow diagram that illustrates an exemplary methodology for making and operating a high-inertia current source.

DETAILED DESCRIPTION

(6) Various technologies pertaining to a high-inertia current source are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It may be evident, however, that such aspect(s) may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more aspects. Further, it is to be understood that functionality that is described as being carried out by certain system components may be performed by multiple components. Similarly, for instance, a component may be configured to perform functionality that is described as being carried out by multiple components.

(7) Moreover, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from the context, the phrase “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, the phrase “X employs A or B” is satisfied by any of the following instances: X employs A; X employs B; or X employs both A and B. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from the context to be directed to a singular form.

(8) Further, as used herein, the terms “component” and “system” are intended to encompass computer-readable data storage that is configured with computer-executable instructions that cause certain functionality to be performed when executed by a processor. The computer-executable instructions may include a routine, a function, or the like. It is also to be understood that a component or system may be localized on a single device or distributed across several devices. Additionally, as used herein, the term “exemplary” is intended to mean serving as an illustration or example of something, and is not intended to indicate a preference.

(9) With reference to FIG. 1, an exemplary system 100 that incorporates a high-inertia current source 102 is illustrated. The system 100 includes the high-inertia current source 102 and a current-dependent load 104. The current-dependent load 104 is modeled as a resistor R.sub.L with a parasitic load capacitance C.sub.L. The high-inertia current source 102 includes a voltage source V.sub.1, a charging switch S.sub.1, a discharge capacitor C.sub.1, a discharge switch S.sub.2, and a saturable inductor L.sub.1. The high-inertia current source 102 shown in FIG. 1 further includes modeled line resistances R.sub.1 and R.sub.2, and a modeled line inductance L.sub.2. It is to be understood that while modeled elements R.sub.1, R.sub.2, C.sub.L and L.sub.2 affect performance of the circuit 100, these elements are not discrete components but rather represent electrical effects of other components, such as the discharge capacitor C.sub.1, the saturable inductor L.sub.1, the current-dependent load 104, and various interconnects among such components.

(10) The voltage source V.sub.1 is connected to ground and to a first node N.sub.1 by way of the charging switch S.sub.1. The discharge capacitor C.sub.1 and its associated line resistance R.sub.1 are connected in series between ground and the first node N1. The discharge switch S.sub.2 is connected between the first node N1 and the series combination of the line inductance L.sub.2 and resistance R.sub.2. It is to be understood that while the switches S.sub.1 and S.sub.2 are modeled as single-pole single-throw (SPST) switches, the switches S.sub.1 and S.sub.2 can instead be a single-pole double-throw (SPDT) switch that selectively connects the discharge capacitor C.sub.1 to either the saturable inductor L.sub.1 (through line impedances L.sub.2 and R.sub.2) or to the voltage source V.sub.1. The series combination of line impedances L.sub.2, R.sub.2 and the saturable inductor L.sub.1 are connected between the discharge switch S.sub.2 and a second node N2. The current-dependent load 104 is connected between ground and the second node N2.

(11) When the charging switch S.sub.1 is closed, the voltage source V.sub.1 charges the discharge capacitor C.sub.1. When the discharge capacitor C.sub.1 is sufficiently charged (e.g., to a set point voltage, to the output voltage of the voltage source V.sub.1, or after a set charging time has elapsed), the charging switch S.sub.1 can be opened, and the discharge capacitor C.sub.1 ceases charging. It is to be understood that in other embodiments, the voltage source V.sub.1 can be replaced by any suitable power source that is capable of charging a capacitor (e.g., a current source).

(12) Subsequent to the discharge capacitor C.sub.1 being charged by the voltage source V.sub.1, and the charging switch S.sub.1 being opened, the discharge switch S.sub.2 is closed. Closing of the discharge switch S.sub.2 causes the discharge capacitor C.sub.1 to discharge current to the current-dependent load 104. The discharge capacitor C.sub.1 discharges current through the saturable inductor L.sub.1 and to the current-dependent load 104. The current-dependent load 104 has an impedance that is a function of the current I.sub.RL delivered to the load 104. The high-inertia current source 102 is configured so that the current I.sub.RL delivered to the load 104 has a substantially linear increase during a linear operational period despite the change in impedance of the current-dependent load 104.

(13) Referring now to FIG. 2, a plot 202 of the load current I.sub.RL of the system 100 against time is shown. At time t.sub.0, the discharge switch S.sub.2 is closed, and the discharge capacitor C.sub.1 begins discharging through the saturable inductor L.sub.1 and the current-dependent load 104. From time t.sub.0 to time t.sub.1, the high-inertia current source 102 operates in an exponential regime wherein the load current I.sub.RL can be modeled as an exponential function I.sub.RL(t)=X.sup.Z where Z is the impedance of the current-dependent load 104. Z changes over time in response to the changing load current I.sub.RL. Depending on the particular construction of the current-dependent load 104, the change in impedance of the load 104 can vary in a linear or a non-linear fashion.

(14) In exemplary embodiments, the high-inertia current source 102 is configured to deliver a substantially linearly increasing load current I.sub.RL in a linear operational period by selection of the discharge capacitor C.sub.1 and the saturable inductor L.sub.1. For example, from time t.sub.1 to time t.sub.2, the load current I.sub.RL can be modeled as a linear function of time, I.sub.RL(t)=mt+b. The high-inertia current source 102 is referred to as “high-inertia” because the current source 102 provides the linearly increasing load current I.sub.RL in the linear operation period t.sub.1.fwdarw.t.sub.2 in spite of the impedance of the load 104 changing in a potentially nonlinear fashion. The high-inertia current source 102 inherently provides a linear output load current I.sub.RL in the linear operation period without need for further control circuitry apart from the discharge switch S.sub.2, which is kept closed throughout operation of the current source 102. The high-inertia current source 102 therefore provides an output load current profile (e.g., I.sub.RL(t)) that is not readily reproducible by switched capacitor networks.

(15) Subsequent to time t.sub.2, the output load current I.sub.RL(t) can be modeled as a sinusoid I.sub.RL(t)=Asin(ωt±θ). Thus, after time t.sub.2 the rate of increase of the load current I.sub.RL(t) falls and eventually turns negative after the load current I.sub.RL(t) peaks at time t.sub.3. In various embodiments, the system 100 is configured such that the current-dependent load 104 has performed an intended functionality prior to the fall-off of the load current I.sub.RL(t) after time t.sub.2. The time period t.sub.0.fwdarw.t.sub.2 can therefore be referred to as a discharge time of the system 100. In some embodiments, the time t.sub.2.fwdarw.t.sub.0 can be less than or equal to about 500 nanoseconds, less than or equal to about 300 nanoseconds, or less than or equal to about 150 nanoseconds.

(16) The discharge capacitor C.sub.1 and the saturable inductor L.sub.1 are configured such that the saturable inductor L.sub.1 is saturated by the load current I.sub.RL during discharge of the capacitor C.sub.1. When the saturable inductor L.sub.1 saturates, the magnetic field established in the core of the inductor L.sub.1 collapses. Collapse of the magnetic field causes the inductance of the saturable inductor L.sub.1 to fall. In exemplary embodiments, saturation of the inductor L.sub.1 causes inductance of the inductor L.sub.1 to drop to 25% or less of its nominal value. The collapse of the magnetic field causes the current through the inductor L.sub.1 to increase. This increase of the current through the inductor L.sub.1 offsets a slowdown in the rate of rise of the current I.sub.RL(t) that would otherwise be delivered by the discharge capacitor C.sub.1.

(17) By way of example, and referring once again to FIG. 2, a second plot 204 of load current I.sub.RL for the system 100 with the saturable inductor L.sub.1 shorted is also shown. Stated differently, the second plot 204 shows the load current I.sub.RL for a circuit that includes the discharge capacitor C.sub.1 but not the saturable inductor L.sub.1, such that the discharge capacitor C.sub.1 discharges directly to the current-dependent load 104. The saturable inductor L.sub.1 can be configured to saturate at an operational point at which the high-inertia current source 102 would otherwise experience a slowdown in the rate of current rise. For instance, the saturable inductor L.sub.1 can be configured to saturate at a time t.sub.saturation that is within the linear operational period t.sub.1.fwdarw.t.sub.2 of the system 100. In exemplary embodiments, t.sub.saturation can be less than or equal to about 100 nanoseconds after t.sub.0 (a time at which the discharge switch S.sub.2 is closed). The plot 204 shows that without the saturable inductor L.sub.1, the load current I.sub.RL delivered by the current source 102 would exhibit a slowing rate of rise at the time t.sub.saturation. The saturable inductor L.sub.1 is configured to saturate at the time t.sub.saturation to offset the slowing rate of rise of the load current I.sub.RL. Thus, from the time t.sub.saturation to the time t.sub.2, the plot 202 of the load current delivered by the high-inertia current source 102 shows that the current source 102 continues to operate in the linear operation region. By contrast, the plot 204 shows that the load current I.sub.RL delivered by a current source without the saturable inductor L.sub.1 enters sinusoidal operational region.

(18) It is to be understood that while the time at which the saturable inductor L.sub.1 saturates, t.sub.saturation, is described herein as being a same time at which a current source without the saturable inductor L.sub.1 would exhibit a drop-off in current rise, the saturable inductor L.sub.1 can instead be configured to saturate prior to a time at which the load current I.sub.RL would drop off in the current source without the saturable inductor L.sub.1. This can account for any time constants due to other parameters of the circuit that may delay the effect of saturation of the inductor L.sub.1 on the load current I.sub.RL.

(19) As indicated by the plots 202, 204, the rate of rise of the load current I.sub.RL(t) and the peak current I.sub.peak are greater for the high-inertia current source 102 than a current source that does not include the saturable inductor L.sub.1. Whether or not a pulse width (e.g., t.sub.4-t.sub.0) of the load current I.sub.RL(t) delivered by the high-inertia current source is wider or narrower than the load current delivered by a current source that does not include the saturable inductor will depend on various parameters of the system 100, such as line impedances.

(20) Design parameters of the saturable inductor L.sub.1 such as core geometry and core material can be selected such that the saturable inductor L.sub.1 saturates at an intended operational point (e.g., a specified discharge time elapsed, or a specified current I.sub.RL). In exemplary embodiments, the saturable inductor L.sub.1 is configured such that the inductor L.sub.1 is capable of handling a pre-defined peak current (e.g., I.sub.peak) of the system 100, and further so that the inductor L.sub.1 saturates in the linear operation period t.sub.1.fwdarw.t.sub.2.

(21) Specific component values of the voltage source V.sub.1, the capacitor C.sub.1, and the saturable inductor L.sub.1 can be selected based upon a desired profile of the load current I.sub.RL. For example, it may be desirable to operate some loads with low voltage (e.g., less than 20 V) and/or low current (e.g., less than 1 A). In such embodiments, the voltage of the voltage source V.sub.1 can be less than or equal to about 20 V. In other embodiments, it may be desirable to operate the load 104 at high voltage (e.g., greater than 100 V) and/or high current (e.g., greater than 1000 A). In such embodiments, the voltage of the voltage source V.sub.1 can be greater than or equal to about 200 V, greater than or equal to about 500 V, or greater than or equal to about 1000 V. In various exemplary embodiments, the capacitance of the discharge capacitor C.sub.1 can be between 0.01 μF and 10 μF. In further embodiments, the inductance of the saturable inductor L.sub.1 can be less than or equal to about 1 mH, 500 nH, or 100 nH. In some embodiments, the saturable inductor L.sub.1 is configured as a strip line inductor, in order to yield a sufficiently low inductance to permit saturation of the inductor L.sub.1. A peak current (e.g., I.sub.peak) delivered by the high-inertia current source 102 can be greater than or equal to about 750 A, greater than or equal to about 1000 A, or greater than or equal to about 1500 A.

(22) It is to be understood that the current through the load, I.sub.RL, will be a function of line resistances R.sub.1 and R.sub.2, line inductance L.sub.2, and the parasitic capacitance of the load C.sub.L. However, the discharge capacitor C.sub.1, the saturable inductor L.sub.1, the discharge switch S.sub.2, and interconnects among these components can be selected such that I.sub.RL is primarily determined by the impedance characteristic of the resistance of the load R.sub.L, the discharge capacitor C.sub.1, the saturable inductor L.sub.1, and the charged voltage across the discharge capacitor C.sub.1 (i.e., prior to the discharge switch S.sub.2 being closed).

(23) In exemplary embodiments, the current-dependent load 104 can be or include a bridge wire detonator. By way of example, and referring now to FIG. 3, an exemplary detonator system 300 that includes a bridge wire detonator 302, a high-inertia current source 304, and a control system 306 is shown. In exemplary embodiments, the high-inertia current source 304 can be or include the high-inertia current source 102. The bridge wire detonator 302 is configured such that, when a high-current, short-duration pulse is provided to the detonator 302, the detonator 302 explodes. Explosion of the detonator 302 can be used to initiate another explosive event by detonating a primary explosive 308. The bridge wire detonator 302 can be connected to the high-inertia current source 304 in a similar manner as the current-dependent load 104 shown in FIG. 1. The control system 306 can be configured to control operation of the high-inertia current source 304. By way of example, the control system 306 can be configured to operate a charging switch and a discharge switch (e.g., the switches S.sub.1, S.sub.2) included in the high-inertia current source 304.

(24) In further exemplary embodiments, the current-dependent load 104 can be or include a flash lamp. By way of example, and referring now to FIG. 4, an exemplary laser system 400 is illustrated. The laser system 400 includes a control system 402, a high-inertia current source 404, a flash lamp 406, and an optical gain medium 408. The control system 402 controls the high-inertia current source 404 (e.g., configurable as the high-inertia current source 102) to provide a current pulse to the flash lamp 406. The current pulse causes the flash lamp 406 to output a high-intensity optical signal to the optical gain medium 408, pumping the optical gain medium 408. The high-intensity optical signal can be configured to cause population inversion in the optical gain medium 408 such that a laser beam 410 is output by the optical gain medium 408. The high-inertia current source 404 can be configured to have a high peak current (e.g., greater than 1000 A) and a short discharge duration (e.g., less than or equal to 150 nanoseconds), facilitating a high output pulse rate of the laser system 400.

(25) FIG. 5 illustrates an exemplary methodology relating to providing and operating a high-inertia current source. While the methodology is shown and described as being a series of acts that are performed in a sequence, it is to be understood and appreciated that the methodology is not limited by the order of the sequence. For example, some acts can occur in a different order than what is described herein. In addition, an act can occur concurrently with another act. Further, in some instances, not all acts may be required to implement a methodology described herein.

(26) Moreover, the acts described herein may be or be facilitated by computer-executable instructions that can be implemented by one or more processors and/or stored on a computer-readable medium or media. The computer-executable instructions can include a routine, a sub-routine, programs, a thread of execution, and/or the like. Still further, results of acts of the methodologies can be stored in a computer-readable medium, displayed on a display device, and/or the like.

(27) Referring now to FIG. 5, a methodology 500 that facilitates providing and operating a high-inertia current source is illustrated. The methodology 500 begins at 502, and at 504, a circuit that includes a high-inertia current source is provided. In exemplary embodiments, at 504, the system 100 can be provided. In other words, at 504, a high-inertia current source circuit is provided, wherein the circuit comprises a power source, a capacitor, a charging switch that selectively couples the power source and the capacitor, a load, a saturable inductive element connected to the load, and a discharge switch that selectively couples the capacitor to the saturable inductive element. At 506, the charging switch is closed to charge the capacitor. At 508, the discharge switch is closed (e.g., subsequent to the charging switch being opened), causing the capacitor to discharge through the saturable inductor and the load. Discharging of the capacitor causes a current through the load to exhibit a substantially linear rise in a linear operational period of the circuit. During discharge of the capacitor in the linear operational period, the saturable inductor saturates, causing the load current to continue to rise in a linear fashion. Inclusion of the saturable inductor in the circuit provided at 504 allows the circuit to continue to exhibit a linear rise in load current after a time at which a current source that did not include the saturable inductor would exhibit a drop-off in the rate of rise of the load current. The methodology 500 ends at 510.

(28) What has been described above includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable modification and alteration of the above devices or methodologies for purposes of describing the aforementioned aspects, but one of ordinary skill in the art can recognize that many further modifications and permutations of various aspects are possible. Accordingly, the described aspects are intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term “includes” is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.