MANUFACTURING METHOD OF THIN FILM TRANSISTOR

Abstract

A manufacturing method of a thin film transistor is provided, which has advantages that there are sufficient hydrogen ions in an interlayer dielectric layer. In an annealing treatment, an amount of the hydrogen ions diffused into an active layer is sufficient, and the hydrogen ions enter a channel of the thin film transistor to fill non-bonded or unsaturated bonds of polysilicon atoms, thereby filling defects in the channel, repairing the defects of the active layer, reducing the number of unsteady states, and improving mobility and threshold voltage uniformity.

Claims

1. A manufacturing method of a thin film transistor, comprising: providing a substrate; forming an active layer which is patterned over the substrate, wherein the active layer is a polysilicon active layer; forming a gate dielectric layer on the active layer which is patterned; forming a gate layer which is patterned on the gate dielectric layer; forming an interlayer dielectric layer on the gate layer, wherein the interlayer dielectric layer comprises a first interlayer dielectric layer and a second interlayer dielectric layer; and implanting hydrogen ions into the interlayer dielectric layer and performing an annealing treatment, wherein the hydrogen ions are diffused to the active layer through the interlayer dielectric layer, and the active layer is subjected to a hydrogenation treatment.

2. The manufacturing method of the thin film transistor as claimed in claim 1, wherein temperature of the annealing treatment ranges between 330 degrees Celsius and 400 degrees Celsius.

3. The manufacturing method of the thin film transistor as claimed in claim 1, wherein after the hydrogenation treatment, the manufacturing method further comprises: forming a source hole and a drain hole inside the interlayer dielectric layer and the gate dielectric layer, wherein the source hole corresponds to a source region of the active layer, and the drain hole corresponds to a drain region of the active layer; and correspondingly forming a source and a drain in the source hole and the drain hole.

4. A manufacturing method of a thin film transistor, comprising: providing a substrate; forming an active layer which is patterned over the substrate; forming a gate dielectric layer on the active layer which is patterned; forming a gate layer which is patterned on the gate dielectric layer; forming an interlayer dielectric layer on the gate layer; and implanting hydrogen ions into the interlayer dielectric layer and performing an annealing treatment, wherein the hydrogen ions are diffused to the active layer through the interlayer dielectric layer, and the active layer is subjected to a hydrogenation treatment.

5. The manufacturing method of the thin film transistor as claimed in claim 4, wherein the active layer is a polysilicon active layer.

6. The manufacturing method of the thin film transistor as claimed in claim 4, wherein the interlayer dielectric layer comprises a first interlayer dielectric layer and a second interlayer dielectric layer.

7. The manufacturing method of the thin film transistor as claimed in claim 4, wherein temperature of the annealing treatment ranges between 330 degrees Celsius and 400 degrees Celsius.

8. The manufacturing method of the thin film transistor as claimed in claim 4, wherein after the hydrogenation treatment, the manufacturing method further comprises: forming a source hole and a drain hole inside the interlayer dielectric layer and the gate dielectric layer, wherein the source hole corresponds to a source region of the active layer, and the drain hole corresponds to a drain region of the active layer; and correspondingly forming a source and a drain in the source hole and the drain hole.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0019] FIG. 1 is a schematic structural diagram of a low temperature polysilicon thin film transistor in the prior art.

[0020] FIG. 2 is a flowchart of manufacturing a thin film transistor.

[0021] FIG. 3A to FIG. 3H are schematic diagrams showing manufacturing a thin film transistor.

DETAILED DESCRIPTION

[0022] Specific embodiments of a manufacturing method of a thin film transistor provided by the present disclosure will be described in detail below with reference to accompanying drawings.

[0023] The present disclosure provides a manufacturing method of a thin film transistor. FIG. 2 is a flowchart of manufacturing a thin film transistor. FIG. 3A to FIG. 3H are schematic diagrams showing manufacturing a thin film transistor.

[0024] Referring to a step S20 and FIG. 3A, a substrate 300 is provided. The substrate 300 may include a hard substrate (such as a glass substrate and a ceramic substrate) and a flexible substrate (such as a plastic substrate or a substrate formed by a suitable material). After this step, a step of forming a buffer layer 301 on the substrate 300 is further included. The buffer layer 301 may be made of silicon nitride or silicon oxide, and may be formed by chemical vapor deposition (CVD).

[0025] Referring to a step S21 and FIG. 3B, a patterned active layer is formed on the substrate 300. In this embodiment, an active layer is formed on the buffer layer 301. The active layer may be a polysilicon. The formation method of the polysilicon active layer includes, but is not limited to, forming an amorphous silicon layer on the buffer layer 301. The amorphous silicon layer is subjected to laser irradiation to realize a crystalline transition to a polysilicon layer, and then the polysilicon layer is etched to form two polysilicon islands, i.e., a first active layer 302 and a second active layer 303. The method of the present disclosure is not only applicable to a case where the active layer is polysilicon, but also applies to a case where the active layer is other materials but needs to be hydrogenated.

[0026] Furthermore, the first active layer 302 is doped to form a first channel 3021, N.sup.+ regions 3022, and N.sup.− regions 3023, where two N.sup.+ regions 3022 are oppositely disposed on both sides of the first channel region 3021, and two N.sup.− regions 3023 are oppositely disposed on two outsides of the N.sup.+ regions 3022. The second active layer 303 is doped to form a second channel 3031 and P.sup.+ regions 3032, where two P.sup.+ regions 3032 are oppositely disposed on both sides of the second channel 3031. The method of doping includes, but is not limited to, ion implantation.

[0027] Referring to a step S22 and FIG. 3C, a gate dielectric layer 305 is formed on the patterned active layer. In this step, a gate dielectric layer 305 is deposited on the buffer layer 301, the first channel 3021, the N.sup.+ regions 3022, the N.sup.− regions 3023, the second channel 3031, and the P.sup.+ regions 3032 by a chemical vapor deposition method. Also, the first channel 3021, the N.sup.+ regions 3022, the N.sup.− regions 3023, second channel 3031, and the P.sup.+ regions 3032 are encapsulated in the gate dielectric layer 305. The gate dielectric layer 305 includes, but is not limited to, a silicon dioxide layer.

[0028] Referring to a step S23 and FIG. 3D, a patterned gate layer 306 is formed on the gate dielectric layer 305. The patterned gate layer 306 is formed by depositing a metal layer on the gate dielectric layer 305. The metal layer is patterned by etching or the like, thereby forming the patterned gate layer 306. The gate layer 306 can be made of a conventional metal material in the art, such as metallic molybdenum.

[0029] Referring to a step S24 and FIG. 3E, an interlayer dielectric layer 307 is formed on the gate layer 306. Material of the interlayer dielectric layer 307 includes, but is not limited to, SiOx or SiNx. In this embodiment, the interlayer dielectric layer 307 includes a first interlayer dielectric layer 3071 and a second interlayer dielectric layer 3072, which are sequentially formed on the gate layer 306. The first interlayer dielectric layer 3071 is SiOx, and the second interlayer dielectric layer 3072 is SiNx. The present disclosure is not limited thereto, and other configurations may be employed in other embodiments.

[0030] Referring to a step S25 and FIG. 3F, hydrogen ions are implanted to the interlayer dielectric layer 307, and an annealing treatment is performed. The hydrogen ions are diffused to the active layer through the interlayer dielectric layer 307, and the active layer is subjected to a hydrogenation treatment. In this step, sufficient hydrogen ions are supplied to the interface dielectric layer 307 to enable sufficient hydrogen ions to be transmitted to the active layer, thereby hydrogenating the active layer to repair defects of the active layer.

[0031] An ion implantation technique, such as a plasma ion implantation immersion technique or an ion bath doping technique, is employed to implant hydrogen ions. These methods are conventional methods of ion implantation and will not be described again.

[0032] When the hydrogen ions are implanted into the interlayer dielectric layer 307, the thin film transistor is heated to be subjected to the annealing treatment to diffuse the hydrogen ions to the active layer, thereby repairing defects of the active layer. Temperature of the annealing treatment ranges between 330 degrees Celsius and 400 degrees Celsius.

[0033] Referring to a step S26 and FIG. 3G, a source hole 308 and a drain hole 309 are respectively formed in an internal layer of the interlayer dielectric layer 307. The source hole 308 corresponds to a source region of the active layer, and the drain hole 309 corresponds to a drain region of the active layer. The method of forming the source hole 308 and the drain hole 309 may be a method known in the art, such as etching.

[0034] Referring to a step S27 and FIG. 3H, a source 310 and a drain 311 are respectively formed in the source hole 308 and the drain hole 309, thereby completing the fabrication of the low temperature polysilicon thin film transistor. The source 310 and the drain 311 can be formed by photolithography and etching processes.

[0035] In the present disclosure, an external hydrogen ions source is additionally provided while the interlayer dielectric layer 307 and the gate dielectric layer 305 which contain hydrogen ions, so that there are sufficient hydrogen ions in the interlayer dielectric layer 307. In the annealing treatment, an amount of the hydrogen ions diffused into the active layer is sufficient, and the hydrogen ions enter a channel of the thin film transistor to fill non-bonded or unsaturated bonds of polysilicon atoms, thereby filling defects in the channel, repairing the defects of the active layer, preventing from decreasing performance of the thin film transistor due to a large number of defects and dangling bonds in the channel, reducing the number of unsteady states, and improving mobility and threshold voltage uniformity.

[0036] The above descriptions are merely preferable embodiments of the present disclosure. Any modification or replacement made by those skilled in the art without departing from the principle of the present disclosure should fall within the protection scope of the present disclosure.

[0037] The subject matter of the present disclosure can be manufactured and used in the industry with industrial applicability.