PHOTODETECTOR, MODULATOR, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS

Abstract

The present invention relates to a photodetector (3) comprising: a longitudinal portion (12) of a waveguide (11) which comprises or is formed by two waveguide segments (12a, 12b), which extend at least substantially parallel to one another in the longitudinal direction and are preferably distanced from one another in the transverse direction, forming a gap (14) between them; and an active element (13), which overlies the longitudinal portion (12) of the waveguide and comprises at least one material or consists of at least one material that absorbs electromagnetic radiation of at least one wavelength and generates an electric photosignal as a result of the absorption, the two waveguide segments (12a, 12b) each being in contact, at least in some portions, on at least one side, in particular on the side facing the active element (14), with a gate electrode (15a, 15b) which preferably comprises silicon or consists of silicon.

Claims

1. Photodetector (3) comprising a longitudinal section (12) of a waveguide (11), which comprises or is formed by two waveguide segments (12a, 12b) extending in the longitudinal direction and at least substantially parallel to one another, the waveguide segments (12a, 12b) being spaced apart from one another preferably in the transverse direction forming a gap (14) extending therebetween, and an active element (13), which overlaps the longitudinal section (12) of the waveguide and comprises or consists of at least one material which absorbs electromagnetic radiation of at least one wavelength and, as a result of the absorption, generates an electrical photosignal, wherein the two waveguide segments (12a, 12b) respectively are in contact, on at least one side, in particular on the side facing the active element (14), at least in sections with a gate electrode (15a, 15b) preferably comprising silicon or consisting of silicon.

2. Photodetector (3) according to claim 1, wherein the gate electrodes (15a, 15b) are each in contact at their underside with the upper side of a waveguide segment (12a, 12b) and are each in contact with their upper side with the underside of a dielectric coat provided between the active element (13) and the waveguide segments (12a, 12b).

3. Photodetector (3) according to claim 1, wherein the gate electrodes (15a, 15b) comprise or consist of a material which is transparent for electromagnetic radiation of at least one wavelength and/or electrically conductive.

4. Photodetector (3) according to claim 1, wherein each of the two gate electrodes (15a, 15b) is associated with a connecting element (8) in contact therewith, and in each case one of the connecting elements (8) extends through one of the waveguide segments (12a, 12b).

5. Photodetector (3) according to claim 1, wherein the active element (13) overlaps the two waveguide segments (12a, 12b) and the gap (14) lying therebetween at least in sections.

6. Photodetector (3) comprising a longitudinal section (12) of a waveguide (11) and an active element (13) comprising or consisting of at least one material which absorbs electromagnetic radiation of at least one wavelength and, as a result of the absorption, generates an electrical photosignal, wherein two carrier elements (20) are arranged on opposite sides of the longitudinal section (12) of the waveguide (11) spaced therefrom forming two gaps (21), wherein the two gaps (21) are free of material, and wherein the active element (13) overlaps the longitudinal section (12) of the waveguide (1) and the two gaps (21) and at least sections of the two carrier elements (20) preferably in the transverse direction.

7. Photodetector (3) according to claim 6, wherein the active element (13) lies on the upper side of the longitudinal section (12) of the waveguide (11) facing the active element (13) and/or on the upper side of the carrier elements (20) facing the active element (13).

8. Photodetector (3) according to claim 1, wherein the at least one material of the active element (13), which absorbs electromagnetic radiation of at least one wavelength and generates an electrical photosignal as a result of the absorption, is graphene, and/or at least one dichalcogenide, in particular two-dimensional transition dichalcogenide, and/or heterostructures of two-dimensional materials and/or germanium and/or at least one electro-optical polymer and/or silicon and/or at least one compound semiconductor, in particular at least one III-V semiconductor and/or at least one II-VI semiconductor.

9. Modulator (22) comprising a longitudinal section (12) of a waveguide (11), which comprises or is formed by four waveguide segments (12a, 12b, 12c, 12d) extending in the longitudinal direction and at least substantially parallel to one another, and two active elements (13) comprising or consisting of at least one material whose refractive index changes as a function of a voltage and/or the presence of charge and/or electric field, or one such active element (13) and an electrode, wherein a lower one of the waveguide segments (12a) is arranged between the two active elements (13) or between the active element (13) and the electrode, a middle one of the waveguide segments (12b) is arranged above the two active elements (13) or above the active element (13) and the electrode and the two remaining, upper waveguide segments (12c, 12d) are arranged above the middle waveguide segment (12b), wherein the two upper waveguide segments (12c, 12d) are spaced apart from each other, preferably in the transverse direction, forming a gap (14) extending therebetween.

10. Modulator (22) comprising a longitudinal section (12) of a waveguide (11), which comprises or is formed by five waveguide segments (12a, 12b, 12c, 12d, 12e) extending in the longitudinal direction and at least substantially parallel to one another, and two active elements (13) comprising or consisting of at least one material whose refractive index changes as a function of a voltage and/or the presence of charge and/or an electric field, or such an active element (13) and an electrode, wherein two lower ones of the waveguide segments (12a, 12b) are arranged below the active elements (13) or below the active element (13) and the electrode and are spaced apart from each other preferably in the transverse direction forming a gap (14) extending therebetween, and a first middle one of the waveguide segments (12c) is arranged between the two active elements (13) or between the active element (13) and the electrode, and a second middle waveguide segment (12d) is arranged above the two active elements (13) or above the active element (13) and the electrode, and an upper waveguide segment (12e) is arranged above the second middle waveguide segment (12d).

11. Modulator (22) comprising a longitudinal section (12) of a waveguide (11), which comprises or is formed by six waveguide segments (12a, 12b, 12c, 12d, 12e, 12f) extending in the longitudinal direction and at least substantially parallel to one another, and two active elements (13) comprising or consisting of at least one material whose refractive index changes as a function of a voltage and/or the presence of charge and/or an electric field, or such an active element (13) and an electrode, wherein two lower ones of the waveguide segments (12a, 12b) are arranged below the active elements (13) or below the active element (13) and the electrode and are spaced apart from one another, preferably in the transverse direction, forming a gap (14) extending therebetween, and a first middle one of the waveguide segments (12c) is arranged between the two active elements (13) or between the active element (13) and the electrode, and a second middle waveguide segment (12d) is arranged above the two active elements (13) or above the active element (13) and the electrode, and the two remaining upper waveguide segments (12e, 12f) are arranged above the second middle waveguide segment (12d), wherein the two upper waveguide segments (12e, 12f) are spaced apart from each other, preferably in the transverse direction, forming a gap (14) extending therebetween.

12. Modulator (22) according to claim 9, wherein the two active elements (13) or the active element (13) and the electrode are spaced apart from one another and are arranged offset from one another in such a way that they lie one above the other in sections thus forming an overlap region (23).

13. Modulator (22) according to claim 9, wherein the overlap region (23) is located above or below the gap (14).

14. Modulator (22) according to claim 11, wherein the overlap region (23) is located above one gap (14) and below the other gap (14).

15. Modulator (22) according to claim 9, wherein exactly one gap (14) formed between two waveguide segments (12a-12f) spaced apart from one another is provided above the two active elements (13) or above the active element and the electrode, and/or in that exactly one gap (14) formed between two waveguide segments (12a-12f) spaced apart from one another is provided below the two active elements (13) or below the active element (13) and the electrode.

16. Modulator (22) according to claim 9, wherein the extension of the overlap region (23) in the transverse direction corresponds to the range from 0.8 times to 1.8 times, preferably 1.0 times to 1.5 times, of the extension of the gap (14) or at least one of the gaps (14) in the transverse direction.

17. Modulator (22) according to claim 9, wherein the at least one material of at least one of the active elements (13), whose refractive index changes as a function of a voltage and/or the presence of charge and/or an electric field, is graphene, and/or at least one dichalcogenide, in particular two-dimensional transition dichalcogenide, and/or heterostructures of two-dimensional materials and/or germanium and/or lithium niobate and/or at least one electro-optical polymer and/or silicon and/or at least one compound semiconductor, in particular at least one III-V semiconductor and/or at least one II-VI semiconductor.

18. Photodetector (3) or modulator (22) according to claim 1, wherein the longitudinal section (12) of the waveguide (11) is arranged on or above a planarization coat (2, 17), wherein the planarization coat (2, 17) is preferably characterized, at least in sections, by a roughness in the range from 1.0 nm RMS to 0.1 nm RMS, in particular 0.6 nm RMS to 0.1 nm RMS, preferably 0.4 nm RMS to 0.1 nm RMS, on the side, on which the longitudinal section (12) of the waveguide (11) is arranged on, and/or in that the longitudinal section (12) of the waveguide (11) is embedded at least in sections in a planarization coat (2, 17) and the active element (13) or one of the active elements (13) is arranged on the planarization coat (2, 17), wherein the planarization coat (2, 17) is preferably characterized, at least in sections, by a roughness in the range from 1.0 nm RMS to 0.1 nm RMS, in particular from 0.6 nm RMS to 0.1 nm RMS, preferably from 0.4 nm RMS to 0.1 nm RMS, on the side on which the active element (13) is arranged on.

19. Photodetector (3) or modulator (22) according to claim 1, wherein the longitudinal section (12) of the waveguide (11) comprises or consists of titanium dioxide and/or aluminium nitride and/or tantalum pentoxide and/or silicon nitride and/or aluminium oxide and/or silicon oxynitride and/or lithium niobate and/or silicon, in particular polysilicon, and/or indium phosphite and/or gallium arsenide and/or indium gallium arsenide and/or aluminium gallium arsenide and/or at least one dichalcogenide, in particular two-dimensional transition metal dichalcogenide, and/or chalcogenide glass and/or heterostructures of two-dimensional materials and/or resins or resin-containing materials, in particular SU8, and/or polymers or polymer-containing materials, in particular OrmoClad and/or OrmoCore.

20. Semiconductor apparatus comprising a chip and at least one photodetector (3) and/or modulator (22), preferably a plurality of photodetectors (3) and/or modulators (22) according to claim 1, wherein the photodetector(s) (3) and/or modulator(s) (22) are preferably arranged on the chip or on a coat arranged on or above the chip.

21. Semiconductor apparatus according to claim 20, wherein the photodetector (3) and/or modulator (22) is part of a photonic platform fabricated on the chip or bonded to the chip.

22. Semiconductor device comprising a wafer (1) and at least one photodetector (3) and/or modulator (22), preferably a plurality of photodetectors (3) and/or modulators (22) according to claim 1, wherein the photodetector(s) (3) and/or modulator(s) (22) are preferably arranged on the wafer (1) or on a coat (2) arranged on or above the wafer (1).

23. Semiconductor device according to claim 22, wherein the photodetector (3) and/or modulator (22) is part of a photonic platform fabricated on or bonded to the wafer (1).

Description

[0119] With regard to embodiments of the invention, reference is also made to the sub-claims as well as to the following description of several example embodiments with reference to the accompanying drawing.

[0120] In the drawing shows:

[0121] FIG. 1 a partial section through a semiconductor device comprising an embodiment of a photodetector according to the first aspect of the invention;

[0122] FIG. 2 a top view of the photodetector of FIG. 1;

[0123] FIG. 3 a partial section through a semiconductor device with a further embodiment of a photodetector according to the first aspect of the invention;

[0124] FIG. 4 a partial section through a semiconductor device with an embodiment of a photodetector according to the second aspect of the invention;

[0125] FIG. 5 a partial section through a semiconductor device with an embodiment of an electro-optical modulator according to the third aspect of the invention;

[0126] FIG. 6 a partial section through a semiconductor device with an embodiment of an electro-optical modulator according to the fourth aspect of the invention;

[0127] FIG. 7 a partial section through a semiconductor device with an embodiment of an electro-optical modulator according to the fifth aspect of the invention; and

[0128] FIG. 8 the steps of the method of fabricating the device according to FIG. 1.

[0129] All figures show purely schematic representations. In the figures, the same components or elements are given the same reference signs.

[0130] FIG. 1 shows a partial section through an embodiment of a semiconductor device according to the invention.

[0131] It comprises a wafer 1, a planarization coat 2 fabricated on the wafer 1 and a plurality of photodetectors 3 fabricated on the planarization coat 2. In the partial section according to FIG. 1, only one of the photodetectors 3 is shown as exemplarily.

[0132] The wafer 1 comprises a single-piece silicon substrate 4 and a plurality of integrated electronic components 5, which, in the example shown, extend in the semiconductor substrate 4. The integrated electronic components 5, which may in particular be transistors and/or resistors and/or capacitors, are indicated in the schematic FIG. 1 only simplified by a line with hatching provided with the reference sign 5. In a corresponding position in the substrate 4, a large number of integrated electronic components 5 are found in a sufficiently known manner. These can also be components of processors, such as CPUs and/or GPUs, or form such components in a likewise known manner.

[0133] The wafer 1 has a front-end-of-line (FEOL for short) 6, in which the plurality of integrated electronic components 5 are arranged, and a back-end-of-line (BEOL for short) 7 lying thereabove, in which or via which the integrated electronic components 5 of the front-end-of-line 6 are interconnected by means of different metal planes. The integrated electronic components 5 in the FEOL 6 and the associated interconnection in the BEOL 7 form integrated circuits of the wafer 1 in a manner that is sufficiently pre-known. A FEOL 6 is also sometimes referred to as transistor front-end and a BEOL 7 as a metal back-end. The metal planes comprise a plurality of interconnection elements 8, which in the present case are given by so-called VIAs, which is the abbreviation for Vertical Interconnect Access. The VIAs 8 consist of metal, for example copper, aluminium or tungsten.

[0134] The planarization coat is fabricated on the upper side 9 of the wafer 1 facing away from the front-end-of-line 6 and consists of a dielectric material. In the present case, the planarization coat 2 consists of silicon dioxide (SiO.sub.2), although this is to be understood as exemplary and other materials may also be used.

[0135] In the embodiment shown, the planarization coat 2 is a coat obtained by deposition of the corresponding coating material, in this case SiO.sub.2, on the upper side 9 of the wafer 1 facing away from the front-end-of-line 6 and subsequent planarization treatment of the deposited material on the upper side 10 facing away from the wafer. Due to the treatment on its upper side 10 facing away from the wafer 1, the planarization coat 2 is presently characterized by a roughness of 0.2 nm RMS, wherein this is to be understood as exemplary.

[0136] In the example shown, the planarization coat 2 extends over the entire upper side 9 of the wafer 1. The material of the planarization coat 2 has been deposited over the entire upper side 9 of the wafer 1. This is therefore characterized by a diameter which at least substantially corresponds to that of the wafer 1.

[0137] The photodetectors 3 fabricated on the planarization coat 2 are embodiments of a photodetector 3 according to the first aspect of the invention. In the embodiment, these are all identical in construction, although this is not to be understood restrictively.

[0138] In the following, the design of the detectors 3 and also their fabrication will be described by way of example on the basis of the one detector 3 shown in FIG. 1. Also, with regard to the embodiments of further detectors and modulators described further below (cf. FIGS. 3 to 6), the design is explained on the basis of the one example shown in the partial sections.

[0139] The (respective) photodetector 3 comprises a longitudinal section 12 of one of the waveguides 11, namely that longitudinal section which is overlapped by an active element 13 of the photodetector 3. In FIG. 2, which shows the active element 13 and the underlying waveguide 11 in purely schematic top view, the longitudinal section 12 of the waveguide covered here by the active element 13 is shown with dashed lines.

[0140] Dielectrics, preferably titanium dioxide, which was also used in the embodiment shown, are particularly suitable as waveguide materials. Alternatively or additionally, one or more waveguides 11 of aluminium nitride and/or tantalum pentoxide and/or silicon nitride and/or aluminium oxide and/or silicon oxynitride and/or lithium niobate or also of semiconductors such as silicon, indium phosphide, gallium arsenide, indium gallium arsenide, aluminium gallium arsenide or dichalcogenides or chalcogenide glass or polymers such as SU8 or Ormo-Clad and/or OrmoCore can be provided.

[0141] The longitudinal section 12 of the waveguide is formed here by two waveguide segments 12a, 12b extending in longitudinal direction and at least substantially parallel to each other and spaced apart from each other in the transverse direction (from left to right or vice versa in the figure) to form a gap 14 extending therebetween. It accordingly is a slot waveguide. By means of such a waveguide 11, the optical mode is guided in the gap 14 during operation. In the example shown, the two waveguide segments are characterized by a rectangular cross-section. The gap 14 can be filled with SiO.sub.2, for example.

[0142] The two waveguide segments 12a, 12b are each in contact with a silicon gate electrode 15a, 15b at least on one side, in this case on their side facing the active element 13. The gate electrodes 15a, 15b are formed by a silicon coat or silicon coating fabricated on the respective waveguide segment 12a, 12b.

[0143] The active element 13 comprises at least one material or consists of at least one material which absorbs electromagnetic radiation of at least one wavelength and generates an electrical photosignal as a result of the absorption. In the example shown, it is given by a graphene film 13. Graphene may also change its refractive index (refractivity and/or absorption) as a function of a voltage and/or charge and/or an electric field. It should be emphasized that it is also possible that the active element 13 is given by a film comprising or consisting of at least one other or further electro-optically active material, for example a film comprising or consisting of a dichalcogenide-graphene heterostructure consisting of at least one layer of graphene and at least one layer of a dichalcogenide, or by a film comprising at least one layer of boron nitride and at least one layer of graphene.

[0144] As can be seen from FIG. 1, the graphene film 13 is arranged on the upper side 16, facing away from the wafer 1, of a further planarization coat 17 in which the waveguide 11 and thus its longitudinal section 12 is embedded. The further planarization coat 17 consists of the same material as the planarization coat 2 and is characterized at its upper side 16 by the same roughness as the upper side 10 of the planarization coat 2. However, this is to be understood only exemplarily and not restrictively.

[0145] By means of the gate electrodes 15a, 15b provided on the waveguide segments 12a, 12b, a pnjunction can be realized in the graphene film 13 in the region extending above the gap 14 and thus in the region of an optical mode guided in operation in the gap 14 of the waveguide 11. A pnjunction can be used to separate electron-hole pairs generated by absorption to produce a photocurrent. Likewise, the thermoelectric effect can be exploited in graphene, where Seebeck coefficients of opposite sign are created in the p and n regions, resulting in a thermoelectric voltage when heated by the absorbed energy (the photons).

[0146] It should be noted that the connection of the gate electrodes 15a, 15b for power supply, which is not shown further, can be located, for example, laterally next to the VIAs 8.

[0147] The photodetector 3, specifically its graphene film 13, is electrically conductively connected to at least one of the integrated electronic components 5 of the front-end-of-line 6 of the wafer 1. As can be seen in the schematic sectional view according to FIG. 1, the connection is realized by the VIAs 8 of the back-end-of-line 7 of the wafer 1 as well as further VIAs 8, which extend through the planarization coat 2 and any further coats or elements present thereon, in this case the further planarization coat 17.

[0148] In concrete terms, the graphene film 13 is electrically conductively connected at opposite end regions via contacts or contact elements 18 with the upper end of VIAs 8, which extend through the further planarization coat 17 and planarization coat 2 to the back-end-of-line 7 of wafer 1. In the top view of FIG. 2, the VIAs 8 in connection with the contact elements 18, which VIAs 8 lie below the contact elements 18, are indicated with a thin line.

[0149] In the example shown, a passivation coat 19 is provided on the graphene films 13, which comprises or consists of aluminium oxide (AL.sub.2O.sub.3) and/or silicon dioxide (SiO.sub.2).

[0150] A photodetector 3, as shown in FIG. 1 and in FIGS. 3 and 4, which will be explained below, can be used in a manner known per se, in particular for signal conversion back from the optical to the electronic world.

[0151] To obtain the semiconductor device shown in FIG. 1, in a first step S1 (cf. FIG. 8) the wafer 1 is provided with the integrated circuits comprising the integrated electronic components 5 and the metallization including the VIAs 8. The wafer 1 may be any wafer 1 of conventional type obtained by a previously known fabricating process.

[0152] In a second step S2, the planarization coat 2 is fabricated on the back-end-of-line 7 of the wafer 1. For this purpose, a coating material, in this case silicon dioxide (SiO.sub.2), is applied, which can be done, for example, by chemical vapor deposition, such as low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition, or physical vapor deposition or also by spinning on spin-on glass. In the present case, PECVD is used. After the coating material has been deposited, the upper side of the coating obtained is subjected to a planarization treatment (step S3), in this case resist planarization, whereby an upper side 10 having a roughness of 0.2 nm RMS is obtained.

[0153] The resist planarization includes a single or repeated spin-on glass spinning on and subsequent etching, presently reactive ion etching (RIE). The spin-on-glass coat partially compensates for height differences, i.e., valleys of the topology have a higher coat thickness after spin-on-glass coating than adjacent elevations. If the entire spin-on-glass coat is etched after spin-on-glass coating, for example by RIE, the height difference has been reduced due to the planarizing effect of the spin-on-glass coat. By repetition, the height difference can be further reduced until the desired roughness is obtained. It should be noted that an upper side 10 of the planarization coat 2 corresponding to low roughness can alternatively be obtained, for example, by means of chemical mechanical polishing (CMP).

[0154] In a next step S4, which represents the first step in the fabrication of the detector 3, the (respective) waveguide 11 with the gate electrodes 15a, 15b is fabricated. For this purpose, waveguide material, presently titanium dioxide (TiO.sub.2), is deposited, in particular over the entire upper side 10 of the obtained planarization coat 2. The deposition can be carried out by PVD or CVD, in particular PECVD or LPCVD, or by spinning on, just as for the planarization coat. Atomic layer deposition (ALD) can also be carried out or a transfer print process. In analogy to the planarization coat 2, LPCVD is used.

[0155] Subsequently, the coating material for the gate electrodes 15a, 15b, gate electrode material, in this case silicon, is deposited, for example by means of PVD or CVD processes and preferably also in a two-dimensional manner.

[0156] Lithography and structuring, in particular by means of reactive ion etching (RIE), are carried out in order to obtain the individual waveguides 11 with the individual waveguide segments 12a, 12b with the respective gap 14 lying therebetween and the individual gate electrodes 15a, 15b.

[0157] In a next step S5, the further planarization coat 17 is fabricated on the waveguides 11 with gate electrodes 15a, 15b provided thereon and the upper side 10 of the planarization coat 2. This is obtained in a completely analogous manner to the planarization coat 2 by deposition by means of PECVD and resist planarization. During or due to the material deposition, the gap 14 is also filled with SiO.sub.2. As a result of the resist planarization, the cross-section of the further planarization coat 17 above the waveguide 11 is trapezoidal (see FIG. 1).

[0158] Also, with regard to the further planarization coat 17, it applies that alternatively to LPCVD and CMP, other of the above-mentioned processes can be used and another planarization treatment, such as CMP, and/or further planarization is possible, as described above for the planarization coat 2.

[0159] The planarization coat 2 and further planarization coat 17 may comprise one or more cover layers which are preferably provided on the surface subjected to planarization treatment and which may be, for example, dichalcogenide layers or dichalcogenide heterostructures or also boron nitride layers. These materials are preferably deposited or transferred without the need for further chemical-mechanical polishing or further resist planarization, although this is not excluded.

[0160] For the sake of completeness, it should be noted that in the event that a semiconductor device according to the invention is also to have regions without a further planarization coat 17, for example also regions in which the structure corresponds to that according to FIGS. 3 to 6, the further planarization coat 17 (and any coats located thereon) is subsequently partially removed again, in particular by lithography and etching.

[0161] In step S6, the VIAs 8 are fabricated through the planarization coat 2 and the further planarization coat 17. In principle, this can be done in any way known from the prior art. In particular, the regions in which they are to extend are first defined, preferably by lithography, and dry-chemically etched by means of RIE. Then metallization is carried out and the metallized surface is structured, for example by means of CMP (Damascene process) or by lithography and RIE. It is possible that the VIAs 8 are fabricated after completion of the further planarization coat 17 through both planarization coats 2, 17 or also after completion of the first coat 2 sections thereof through the first planarization coat 2 and after completion of the second planarization coat 17 sections thereof through the second coat 17.

[0162] In step S7, the active element of the (respective) detector 3 given by a graphene film 13 is provided on the upper side 16 of the further planarization coat 17, for example deposited on the upper side 16.

[0163] The deposition of the graphene film 13 of the (respective) detector can be carried out, for example, by means of a transfer process as described in more detail above. Then, in particular, in each case a graphene film fabricated on a separate substrate or a separate metal foil or a separate germanium wafer is transferred to the further planarization coat 17. It is also possible that the (respective) graphene film 13 is fabricated directly on the further planarization coat 17. This may include, for example, a material deposition.

[0164] If a transfer process is used, it is possible that the passivation coat is already provided on the upper side of the respective graphene film 13, that this has been deposited thereon, for example, and is then transferred with it. Alternatively, a passivation coat may also be deposited after the graphene film(s) 13 has/have been transferred or fabricated.

[0165] It is also possible that first a full-area graphene film and/or a full-area passivation coat is fabricated on the further planarization coat 17, which extend over the entire surface of the further planarization coat 17. In this case, structuring is then still carried out, in particular by lithography and RIE, in order to obtain the individual graphene films 13 as active elements of several detectors 3.

[0166] The contact elements 18 are then fabricated (step S8), preferably by depositing metal over the entire surface and then again structuring by lithography and RIE to obtain the individual elements 18.

[0167] In a penultimate step S9, the upper passivation coat 19 preferably of Al.sub.2O.sub.3 and/or SiO.sub.2 is deposited. In this coat, openings, in particular for contact elements, are then expediently fabricated by means of lithography and RIE (step S10). Preferably, openings are made to contact elements which serve to connect the photonics and/or electronics to the outside.

[0168] FIG. 3 shows a further embodiment of a photodetector 3 according to the first aspect of the invention.

[0169] This differs from that according to FIG. 1 essentially in that the two waveguide segments 12a, 12b of the longitudinal section 12 of the waveguide 11 do not have a rectangular cross-section and there is no further planarization coat 17, but instead the active element, which is also given here—by way of example—by a graphene film 13, is arranged on a dielectric coat provided on the gate electrodes 15a, 15b, which cannot be seen in the figure. The dielectric coat represents a gate dielectric. It is characterized on its upper side by a roughness of 0.2 nm RMS. Its thickness is 15 nm, wherein these two values are to be understood purely as examples.

[0170] As can be seen, each of the two waveguide segments 12a, 12b has an end region facing the gap 14 located between the two segments 12a, 12b, the cross-section of which widens in sections in the direction of the gap 14. As can be seen, the two end regions and the gap 14 form a central, trapezoidal region. The sections or regions of the segments 12a, 12b adjoining this trapezoidal region on both sides are characterized by a constant thickness, as can be seen.

[0171] The two gate electrodes 15a, 15b each extend in the transverse direction over only a section of the upper side of the respective segment 12a, 12b.

[0172] In FIG. 3, the VIAs 8 associated with the gate electrodes 15a, 15b and each in contact with a gate electrode 15a, 15b can be seen. Via these, a connection is made to at least one integrated electronical component 5 from the FEOL 6, but this is not visible in the figure for reasons of simplified representation. As can be seen, these VIAs 8 extend in each case through the planarization coat 2 and that waveguide segment 12a, 12b on which the respective gate electrode 15a, 15b is arranged. The voltage supply of the gate electrodes 15a, 15b is ensured via the VIAs 8. In the example shown in FIG. 3, too, a pn junction can be obtained in the graphene film 13 via the gate electrodes 15a, 15b during operation, again in the region extending above the gap 14 in which the optical mode is guided during operation.

[0173] To obtain the arrangement according to FIG. 3, the steps S1 to S3 can be identical to those for the fabrication of the arrangement of FIG. 1.

[0174] In step S4, an adapted etching process, in particular RIE process, is carried out for the fabrication of the waveguides 11 and gate electrodes 15, 15b, after the waveguide material has also been deposited here over the area, for example in the same way as described above in connection with FIG. 1, in order to obtain the trapezoidal region with the beveled edges. An isotropic etching behavior of the RIE process can be obtained for example by an increased process pressure and adapted gas mixture compared to the anisotropic etching process. The increased process pressure, for example 20 mTorr compared to 10 mTorr, gives the etching process an undirected component, which causes a higher removal rate at the upper edge due to the longer etching time. Subsequently, first the VIAs 8 for the gate electrodes 15a, 15b are fabricated and then again material for the gate electrodes 15a, 15b, such as silicon, is deposited.

[0175] Then the (respective) slot 14 and the gate electrodes 15a, 15b are etched. As a result, the gate electrode coat, which is initially full-surface, is “divided”.

[0176] Step S5 for the arrangement shown in FIG. 1 is omitted here, since no further planarization coat 17 is to be fabricated here. Therefore, the VIAs 8 for the graphene film 13 are fabricated in step S5 here.

[0177] In step S6, the dielectric coat is first fabricated on the upper side of the gate electrodes 15a, 15b and resist-planarized preferably on its upper side in order to achieve the aforementioned roughness, and then the graphene film 13 is provided thereon.

[0178] The trapezoidal shape ensures that the active element, in this case the graphene film 13, follows the gate electrodes 15a, 15b or the dielectric coat, in particular on the beveled edges. As a result, the graphene always lies on the dielectric coat on the electrodes 15a, 15b and can be electrostatically controlled particularly well. Also, a particularly homogeneous electric field can be achieved.

[0179] The steps following the provision of the (respective) graphene film 13 can correspond to those for the arrangement shown in FIG. 1 (in particular fabrication of the contact elements 18, fabrication of the passivation coat 19 and provision of openings therein).

[0180] FIG. 4 shows an embodiment of a photodetector according to the second aspect of the invention.

[0181] It also comprises a longitudinal section 12 of a waveguide 11, and an active element 13 comprising or consisting of at least one material which absorbs electromagnetic radiation of at least one wavelength and generates an electrical photosignal as a result of the absorption. Also, in the detector according to FIG. 3, the active element is—exemplarily—given by a graphene film 13.

[0182] Contrary to the examples in FIGS. 1 and 3, the waveguide 11 and its longitudinal section 12 belonging to the detector 3 are formed in one piece here. Specifically, it is a strip waveguide with a rectangular cross-section.

[0183] A further difference is given by the fact that two carrier elements 20 are arranged on opposite sides of the longitudinal section of the waveguide 11, being spaced therefrom forming two gaps 21. The carrier elements 20 are thereby arranged at a distance from the longitudinal section 12 of the waveguide 11 in the transverse direction. The two gaps 21 are free of material. Vacuum is present in them.

[0184] The carrier elements 20 can be made of the same material as the longitudinal section 12 of the waveguide 11, although this is to be understood as exemplarily.

[0185] The active element 13 overlaps, as can be seen, in the transverse direction the longitudinal section 12 of the waveguide 11 and the two gaps 21 and in sections the two carrier elements 20.

[0186] Furthermore, the graphene film 13 is planar, contrary to the examples of FIGS. 1 and 3, where it rests in a trapezoidal region.

[0187] As far as the wafer 1, the planarization coat 2 and the passivation coat 19 are concerned, the arrangement in FIG. 4 is identical to that in FIG. 2. As can be seen, it also has no further planarization coat 17. Furthermore, this detector 3 does not comprise gate electrodes.

[0188] To fabricate the arrangement of FIG. 4, steps S1 to S3 may again be identical to those described in connection with FIG. 1.

[0189] In a step S4, the waveguides 11 and carrier elements 20 are then fabricated. For this purpose, waveguide material, for example the same as in the previous examples, is deposited over the surface and then the gaps 21 are obtained by lithography and etching.

[0190] The VIAs 8 are fabricated then, extending here through the one planarization coat 2 and one of the carrier elements 20 each (step S5).

[0191] In a step S6, the active elements, for instance in the form of graphene films 13, are provided, which is expediently done by a transfer process as described in more detail above.

[0192] The remaining steps can again be the same as those that followed the provision of the active elements 13 in the previous examples (in particular, the fabrication of the contact elements 18, the fabrication of the passivation coat 19 and the provision of openings therein).

[0193] FIG. 5 shows an embodiment of an electro-optical modulator 22 according to the third aspect of the invention.

[0194] It also comprises a longitudinal section 12 of a waveguide 11, but comprising four waveguide segments 12a, 12b 12c, 12d extending in the longitudinal direction and at least substantially parallel to one another.

[0195] As it is a modulator 22, it further comprises two active elements 13a, 13b comprising at least one material or consisting of at least one material whose refractive index changes as a function of a voltage and/or the presence of charge and/or an electric field. In the example shown, the two active elements are given by two graphene films 13a, 13b.

[0196] Of the two active elements 13a, 13b, the lower one 13a is located on the upper side 10 of the planarization coat 2.

[0197] It should be noted that, alternatively to two active elements 13a, 13b being provided, only one active element and one conventional electrode, such as made of a metal, may be provided and arranged correspondingly to each other.

[0198] With respect to the four waveguide segments 12a-12d, it further applies that a lower one of the waveguide segments 12a is arranged between the two active elements 13a, 13b and a middle one of the waveguide segments 12b is arranged above the two active elements 13a, 13b, specifically on the upper active element 13b. In other words, there is a sandwich configuration (in FIG. 5 from bottom to top) of the first active element 13a, the lower waveguide segment 12a, the second active element 13b and the middle segment 12b. The upper active element 13b extends within the longitudinal section 12 of the waveguide. The waveguide segments 12a-12d may all be of the same material.

[0199] The lower and middle waveguide segments 12a, 12b serve simultaneously as passivation and etch protection. In particular, the segment 12a is part of the waveguide and also protection for the element 13a when the element 13b is etched. Then, waveguide segment 12a serves as an etch stop coat and as a passivation coat to protect the graphene 13a. In particular, segment 12b is also etch stop coat for structuring of parts 12c and 12d during fabrication of region 14.

[0200] The two remaining, upper waveguide segments 12c, 12d are arranged above the middle waveguide segment 12b, presently on its upper side. The two upper waveguide segments 12c, 12d are spaced apart from each other in the transverse direction forming a gap 14 extending therebetween. The two upper waveguide segments 12c, 12d thus lie side by side on the middle waveguide segment 12b and the gap 14 lies between them. It applies that exactly one gap 14 is provided above the two active elements 13. The gap 14 is filled with the material of the coat 19.

[0201] The extension of the lower and middle waveguide segments 12a, 12b in the transverse direction exceeds, as can be seen, the extension of the two upper segments 12c, 12d in this direction by a multiple. The cross-section of the segments 12a-12d is rectangular.

[0202] The two active elements 13a, 13b are spaced apart from each other—by the lower waveguide segment 12a—and, moreover, are offset from each other in the transverse direction in such a way that they lie one above the other in sections in an overlap region 23. A section of one active element 13 is aligned or overlapped with a section of the other active element 13. Specifically, the end regions facing each other are lying one above the other or are aligned, forming the overlap region 23. As can be seen from FIG. 5, the overlap region 23 lies below the gap 14 formed between the two segments 12c, 12d and is aligned therewith.

[0203] The extension of the overlap region 23 and the extension of the gap 14 in the transverse direction are adapted to each other. In concrete terms, the extension of the overlap region 23 in the transverse direction is approximately 1.3 times the extension of the gap 14 in this direction. For example, it can also correspond to 1.0 times or 0.8 times, i.e., have the same or a smaller extension in this direction. In particular, it applies that the smaller the overlap, the lower the capacitance and the faster the modulator.

[0204] Also, in the case of the modulator 22 with two active elements 13, it applies that the modulator, specifically its active elements 13, are connected to at least one integrated electronic component 5 from the FEOL of the wafer 1. Each active element 13 is connected to a VIA 8 by a contact element 18 associated therewith and in contact therewith, which VIA 8 extends through the planarization coat 2 (VIA 8 for the active element 13 on the left in FIG. 5) or the planarization coat 2 and the waveguide segment 12a (VIA 8 for the active element 13 on the right in FIG. 5) and, together with further VIAs 8 in the BEOL 7, ensures the connection.

[0205] An electro-optical modulator 22, as shown in FIG. 5 and also in FIGS. 6 and 7, which will be explained further on, can be used in a manner known per se, in particular for optical signal coding.

[0206] To obtain the arrangement of FIG. 5, the steps S1 to S3 can be identical.

[0207] Subsequently, in a step S4, the first, lower graphene film 13a can be provided as the lower active element. This can be done in the same way as described above for the one active element 13 of the detectors 3. Accordingly, this may comprise, for example, a full-area deposition of material and subsequent structuring.

[0208] Then the contact element 18 belonging to this active element 13 can be fabricated, again in exactly the same way as the contact elements 18 from FIGS. 1, 3 and 4.

[0209] In step S6, the lower waveguide segment 12a is then fabricated, which can preferably comprise material deposition and subsequent structuring—in analogy to the segments 12a, 12b from the previous figures. The same materials as mentioned for the previous embodiments can be used as waveguide material.

[0210] In step S7, the second, upper graphene film 13b is provided on the upper side of the segment 12a, preferably in the same way as the first, lower graphene film 13a.

[0211] In step S8, the contact element 18 is fabricated for it.

[0212] In step S9, the middle segment 12b is fabricated—preferably in the same way as the lower segment 12a—and in step S10 the two upper segments 12c, 12d are fabricated on top of the middle segment 12c. Again, a waveguide material can be deposited in the manner described above and then structured to obtain the two adjacent segments 12c, 12d enclosing the gap 14 between them. It should be noted that it is possible for the material deposition for the middle segment 12b and the upper two segments 12c, 12d to be interrupted or separate, for example when different waveguide materials are used. However, it is not excluded that the material required for the middle segment 12b and the material required for the upper segments 12c, 12d are applied in one deposition process, without interruption, and the segments 12b, 12c, 12d are obtained by subsequent structuring.

[0213] This is then preferably followed by the steps for obtaining the passivation coat 19 (S11) and the openings therein (S12), as explained above in connection with the preceding figures. The gap 14 fills with the material of the coat 19 during or due to the material deposition for the coat 19.

[0214] FIG. 6 shows an embodiment of a modulator 22 according to the fourth aspect of the invention.

[0215] It differs from that according to FIG. 5 in particular in that there is a gap 14 not above, but below the active elements 13, which are also given here—by way of example—by graphene films 13, and the longitudinal section 12 of the waveguide 11 does not comprise four, but five segments 12a, 12b, 12c, 12d, 12e.

[0216] In concrete terms, two lower ones of the waveguide segments 12a, 12b are arranged below the active elements 13 and are spaced apart from each other in the transverse direction forming a gap 14 extending therebetween, and a first middle one of the waveguide segments 12c is arranged between the two active elements 13, and a second middle waveguide segment 12d is arranged above the two active elements 13, specifically on the upper side of the upper active element 13, and an upper waveguide segment 12e is arranged above the second middle waveguide segment 12d, specifically on the upper side thereof. In this example, there is thus a sandwich-like structure comprising—from bottom to top—the two lower waveguide segments 12a, 12b, the lower active element 13a, a first middle waveguide segment 12c, the upper active element 13b, a second middle waveguide segment 12d and, on its upper side, the upper waveguide segment 12e. Here, both active elements 13 extend within the longitudinal section 12 of the waveguide 11.

[0217] Here, the two lower waveguide segments 12a, 12b and the first middle waveguide segment 12c serve also simultaneously as passivation and etch protection.

[0218] Concerning the extension of the gap 14 in the overlap region 23 in the transverse direction, the same applies as with respect to FIG. 5.

[0219] To obtain the arrangement of FIG. 6, the steps S1 to S3 can be identical again.

[0220] In a step S4, the two waveguide segments 12a, 12b are then first fabricated on the upper side 10 of the planarization coat 2, wherein waveguide material is deposited for this purpose, preferably exactly in the same way as in the preceding embodiments, whereby a continuous coat is initially obtained, and then the gap 14 is fabricated by structuring, which preferably includes lithography and etching, in particular RIE, and filled with a dielectric material, for example SiO.sub.2, and the surface is preferably planarized, for example by CMP and/or resist planarization.

[0221] Then, the VIA 8 associated with the left graphene film 13 in FIG. 5 can be fabricated (step S5), extending through the planarization coat 2 and the left one of the lower segments 12a in FIG. 5, which can be done as described above.

[0222] Next, the first, lower graphene film 13 is provided (step S6), which can also be done as in the previous examples. The lower graphene film 13 is preferably arranged in such a way that it completely overlaps the gap 14—as can be seen in FIG. 5—in the transverse direction.

[0223] Then, the associated contact element 18 can be fabricated as described above (step S6), and then the first middle waveguide segment 12c, the VIA 8 for the second, upper graphene film 13 (step S7), the second, upper graphene film 13 (S8), as the first one, the second middle segment 12d (S9) and the upper segment 12e (S10). The fabrication of the segments 12c, 12d and 12e can be done, for example, analogously to the fabrication of the segments 12a to 12d of FIG. 5, with the difference that no gap is provided in the segment 12e, which is etched only as a strip-shaped segment with a rectangular cross-section.

[0224] Finally, the steps described above for obtaining the passivation coat 19 (S11) and the openings therein (S12) can also be carried out here.

[0225] FIG. 7 shows an embodiment of a modulator 22 according to the fifth aspect of the invention.

[0226] It differs from the example in FIG. 6 only in that a second gap 14 is additionally provided above the active elements, again by way of example, formed by graphene films 13. Instead of the strip-shaped waveguide segment 12e as in FIG. 6, two adjacent segments 12e and 12f spaced apart from one another to form the second gap 14 are also provided here above the graphene films 13 on the upper side of the second middle segment 12d. It should be noted that the second, upper gap 14 also fills with the material of the coat 19 in this case during or due to the deposition of the material for the coat 19.

[0227] In this example, there is a sandwich-like structure comprising—from bottom to top—the two lower waveguide segments 12a, 12b, the lower active element 13a, a first middle waveguide segment 12c, the upper active element 13b, a second middle waveguide segment 12d and, on its upper side two adjacent upper waveguide segments 12e, 12f. Again, both active elements 13 extend within the longitudinal section 12 of the waveguide 11.

[0228] The two lower waveguide segments 12a, 12b and the first middle waveguide segment 12c also serve here simultaneously as passivation and etching protection.

[0229] As can be seen in FIG. 6, the overlap region 23 formed by the two active elements 13 due to the offset is located above one gap 14, specifically between the lower segments 12a and 12b, and below the other gap 14, in concrete terms that one between the upper segments 12e and 12f.

[0230] The lower gap 14, the overlap region 23 and the upper gap 14 are aligned.

[0231] It further applies here that the extension of the overlap region 23 and the extension of both gaps 14 are adapted to each other in the transverse direction. Specifically, the extension of the overlap region 23 in the transverse direction is approximately 1.3 times the extension of the upper gap 14 and the lower gap 14 in this direction. For example, it may correspond also to 1.0 times or 0.8 times.

[0232] To obtain the arrangement of FIG. 7, the same procedure can be followed as for that of FIG. 6, with the only difference that the upper gap 14 must also be etched. As a result, the two upper segments 12e and 12f with the gap 14 therebetween are then obtained on the upper side of the second middle waveguide segment 12d instead of the one upper segment 12e.

[0233] As noted above, the examples of semiconductor devices according to the invention each include a plurality of photodetectors 3 or modulators 22, only one of which is shown by way of example in the partial sections. In the illustrated embodiments of semiconductor devices according to the invention, all photodetectors 3 or modulators 22 can be identical in design. The conformity then enables a particularly simple, rapid fabrication. It should be emphasized, however, that it is of course also possible for a semiconductor device according to the invention to comprise different embodiments of photodetectors 3 and/or modulators 22 shown in FIGS. 1 and 3 to 6, for example both detectors 3 according to FIG. 1 and modulators according to FIG. 5. There may also be more than two different embodiments, for example one or more of each of the photodetectors 3 and/or modulators 22 shown.

[0234] It should be noted that the respective arrangements provided on the wafer 1, which comprise the coats 2, possibly 17 and 19, as well as photodetectors 3 and/or modulators 22, may also each be considered and designated as a photonic platform. Furthermore, it should be noted that, alternatively to the photonic platform being fabricated on the BEOL 7 of the wafer 1 as in the described embodiments, it is also possible in principle for it to be fabricated separately and bonded to the wafer 1.

[0235] After completion of a semiconductor device according to the present invention, a plurality of semiconductor apparatuses, each formed by a chip with integrated photonics built thereon with one or more photodetectors 3 and/or modulators 22 according to the present invention, can be obtained therefrom in a simple and fast manner, specifically by mere dicing, in other words fragmenting.

[0236] The “bare chips” with photodetectors 3 and/or modulators 22 obtained by dicing can then, as it is also known from conventional bare chips, be inserted into packages and supplied for further use.

[0237] A chip obtained by dicing the semiconductor device with the wafer 1 and the photodetectors 3 and/or modulators 22 with one or more such is an embodiment of a semiconductor apparatus according to the invention.

[0238] It should be noted that all partial sectional views show only a comparatively very small section, specifically a section showing only a small part of the wafer 1 or a chip obtained after dicing. All partial sections thus represent sections both through an embodiment of a semiconductor device according to the invention and through an embodiment of a semiconductor apparatus according to the invention. Furthermore, it should be noted that already above a single chip a plurality of photodetectors 3 and/or modulators 22 can be provided, depending on the application, for example several tens, several hundreds or even several thousands.