Plating apparatus and plating method
11781235 · 2023-10-10
Assignee
Inventors
Cpc classification
C25D17/001
CHEMISTRY; METALLURGY
C25D5/18
CHEMISTRY; METALLURGY
C25D7/123
CHEMISTRY; METALLURGY
H01L21/2885
ELECTRICITY
C25D17/002
CHEMISTRY; METALLURGY
C25D5/08
CHEMISTRY; METALLURGY
H01L21/76868
ELECTRICITY
International classification
C25D5/18
CHEMISTRY; METALLURGY
C25D17/00
CHEMISTRY; METALLURGY
Abstract
A plating apparatus and plating methods for plating metal layers on a substrate. In an embodiment, a plating method comprises: step 1: immersing a substrate into plating solution of a plating chamber assembly including at least a first anode and a second anode (3001); step 2: turning on a first plating power supply applied on the first anode, setting the first plating power supply to output a power value P.sub.11 and continue with a period T.sub.11 (3002); step 3: when the period T.sub.11 ends, adjusting the first plating power supply applied on the first anode to output a power value P.sub.12 and continue with a period T.sub.12, at the same time, turning on a second plating power supply applied on the second anode, and setting the second plating power supply to output a power value P.sub.21 and continue with a period T.sub.21 (3003); and step 4: when the period T.sub.21 ends, adjusting the second plating power supply applied on the second anode to output a power value P.sub.22 and continue with a period T.sub.22; wherein step 2 to step 4 are performed periodically.
Claims
1. A plating method for plating metal layers on a substrate, comprising: step 1: immersing a substrate into plating solution of a plating chamber assembly including at least a first anode and a second anode; step 2: turning on a first plating power supply applied on the first anode, setting the first plating power supply to output a power value P.sub.11 and continue with a period T.sub.11; step 3: when the period T.sub.11 ends, adjusting the first plating power supply applied on the first anode to output a power value P.sub.12 and continue with a period T.sub.12, at the same time, turning on a second plating power supply applied on the second anode, and setting the second plating power supply to output a power value P.sub.21 and continue with a period T.sub.21; and step 4: when the period T.sub.21 ends, adjusting the second plating power supply applied on the second anode to output a power value P.sub.22 and continue with a period T.sub.22; wherein step 2 to step 4 are performed periodically, when step 2 to step 4 are performed, different modes are applied, the different modes have different combinations of power types, power values and length of periods, the modes are selected according to phases of the plating process, and wherein during at least one mode, the power value P.sub.11 or P.sub.12 of the first plating power supply is below a plating threshold while at least one of voltage and current of the first plating power supply is positive to repair or protect a seed layer for plating.
2. The plating method according to claim 1, wherein the power value P.sub.12 is less than the power value P.sub.11, the power value P.sub.22 is less than the power value P.sub.21.
3. The plating method according to claim 1, wherein there is a time interval between adjusting the first plating power supply to output a power value P.sub.12 and setting the second plating power supply to output a power value P.sub.21.
4. The plating method according to claim 1, wherein there is a time interval between adjusting the second plating power supply to output a power value P.sub.22 and setting the first plating power supply to output a power value P.sub.11.
5. The plating method according to claim 1, wherein the first plating power supply and the second plating power supply are turned on in sequence, and the period T.sub.11 and the period T.sub.21 are adjustable.
6. The plating method according to claim 1, wherein the power value P.sub.12 and the power value P.sub.22 are zero or respectively a set value.
7. The plating method according to claim 1, wherein the period T.sub.11 and the period T.sub.21 are respectively in the range of 0.01 ms to 2000 ms.
8. The plating method according to claim 1, wherein the period T.sub.12 and the period T.sub.22 are respectively in the range of 0.01 ms to 2000 ms.
9. The plating method according to claim 1, wherein the first plating power supply and the second plating power supply are a pulse direct current or a pulse direct voltage.
10. The plating method according to claim 1, wherein during the period T.sub.11 and the period T.sub.21, the first plating power supply and the second plating power supply are a pulse direct current, and during the period T.sub.12 and the period T.sub.22, the first plating power supply and the second plating power supply are a pulse direct voltage with a set value.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DETAILED DESCRIPTION
(37)
(38) Referring to
(39) The anode chamber 210 is divided into multiple anode zones 211 and every two adjacent anode zones 211 are separated by a vertically arranged partition 212. The material of the partitions 212 is non-conductive and chemical resistant. The partitions 212 separate the electric fields and restrict the electrolyte flow fields. In an embodiment, no limitation to the present invention, the anode chamber 210 is divided into four anode zones 211. Every anode zone 211 accommodates an anode 2111. The anodes 2111 can be, for example, copper cylinders or copper particles. The four anodes 2111 can be respectively numbered a first anode, a second anode, a third anode and a fourth anode from the center to edge of the anode chamber 210. It should be recognized that according to different process requirements, the anodes 2111 can be made of different materials.
(40) As shown in
(41) A membrane frame 221 is fixed on the top of the anode chamber 210 and the bottom of the membrane frame 221 is supported by the partitions 212. The membrane frame 221 is configured to form the cathode chamber 220. The membrane 230 is attached on the bottom of the membrane frame 221 to separate the anode chamber 210 and the cathode chamber 220. A plurality of pairs of seal rings 260 are configured to completely separate the anode zones 211 so as to guarantee no any mass and energy transmission between the anode zones 211. Specifically, one pair of seal rings 260 is set between the bottom of the membrane frame 221 and the top of the anode chamber 210 and the other pairs of seal rings 260 are respectively set between the bottom of the membrane frame 221 and the top of the partitions 212 to form completely independent anode zones 211. Every independent anode zone 211 has an anolyte inlet 213 which is connected to an electrolyte flow control device for supplying plating solution to the anode zone 211. Every independent anode zone 211 has an anolyte outlet 214 for discharging aged electrolyte, decomposition products, and particles from the anode zone 211.
(42) Every independent anode zone 211 further has a vent drain outlet 215. Each vent drain outlet 215 connects to a vent drain passage 216. The vent drain passage 216 is set in the anode zone 211 and abuts the partition 212. The vent drain passage 216 has a top end 217 which is located at the highest point of the anode zone 211. As shown in
(43) With reference to
(44) The base portion 2211 of the membrane frame 221 has a plurality of pairs of branch pipes 2219 for supplying plating solution into the cathode chamber 220. Each branch pipe 2219 extends from the edge of the base portion 2211 to the center of the base portion 2211 so that the flow direction of the plating solution in each branch pipe 2219 is from the edge to center of the base portion 2211. Each branch pipe 2219 is connected to a catholyte inlet 2221. Each branch pipe 2219 has a plurality of plating solution supply holes 2222. The plurality of supply holes 2222 on each branch pipe 2219 are divided into four groups and each group of supply holes 2222 is corresponding to one cathode zone. As shown in
(45) Please refer to
(46) The membrane 230 is attached on the bottom of the base portion 2211 of the membrane frame 221 for separating the anode chamber 210 and the cathode chamber 220. Only metal ions can transmit via the membrane 230 on specific direction, and the electrolyte and additives in the electrolyte cannot transmit via the membrane 230, guaranteeing there is only metal ions exchange between the anode chamber 210 and the cathode chamber 220.
(47) The bottom of the base portion 2211 of the membrane frame 221 can be designed in various shapes. For example, the bottom of the base portion 2211 is obliquely upward, as shown in
(48) A diffusion plate 270 is set in the cathode chamber 220. Referring to
(49) A plurality of second separating walls 280 is inserted and fixed in the upper inserting slots 272 of the diffusion plate 270 to divide the cathode chamber 220 into multiple cathode zones, benefitting the substrate edge plating profile control. In an embodiment, the number of the second separating walls 280 is three to divide the cathode chamber 220 into four cathode zones. The second separating walls 280 are made of non-conducting and anti-acidic material, such as PVC, PP, etc.
(50) There are several ways to fix the second separating walls 280 on the top surface of the diffusion plate 270. Referring to
(51) The thickness of the second separating walls 280 will influence the plating profile of the areas on the substrate which are over against the second separating walls 280 and the plated film thickness of these areas will be lower than the other areas on the substrate due to the electric filed above the second separating walls 280 is weaker, causing zone to zone plating profile boundary effect. Therefore, the second separating walls 280 with a thinner thickness are helpful to minimize the boundary effect. In an embodiment, the thickness of every second separating wall 280 is about 0.5 mm. And by optimizing the top shape of the second separating walls 280 also can weaken the boundary effect. Referring to
(52) Referring to
(53) Referring to
(54) At least one substrate rinse nozzle 290 is configured to clean the plated film on the substrate after the substrate has been plated, avoiding the electrolyte etching the plated film.
(55) A chuck cleaning nozzle 300 is configured to clean the chuck assembly 100. While cleaning the chuck assembly 100, cleaning liquid is collected by the collecting groove 251 of the shroud 250 and drained through the liquid outlet 253 of the shroud 250.
(56) When the plating apparatus is used for plating metal layers on a substrate to form interconnection structures, the substrate 400 is transferred to the chuck assembly 100 which is configured to hold the substrate 400 for plating. The chuck assembly 100 is located above the plating chamber assembly 200. The substrate 400 has features of patterned structures, such as trenches, vias, etc. The chuck assembly 100 carries the substrate 400 and makes the substrate 400 submerge into the plating solution of the cathode chamber 220. The chuck assembly 100 is operable to make the substrate 400 tilt a pre-set angle relative to a horizontal plane and rotate at a pre-set speed during the process of the substrate 400 entering the plating solution of the cathode chamber 220, and at the same time, the chuck assembly 100 is operable to make the substrate 400 move downward to be submerged into the plating solution of the cathode chamber 220. In the substrate 400 submersion process, the chuck assembly 100 is operable to make the substrate 400 gradually become horizontal and finally become absolutely horizontal when the substrate 400 is fully immersed into the plating solution of the cathode chamber 220.
(57) Referring to
(58) The gap between the substrate 400 and the top end of the second separating walls 280 is critical for plating rate and plating profile control. The small gap is more beneficial to single zone plating profile control. The plating current of each zone will just act on its zone, and there is minimal current cross talking between zones. The larger gap is beneficial to achieving a smooth plating profile. Therefore, after the filling of trenches, vias, etc., patterned structures of the substrate 400 is completed, while implementing the subsequent overburden metal layer plating, preferably, the gap between the substrate 400 and the top end of the second separating walls 280 can be adjusted to a large gap. The gap normally is set in the range of 1 mm to 20 mm during the plating process.
(59) Referring to
(60) Referring to
(61) As shown in
(62) Please refer to
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(64) Please refer to
(65) Although not illustrated in the drawings, a controller is provided and configured to control the plating power supplies to operate in different modes. The controller may be connected to the respective plating power supplies and the controller may be configured to control the plating power supplies to operate as follows:
(66) Combined with
(67) The mode M.sub.0A1: within every time period T.sub.n1, the output of the plating power supply is current. The power value P.sub.n1 is a low value which is lower than 1 ASD. The “.sub.n” represents the serial number of the anode. The pulse length, that is the time period T.sub.n1, is short, which is lower than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is zero. The pulse length, that is the time period T.sub.n2, is short, which is lower than 10 ms. By taking the mode M.sub.0A1, a seed layer on the substrate can be protected, avoiding the seed layer surface being etched or uncontrollable galvanic reactions by plating solution.
(68) The mode M.sub.0A2: within every time period T.sub.n1, the output of the plating power supply is voltage. The power value P.sub.n1 is a low value which is lower than 1 ASD. The pulse length, that is the time period T.sub.n1, is short, which is lower than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is zero. The pulse length, that is the time period T.sub.n2, is short, which is lower than 10 ms. By taking the mode M.sub.0A2, a seed layer on the substrate can be protected, avoiding the seed layer surface being etched or uncontrollable galvanic reactions by plating solution.
(69) The mode M.sub.0B1: within every time period T.sub.n1, the output of the plating power supply is current. The power value P.sub.n1 is a low value which is lower than 1 ASD. The pulse length, that is the time period T.sub.n1, is long, which is greater than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is zero. The pulse length, that is the time period T.sub.n2, is long, which is greater than 10 ms. While plating narrow lines, the defect of PVD (physical vapor deposition) process may cause the seed layer deposition on side walls of the narrow lines is not consecutive and uniform, which will induce the plating failure on the side walls of the narrow lines and form some voids when the subsequent plating process is implemented. For solving the problem, it is preferable to repair the seed layers on patterned structures of the substrate before plating metal layers on the seed layers. By taking the mode M.sub.0B1, the seed layers on the patterned structures of the substrate can be repaired. Because the output of the plating power supply is a low current, within the time periods T.sub.n1, additives in the plating solution are not activated so that the plating is a conformal plating process, which causes the bottoms and side walls of the patterned structures to be uniformly plated a thin metal layer, which will optimize the seed layer uniformity on the patterned structures.
(70) The mode M.sub.0B2: within every time period T.sub.n1, the output of the plating power supply is voltage. The power value P.sub.n1 is a low value which is lower than 1 ASD. The pulse length, that is the time period T.sub.n1, is long, which is greater than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is zero. The pulse length, that is the time period T.sub.n2, is long, which is greater than 10 ms. Similarly with the mode M.sub.0B1, by taking the mode M.sub.0B2, the seed layer on the patterned structures of the substrate can be repaired.
(71) The mode M.sub.1: within every time period T.sub.n1, the output of the plating power supply is current. The power value P.sub.n1 is a high value which is greater than 1 ASD. The pulse length, that is the time period T.sub.n1, is long, which is greater than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is current. The power value P.sub.n2 is zero. The pulse length, that is the time period T.sub.n2, is long, which is greater than 10 ms. By taking the mode M.sub.1, cooperating with additives, within time periods T.sub.n1, a bottom-up plating is formed to fill the patterned structures. In the patterned structures, the vertical direction plating rate is accelerated, and the horizontal direction plating rate is suppressed.
(72) The mode M.sub.2: within every time period T.sub.n1, the output of the plating power supply is current. The power value P.sub.n1 is a high value which is greater than 1 ASD. The pulse length, that is the time period T.sub.n1, is long, which is greater than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is a low current that is lower than 1 ASD. The pulse length, that is the time period T.sub.n2, is long, which is greater than 10 ms. By taking the mode M.sub.2, within time periods T.sub.n1, a bottom-up plating is formed to fill the patterned structures, and within time periods T.sub.n2, the seed layer on the patterned structures can be repaired.
(73) The mode M.sub.3: within every time period T.sub.n1, the output of the plating power supply is current. The power value P.sub.n1 is a high value which is greater than 1 ASD. The pulse length, that is the time period T.sub.n1, is long, which is greater than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is a low voltage with no current. The current value is 0 ASD. The pulse length, that is the time period T.sub.n2, is long, which is greater than 10 ms. By taking the mode M.sub.3, within time periods T.sub.n1, a bottom-up plating is formed to fill the patterned structures, and within time periods T.sub.n2, the seed layer on the patterned structures is protected, avoiding the seed layer surface being etched or uncontrollable galvanic reactions by plating solution.
(74) The mode M.sub.4: within every time period T.sub.n1, the output of the plating power supply is current. The power value P.sub.n1 is a high value which is greater than 1 ASD. The pulse length, that is the time period T.sub.n1, is long, which is greater than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is a low voltage with a low current that is lower than 1 ASD. The pulse length, that is the time period T.sub.n2, is long, which is greater than 10 ms. By taking the mode M.sub.4, within time periods T.sub.n1, a bottom-up plating is formed to fill the patterned structures, and within time periods T.sub.n2, the seed layer on the patterned structures can be repaired.
(75) The mode M.sub.5: within every time period T.sub.n1, the output of the plating power supply is voltage. The power value P.sub.n1 is a high value which is greater than 1 ASD. The pulse length, that is the time period T.sub.n1, is long, which is greater than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is a low voltage with no current. The current value is 0 ASD. The pulse length, that is the time period T.sub.n2, is long, which is greater than 10 ms. By taking the mode M.sub.5, within time periods T.sub.n1, a bottom-up plating is formed to fill the patterned structures, and within time periods T.sub.n2, the seed layer on the patterned structures is protected, avoiding the seed layer surface being etched or uncontrollable galvanic reactions by plating solution.
(76) The mode M.sub.6: within every time period T.sub.n1, the output of the plating power supply is voltage. The power value P.sub.n1 is a high value which is greater than 1 ASD. The pulse length, that is the time period T.sub.n1, is long, which is greater than 10 ms. Within every time period T.sub.n2, the output of the plating power supply is a low voltage with a low current that is lower than 1 ASD. The pulse length, that is the time period T.sub.n2, is long, which is greater than 10 ms. By taking the mode M.sub.6, within time periods T.sub.n1, a bottom-up plating is formed to fill the patterned structures, and within time periods T.sub.n2, the seed layer on the patterned structures can be repaired.
(77) In the modes M.sub.0A1 to M.sub.6, both the current and the voltage are converted to current density to be described. Normally all anode zones will be set the same current density, but according to the flow and electric field distribution, the current correction of each anode zone is necessary for actual application.
(78) According to the modes M.sub.0A1 to M.sub.6, the present invention provides plating methods for plating metal layers on a substrate to form, for example, interconnection structures.
(79) Referring to
(80) Step 3001: immersing the substrate into plating solution of a plating chamber assembly including at least a first anode and a second anode;
(81) Step 3002: turning on a first plating power supply applied on the first anode, setting the first plating power supply to output a power value P.sub.11 and continue with a period T.sub.11;
(82) Step 3003: when the period T.sub.11 ends, adjusting the first plating power supply applied on the first anode to output a power value P.sub.12 and continue with a period T.sub.12, at the same time, turning on a second plating power supply applied on the second anode, and setting the second plating power supply to output a power value P.sub.21 and continue with a period T.sub.21; and
(83) Step 3004: when the period T.sub.21 ends, adjusting the second plating power supply applied on the second anode to output a power value P.sub.22 and continue with a period T.sub.22, at the same time, adjusting the first plating power supply applied on the first anode to output a power value P.sub.11 and continue with a period T.sub.11;
(84) wherein step 3003 to step 3004 are performed periodically. That the first plating power supply is controlled to continuously output a power value P.sub.11 with a period T.sub.11 and a power value P.sub.12 with a period T.sub.12 can be defined one cycle.
(85) In an embodiment, the power value P.sub.12 is less than the power value P.sub.11, the power value P.sub.22 is less than the power value P.sub.21.
(86) In an embodiment, there is a time interval between adjusting the first plating power supply to output a power value P.sub.12 and setting the second plating power supply to output a power value P.sub.21.
(87) In an embodiment, there is a time interval between adjusting the second plating power supply to output a power value P.sub.22 and setting the first plating power supply to output a power value P.sub.11.
(88) In an embodiment, when the step 3002 to the step 3005 are performed, different modes are applied, the different modes have different combinations of power types, power values and length of periods, the modes are selected according to the phases of the plating process.
(89) In an embodiment, the first plating power supply and the second plating power supply are turned on in sequence, and the period T.sub.11 and the period T.sub.21 are adjustable, therefore, the plating film thickness corresponding to anode zones accommodating the first anode and the second anode is controlled.
(90) The power value P.sub.12 and the power value P.sub.22 are zero or respectively a set value.
(91) The period T.sub.11 and the period T.sub.21 are respectively in the range of 0.01 ms to 2000 ms.
(92) The period T.sub.12 and the period T.sub.22 are respectively in the range of 0.01 ms to 2000 ms.
(93) In an embodiment, the first plating power supply and the second plating power supply are a pulse direct current.
(94) In another embodiment, the first plating power supply and the second plating power supply are a pulse direct voltage.
(95) In yet another embodiment, during the period T.sub.11 and the period T.sub.21, the first plating power supply and the second plating power supply are a pulse direct current, and during the period T.sub.12 and the period T.sub.22, the first plating power supply and the second plating power supply are a pulse direct voltage with a set value.
(96) Referring to
(97) Step 3101: making the substrate enter into plating solution of a plating chamber assembly including at least a first anode and a second anode and at the same time, turning on a first plating power supply applied on the first anode, setting the first plating power supply to output a power value P.sub.11 and continue with a period T.sub.11;
(98) Step 3102: when the period T.sub.11 ends, adjusting the first plating power supply applied on the first anode to output a power value P.sub.12 and continue with a period T.sub.12, at the same time, turning on a second plating power supply applied on the second anode, setting the second plating power supply to output a power value P.sub.21 and continue with a period T.sub.21;
(99) Step 3103: when the period T.sub.21 ends, adjusting the second plating power supply applied on the second anode to output a power value P.sub.22 and continue with a period T.sub.22, at the same time, adjusting the first plating power supply applied on the first anode to output a power value P.sub.11 and continue with a period T.sub.11;
(100) Step 3104: the first plating power supply and the second plating power supply are adjusted periodically. That the first plating power supply is controlled to continuously output a power value P.sub.11 with a period T.sub.11 and a power value P.sub.12 with a period T.sub.12 can be defined one cycle.
(101) In an embodiment, the power value P.sub.12 is less than the power value P.sub.11, the power value P.sub.22 is less than the power value P.sub.21.
(102) In an embodiment, there is a time interval between adjusting the first plating power supply to output a power value P.sub.12 and setting the second plating power supply to output a power value P.sub.21.
(103) In an embodiment, there is a time interval between adjusting the second plating power supply to output a power value P.sub.22 and setting the first plating power supply to output a power value P.sub.11.
(104) In an embodiment, when adjusting the first plating power supply and the second plating power supply, different modes are applied, the different modes have different combinations of power types, power values and length of periods, the modes are selected according to the phases of the plating process.
(105) In an embodiment, the first plating power supply and the second plating power supply are turned on in sequence, and the period T.sub.11 and the period T.sub.21 are adjustable, therefore, the plating film thickness corresponding to anode zones accommodating the first anode and the second anode is controlled.
(106) The power value P.sub.12 and the power value P.sub.22 are zero or respectively a set value.
(107) The period T.sub.11 and the period T.sub.21 are respectively in the range of 0.01 ms to 2000 ms.
(108) The period T.sub.12 and the period T.sub.22 are respectively in the range of 0.01 ms to 2000 ms.
(109) In an embodiment, the first plating power supply and the second plating power supply are a pulse direct current.
(110) In an embodiment, the first plating power supply and the second plating power supply are a pulse direct voltage.
(111) In an embodiment, during the period T.sub.11 and the period T.sub.21, the first plating power supply and the second plating power supply are a pulse direct current, and during the period T.sub.12 and the period T.sub.22, the first plating power supply and the second plating power supply are a pulse direct voltage with a set value.
(112) A plating procedure according to an exemplary embodiment of the present invention will be illustrated. In this exemplary embodiment, the anode chamber of the plating chamber assembly has four anode zones and four anodes. The four anodes can be respectively numbered a first anode, a second anode, a third anode and a fourth anode from the center to edge of the anode chamber. Correspondingly, four plating power supplies are respectively applied on the four anodes. The four plating power supplies can be respectively numbered a first plating power supply applied on the first anode, a second plating power supply applied on the second anode, a third plating power supply applied on the third anode and a fourth plating power supply applied on the fourth anode.
(113) Plating Procedure
(114) Step 3201: a substrate entering plating solution of the plating chamber assembly. In this entry step, traditional methods can be used.
(115) Step 3202: plating of patterned structures of the substrate, which further comprises:
(116) step 32021, turning on the first plating power supply applied on the first anode and setting the first plating power supply to output a power value P.sub.11 and continue with a period T.sub.11;
(117) step 32022, when the period T.sub.11 ends, adjusting the first plating power supply applied on the first anode to output a power value P.sub.12 and continue with a period T.sub.12, at the same time, turning on the second plating power supply applied on the second anode, and setting the second plating power supply to output a power value P.sub.21 and continue with a period T.sub.21;
(118) step 32023, when the period T.sub.21 ends, adjusting the second plating power supply applied on the second anode to output a power value P.sub.22 and continue with a period T.sub.22, at the same time, turning on the third plating power supply applied on the third anode, and setting the third plating power supply to output a power value P.sub.31 and continue with a period T.sub.31;
(119) step 32024, when the period T.sub.31 ends, adjusting the third plating power supply applied on the third anode to output a power value P.sub.32 and continue with a period T.sub.32, at the same time, turning on the fourth plating power supply applied on the fourth anode, and setting the fourth plating power supply to output a power value P.sub.41 and continue with a period T.sub.41; and
(120) step 32025, when the period T.sub.41 ends, adjusting the fourth plating power supply applied on the fourth anode to output a power value P.sub.42 and continue with a period T.sub.42, at the same time, adjusting the first plating power supply applied on the first anode to output a power value P.sub.11 and continue with a period T.sub.11;
(121) wherein step 32022 to step 32025 are performed periodically.
(122) According to another embodiment of the present invention, the step 3202 further comprises:
(123) step 32021, turning on the fourth plating power supply applied on the fourth anode, setting the fourth plating power supply to output a power value P.sub.41 and continue with a period T.sub.41;
(124) step 32022, when the period T.sub.41 ends, adjusting the fourth plating power supply applied on the fourth anode to output a power value P.sub.42 and continue with a period T.sub.42, at the same time, turning on the third plating power supply applied on the third anode, and setting the third plating power supply to output a power value P.sub.31 and continue with a period T.sub.31;
(125) step 32023, when the period T.sub.31 ends, adjusting the third plating power supply applied on the third anode to output a power value P.sub.32 and continue with a period T.sub.32, at the same time, turning on the second plating power supply applied on the second anode, and setting the second plating power supply to output a power value P.sub.21 and continue with a period T.sub.21;
(126) step 32024, when the period T.sub.21 ends, adjusting the second plating power supply applied on the second anode to output a power value P.sub.22 and continue with a period T.sub.22, at the same time, turning on the first plating power supply applied on the first anode, and setting the first plating power supply to output a power value P.sub.11 and continue with a period T.sub.11; and
(127) step 32025, when the period T.sub.11 ends, adjusting the first plating power supply applied on the first anode to output a power value P.sub.12 and continue with a period T.sub.12, at the same time, adjusting the fourth plating power supply to output a power value P.sub.41 and continue with a period T.sub.41;
(128) wherein step 32022 to step 32025 are performed periodically.
(129) When step 32021 to step 32025 are performed, different modes are applied, the different modes have different combinations of power types, power values and length of periods, the modes are selected according to the phases of the plating process.
(130) The four plating power supplies applied on the four anodes are turned on in sequence.
(131) The power value P.sub.12, the power value P.sub.22, the power value P.sub.32, and the power value P.sub.42 are zero or respectively a set value. The power value P.sub.12 is less than the power value P.sub.11. The power value P.sub.22 is less than the power value P.sub.21. The power value P.sub.32 is less than the power value P.sub.31. The power value P.sub.42 is less than the power value P.sub.41.
(132) The period T.sub.11, the period T.sub.21, the period T.sub.31 and the period T.sub.41 are respectively in the range of 0.01 ms to 2000 ms.
(133) The period T.sub.12, the period T.sub.22, the period T.sub.32 and the period T.sub.42 are respectively in the range of 0.01 ms to 2000 ms.
(134) In an embodiment, the four plating power supplies are a pulse direct current, as shown in
(135) In another embodiment, the four plating power supplies are a pulse direct voltage, as shown in
(136) In another embodiment, as shown in
(137) Step 3203: plating overburden metal layer on the substrate. In this step, a direct current or direct voltage is applied to complete the overburden metal layer plating.
(138) Step 3204: carrying out a first drying to the substrate.
(139) Step 3205: carrying out a pre-cleaning to the substrate.
(140) Step 3206: carrying out a second drying to the substrate.
(141) Plating Procedure
(142) Step 3501: making a substrate enter plating solution of the plating chamber assembly and at the same time, turning on the first plating power supply applied on the first anode, setting the first plating power supply to output a power value P.sub.11 and continue with a period T.sub.11;
(143) Step 3502: when the period T.sub.11 ends, adjusting the first plating power supply applied on the first anode to output a power value P.sub.12 and continue with a period T.sub.12, at the same time, turning on the second plating power supply applied on the second anode, and setting the second plating power supply to output a power value P.sub.21 and continue with a period T.sub.21;
(144) Step 3503: when the period T.sub.21 ends, adjusting the second plating power supply applied on the second anode to output a power value P.sub.22 and continue with a period T.sub.22, at the same time, turning on the third plating power supply applied on the third anode, and setting the third plating power supply to output a power value P.sub.31 and continue with a period T.sub.31;
(145) Step 3504: when the period T.sub.31 ends, adjusting the third plating power supply applied on the third anode to output a power value P.sub.32 and continue with a period T.sub.32, at the same time, turning on the fourth plating power supply applied on the fourth anode, and setting the fourth plating power supply to output a power value P.sub.41 and continue with a period T.sub.41;
(146) Step 3505: when the period T.sub.41 ends, adjusting the fourth plating power supply applied on the fourth anode to output a power value P.sub.42 and continue with a period T.sub.42, and adjusting the first plating power supply applied on the first anode to output a power value P.sub.11 and continue with a period T.sub.11;
(147) Step 3506: repeating the step 3502 to the step 3505 to complete the patterned structures plating;
(148) Step 3507: plating overburden metal layer on the substrate;
(149) Step 3508: carrying out a first drying to the substrate;
(150) Step 3509: carrying out a pre-cleaning to the substrate; and
(151) Step 3510: carrying out a second drying to the substrate.
(152) As described above, the present invention adopts pulse modes for plating metal layers on the substrate, which can protect the seed layer on the substrate. Besides, in the plating process, the amount of electricity per unit time is small, avoiding producing gassing at the anodes. Therefore, the quality of the plating is improved.
(153) The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. Such modifications and variations that may be apparent to those skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims.