POWER AMPLIFIER

Abstract

An ultra-wideband power amplifier includes a preamplifier circuit and a post amplifier circuit. The preamplifier circuit includes a first DC blocking capacitor C.sub.1, a first decoupling capacitor C.sub.2, a second decoupling capacitor C.sub.3, a stabilizing resistor R.sub.in, a first AC blocking resistor RG.sub.1, a first input inductor L.sub.1, a second input inductor L.sub.2, an output inductor L.sub.3, a first input microstrip line MLIN.sub.1, a second input microstrip line MLIN.sub.2, an output microstrip line MLIN.sub.3, and a first transistor Q.sub.1. A first end of the first DC blocking capacitor C.sub.1 acts as an input terminal of the preamplifier circuit, and a second end of the first DC blocking capacitor C.sub.1 is connected to the stabilizing resistor R.sub.in, the first input inductor L.sub.1, the first input microstrip line MLIN.sub.1, and a gate electrode of the first transistor Q.sub.1 sequentially. One end of the first decoupling capacitor C.sub.2 is grounded.

Claims

1. A power amplifier, comprising: 1) a preamplifier circuit, the preamplifier circuit comprising a first DC blocking capacitor C.sub.1, a first decoupling capacitor C.sub.2, a second decoupling capacitor C.sub.3, a stabilizing resistor Rill, a first AC blocking resistor RG.sub.1, a first input inductor L.sub.1, a second input inductor L.sub.2, an output inductor L.sub.3, a first input microstrip line MLIN.sub.1, a second input microstrip line MLIN.sub.2, an output microstrip line MLIN.sub.3, and a first transistor Q.sub.1; and 2) a post amplifier circuit, the post amplifier circuit comprising a first gate microstrip line MLIN.sub.4, a second gate microstrip line MLIN.sub.5, a third gate microstrip line MLIN.sub.6, a fourth gate microstrip line MLIN.sub.7, a drain inductor L.sub.4, a first drain microstrip line MLIN.sub.8, a second drain microstrip line MLIN.sub.9, a second AC blocking resistor RG.sub.2, a third decoupling capacitor C.sub.5, a fourth decoupling capacitor C.sub.6, a third DC blocking capacitor C.sub.7, an AC blocking inductor L.sub.5, a second transistor Q.sub.2, a third transistor Q.sub.3, and a fourth transistor Q.sub.4; wherein: a first end of the first DC blocking capacitor C.sub.1 acts as an input terminal of the preamplifier circuit, and a second end of the first DC blocking capacitor C.sub.1 is connected to the stabilizing resistor R.sub.in, the first input inductor L.sub.1, the first input microstrip line MLIN.sub.1, and a gate electrode of the first transistor Q.sub.1 sequentially; a first end of the first decoupling capacitor C.sub.2 is grounded, and a second end of the first decoupling capacitor C.sub.2 is connected to the first AC blocking resistor RG.sub.1, the second input inductor L.sub.2, the second input microstrip line MLIN.sub.2, and the gate electrode of the first transistor Q.sub.1 sequentially; a junction of the first decoupling capacitor C.sub.2 and the first AC blocking resistor RG.sub.1 is connected to a gate supply voltage V.sub.gs1; a first end of the second decoupling capacitor C.sub.3 is grounded, and a second end of the second decoupling capacitor C.sub.3 is connected to the output inductor L.sub.3, the output microstrip line MLIN.sub.3, and a drain electrode of the first transistor Q.sub.1; a junction of the second decoupling capacitor C.sub.3 and the output inductor L.sub.3 is connected to a drain supply voltage V.sub.ds1; and a junction of the output inductor L.sub.3 and the output microstrip line MLIN.sub.3 acts as an output terminal of the preamplifier circuit; a second DC blocking capacitor C.sub.4 is disposed between the preamplifier circuit and the post amplifier circuit; a first end of the first gate microstrip line MLIN.sub.4 acts as an input terminal of the post amplifier circuit, and a second end of the first gate microstrip line MLIN.sub.4 is connected to the second gate microstrip line MLIN.sub.5, the third gate microstrip line MLIN.sub.6, the fourth gate microstrip line MLIN.sub.7, the second AC blocking resistor RG.sub.2, and the third decoupling capacitor C.sub.5 sequentially; and one end of the third decoupling capacitor C.sub.5 is grounded; a junction of the second AC blocking resistor RG.sub.2 and the third decoupling capacitor C.sub.5 is connected to a gate supply voltage V.sub.gs2; a junction of first gate microstrip line MLIN.sub.4 and the second gate microstrip line MLIN.sub.5 is connected to a gate electrode of the second transistor Q.sub.2; a junction of the second gate microstrip line MLIN.sub.5 and the third gate microstrip line MLIN.sub.6 is connected to a gate electrode of the third transistor Q.sub.3; a junction of the third gate microstrip line MLIN.sub.6 and the fourth gate microstrip line MLIN.sub.7 is connected to a gate electrode of the fourth transistor Q.sub.4; the drain inductor L.sub.4 is disposed between drain electrodes of the second transistor Q.sub.2 and the third transistor Q.sub.3; the first drain microstrip line MLIN.sub.8 is disposed between drain electrodes of the third transistor Q.sub.3 and the fourth transistor Q.sub.4; and a junction of the first drain microstrip line MLIN.sub.8 and the fourth transistor Q.sub.4 is connected to a first end of the second drain microstrip line MLIN.sub.9; a second end of the second drain microstrip line MLIN.sub.9 is connected to first ends of the fourth decoupling capacitor C.sub.6, the AC blocking inductor L.sub.5, and the third DC blocking capacitor C.sub.7; a second end of the fourth decoupling capacitor C.sub.6 is grounded; a second end of the AC blocking inductor L.sub.5 is connected to a voltage source V.sub.ds2; and a second end of the third DC blocking capacitor C.sub.7 acts as an output terminal of the post amplifier circuit.

Description

DETAILED DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a schematic diagram of an ultra-wideband power amplifier according to Example 1 of the disclosure;

[0011] FIG. 2 is a schematic diagram of an ultra-wideband power amplifier according to Comparison example 1 of the disclosure;

[0012] FIG. 3 is a graph of a simulation result obtained in accordance with Example 1 of the disclosure;

[0013] FIG. 4 is a comparison graph of simulation results obtained in accordance with Example 1 and Comparison example 1 of the disclosure; and

[0014] FIG. 5 is a comparison graph of simulation results obtained in accordance with Example 1 and Comparison example 1 of the disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] To further illustrate, embodiments detailing an ultra-wideband power amplifier are described below. It should be noted that the following embodiments are intended to describe and not to limit the disclosure.

Example 1

[0016] An ultra-wideband power amplifier comprises a power supply, a preamplifier circuit, a second DC blocking capacitor C.sub.4, and a post amplifier circuit; the preamplifier circuit comprises a first DC blocking capacitor C.sub.1, a first decoupling capacitor C.sub.2, a second decoupling capacitor C.sub.3, a stabilizing resistor R.sub.in, a first AC blocking resistor RG.sub.1, a first input inductor L.sub.1, a second input inductor L.sub.2, an output inductor L.sub.3, a first input microstrip line MLIN.sub.1, a second input microstrip line MLIN.sub.2, an output microstrip line MLIN.sub.3, and a first transistor Q.sub.1; the post amplifier circuit comprises a first gate microstrip line MLIN.sub.4 and a multi-stage traveling-wave amplifier circuit; the multi-stage traveling-wave amplifier circuit comprises a second gate microstrip line MLIN.sub.5, a third gate microstrip line MLIN.sub.6, a fourth gate microstrip line MLIN.sub.7, a drain inductor L.sub.4, a first drain microstrip line MLIN.sub.8, a second drain microstrip line MLIN.sub.9, a second AC blocking resistor RG.sub.2, a third decoupling capacitor C.sub.5, a fourth decoupling capacitor C.sub.6, a third DC blocking capacitor C.sub.7, an AC blocking inductor L.sub.5, a second transistor Q.sub.2, a third transistor Q.sub.3, and a fourth transistor Q.sub.4; the first DC blocking capacitor C.sub.1, the first decoupling capacitor C.sub.2, the stabilizing resistor R.sub.in, the second AC blocking resistor RG.sub.2, the first input microstrip line MLIN.sub.1, and the second input microstrip line MLIN.sub.2 are used to match a first impedance at an input terminal of the first transistor Q.sub.1; the output microstrip line MLIN.sub.3 is used to match a second impedance at an output terminal of the first transistor Q.sub.1; and the preamplifier circuit is connected to the second DC blocking capacitor C.sub.4, the first gate microstrip line MLIN.sub.4, and the multi-stage traveling-wave amplifier circuit sequentially.

[0017] Simulation results of the ultra-wideband power amplifier show that a working frequency is 0.03-2.5 GHz, an output frequency is greater than 41 dBm, a power-added efficiency (PAE) is greater than 47%, a gain is greater than 15 dB; and the ultra-wideband power amplifier further comprises a signal source Z.sub.s and a load Z.sub.L.

[0018] FIG. 1 is a schematic diagram of the ultra-band power amplifier of the disclosure. A radio frequency (RF) signal is transmitted to the preamplifier circuit for amplification; and the size of the first transistor Q.sub.1 is small for better impedance matching and ultra-wideband amplification with flat gain.

[0019] The RF signal is transmitted from the preamplifier circuit to the post amplifier circuit via the second DC blocking capacitor C.sub.4; the post amplifier circuit comprises a distributed amplifier topology; the first gate microstrip line MLIN.sub.4 acts as an input terminal of the post amplifier circuit and adjusts an output impedance of the first transistor Q.sub.1; the sizes of the second transistor Q.sub.2, the third transistor Q.sub.3, and the fourth transistor Q.sub.4 are different for achieving an optimal power and an improved efficiency of impedance matching; and the drain inductor L.sub.4 has a high inductance for better impendence matching.

[0020] Inductance and resistance are used to match an impedance at an input terminal of the preamplifier circuit so that an excellent standing wave is formed; and the preamplifier circuit is used in conjunction with the post amplifier to form a desired reverse isolation.

[0021] The first DC blocking capacitor C.sub.1, second DC blocking capacitor C.sub.4, and the third DC blocking capacitor C.sub.7 are high-capacity off-chip capacitors for blocking a low-frequency DC signal; and the output inductor L.sub.3 and AC blocking inductor L.sub.5 are high-capacity off-chip inductors for preventing a loss of a low-frequency signal.

[0022] Multiple nonlinear components in the transistor are superpositioned, resulting in a sweet spot in a 3.sup.rd order intermodulation distortion at a critical input power. Specifically, as the input power varies, the level of the 3.sup.rd order intermodulation distortion is lowered to a minimum value, at which the corresponding input power is defined as the sweet spot. The preamplifier circuit is configured to send the output signal to the post amplifier circuit. The signal source is configured to generate a fundamental signal and transmit it to the preamplifier circuit. The preamplifier circuit outputs a plurality of signals that comprises a plurality of frequency components caused by a nonlinear effect; fundamental frequency components are nonlinear and generates 5.sup.th and higher order frequency components; 3.sup.rd order frequency components in the preamplifier circuit are produced by nonlinearity of the fundamental frequency components and by the 5.sup.th and higher order frequency components; the plurality of frequency components, which have different amplitudes and phases, are transmitted to the post amplifier circuit; a plurality of more complex frequency components are produced due to a non-linear superposition of the plurality of frequency components; 3.sup.rd order frequency components in the post amplifier circuit comprises the 3.sup.rd order frequency components which are transmitted from the preamplifier circuit, amplified from the 3.sup.rd order frequency components in the preamplifier circuit, and generated by 1.sup.st, 2.sup.nd, 5.sup.rd and higher other order frequency components.

[0023] A gate supply voltage across the preamplifier circuit is adjusted to produce a plurality of non-linear frequency components having different amplitudes and phases; the plurality of non-linear frequency components is transmitted to the post amplifier circuit and results in different non-linear effects; the non-linear effects include the fact that the value for the sweet spot varies with the gate supply voltage across the preamplifier circuit; that is, the gate supply voltage is adjusted to produce different sweet spots; at each of the different sweet spots, the level of the 3.sup.rd order intermodulation distortion is lowered to a minimum value, and a 3.sup.rd order output intercept point (OIP3) has a maximum value; so the gate supply voltage is adjusted to make the plurality of sweet spot has a value close to a saturation output power, thus achieving a high-linearity and high-efficiency amplifier at a low back-off output power level. The power back-off method is also suitable for harmonic tuning.

[0024] The preamplifier circuit comprises a stabilizing resistor R.sub.in, a first AC blocking resistor RG.sub.1, a first input inductor L.sub.1, a second input inductor L.sub.2, a first input microstrip line MLIN.sub.1, a second input microstrip line MLIN.sub.2, an output microstrip line MLIN.sub.3, a first DC blocking capacitor C.sub.1, a first decoupling capacitor C.sub.2, a second decoupling capacitor C.sub.3, a gate supply voltage V.sub.gs1, a drain supply voltage V.sub.ds1, and a first transistor Q.sub.1; a first end of the first DC blocking capacitor C.sub.1 is connected to the stabilizing resistor R.sub.in; and a second end of the first DC blocking capacitor C.sub.1 is connected to the signal source Z.sub.s.

[0025] The power amplifier further comprises a second DC blocking capacitor C.sub.4 disposed between the preamplifier circuit and the post amplifier circuit.

[0026] The post amplifier circuit comprises a first gate microstrip line MLIN.sub.4, a second gate microstrip line MLIN.sub.5, a third gate microstrip line MLIN.sub.6, a fourth gate microstrip line MLIN.sub.7, a drain inductor L.sub.4, a first drain microstrip line MLIN.sub.8, a second drain microstrip line MLIN.sub.9, a second AC blocking resistor RG.sub.2, a third decoupling capacitor C.sub.5, and a fourth decoupling capacitor C.sub.6, a third DC blocking capacitor C.sub.7, an AC blocking inductor L.sub.5, a second transistor Q.sub.2, a third transistor Q.sub.3, a fourth transistor Q.sub.4, a gate supply voltage V.sub.gs2, and a drain supply voltage Vasa, a first end of the third DC blocking capacitor C.sub.7 is connected to the second drain microstrip line MLIN.sub.9; and a second end of the third DC blocking capacitor C.sub.7 is connected to the load Z.sub.L.

[0027] The transistor comprises a source electrode that is grounded.

Comparison Example 1

[0028] A second example of the ultra-wideband power amplifier is illustrated in FIG. 2. It is similar to the example described in Example 1, except for the following difference: the ultra-wideband power amplifier comprises a distributed amplifier topology instead of the preamplifier circuit. Simulation results of the ultra-wideband power amplifier in FIG. 2 show that a working frequency is 0.03-2.5 GHz, an output power is greater than 40 dBm, a gain is greater than 10 dB, and a power-added efficiency is greater than 48%.

[0029] FIG. 1 is a graph illustrating a simulation result of a position of a sweet spot in a 3.sup.rd order intermodulation distortion at 12.00 MHz (with a frequency interval of 1 MHz) according to Example 3 of the disclosure.

[0030] FIGS. 4-5 are comparison graphs of simulation results obtained in accordance with Example 1 and Comparison example 1.

[0031] FIG. 4 is a comparison graph of IM3 and corresponding PAE at a minimum value of IM3 at 1200 MHz (with a frequency interval of 1 MHz) according to Example 1 and Comparison example 1. In Example 1, the output power back-off 1.4 dB, resulting in IM3 of −45 dBc and the corresponding PAE of 41%; and in Comparison example 1, the output power back-off 5 dB, resulting in IM3 of −35 dBc and the corresponding PAE of 38.3%.

[0032] FIG. 5 is a comparison graph of IM3 and corresponding PAE at a maximum value of IM3 at 2500 MHz (with a frequency interval of 1 MHz) according to Example 1 and Comparison example 1. In Example 1, the output power back-off 1.6 dB, resulting in IM3 of −46 dBc and the corresponding PAE of 38.5%; in Comparison example 1, the output power back-off 5 dB, resulting in IM3 of −41 dBc and the corresponding PAE of 31.6%.

[0033] In the disclosure, the pre-amplifier circuit comprises a single transistor matched amplifier and is matched with the multi-stage traveling wave amplifier of the post-stage; and the transistors are properly biased to improve linearity and efficiency of an ultra-wideband power amplifier.

[0034] It will be obvious to those skilled in the art that changes and modifications may be made, and therefore, the aim in the appended claims is to cover all such changes and modifications.