Flexible modeling method for timing constraint of register

Abstract

Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state. A flexible timing constraint model in the present invention has advantages of low simulation overheads and high prediction precision, and is of great significance for static timing analysis timing signoff of a digital integrated circuit.

Claims

1. A flexible modeling method for a timing constraint of a register, including the following steps: step 1. performing simulation in a case of each combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk respectively to obtain a timing constraint range for establishing a model, where S.sub.Q represents an output terminal state of a register; T.sub.di represents p types of input terminal transition time T.sub.d of the register, i is an integer, and 1≤i≤p; T.sub.ckj represents q types of clock terminal transition time T.sub.ck of the register, j is an integer, and 1≤j≤q; and C.sub.Lk represents m types of output load capacitance C.sub.L of the register, k is an integer, and 1≤k≤m; step 2. under the obtained timing constraint range under each combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.LK, setting that T.sub.step is a sampling interval of both setup slack and hold slack, extracting N combination pairs of setup slack T.sub.su and hold slack T.sub.hd with the set T.sub.step as intervals for both setup slack and hold slack, performing simulation by using a transistor-level simulation tool to respectively obtain N clock terminal-to-output terminal delays of the register, and subsequently combining all simulation data of under all combinations of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.LK together to obtain N.sub.s groups of model training sample data, where each group of training sample data includes parameters including the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, the output terminal state, and the clock terminal-to-output terminal delay of the register, where N is an integer which denotes the number of combinations for simulation with different T.sub.su and T.sub.hd under the same set of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.LK, N.sub.s is an integer which denotes the number of samples for model training with different S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk as well as T.sub.su and T.sub.hd and T.sub.su and T.sub.hd denote the time of setup slack and hold slack respectively; step 3. using the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and the output terminal state of the register as model features, using the corresponding clock terminal-to-output terminal delays of the register obtained in step 2 as model labels, performing training by using a neural network, and establishing a mutually independent timing model of the register; and step 4. obtaining timing constraints by using a static timing analysis tool, the timing constraints including the output terminal state, the input terminal transition time, the clock terminal transition time, and the output load capacitance of the register, and performing inference by using the mutually independent timing model of the register obtained in step 3 to obtain a clock terminal-to-output terminal delay of the register when the setup slack is T.sub.su.sup.t and a clock terminal-to-output terminal delay of the register when the hold slack is T.sub.hd.sup.t, wherein step 1 includes the following steps: step 1.1. under each combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.LK, performing simulation by using the transistor-level simulation tool first to obtain clock terminal-to-output terminal delays T.sub.cq when the setup slack has a sufficiently large value T.sub.su(max) and the hold slack has a sufficiently large value T.sub.hd(max), where the sufficiently large value of the setup slack refers to that in this case, if T.sub.su continues to increase, T.sub.cq no longer continues to decrease, and the sufficiently large value of the hold slack refers to that in this case, if T.sub.hd continues to increase, T.sub.cq no longer continues to decrease, that is, when the setup slack increases from T.sub.su(max) to δ.sub.su×T.sub.su(max) and the hold slack increases from T.sub.hd(max) to δ.sub.hd×T.sub.hd(max), T.sub.cq remains unchanged, where δ.sub.su is a setup slack verification coefficient, 1≤δ.sub.su≤1.1, δ.sub.hd is a hold slack verification coefficient, 1≤δ.sub.hd≤1.1, and in this case, the register operates in a stable region, and it is denoted in this case that T.sub.cq is T.sub.cq.sup.min in the hold slack is T.sub.hd.sup.A, and the setup slack is T.sub.su.sup.A; step 1.2. gradually reducing the setup slack with T.sub.hd.sup.A as a fixed hold slack, where setup slack obtained when transistor-level simulation fails is minimum setup slack in the timing constraint range, and it is denoted in this case that the setup slack is T.sub.su.sup.C; step 1.3. searching for the value of the setup slack by using a binary method with T.sub.hd.sup.A as a fixed hold slack, where an interval in which the search is started is [T.sub.su.sup.C, T.sub.su.sup.A], performing simulation on the setup slack by using the transistor-level simulation tool to obtain T.sub.cq, and setting a target value of T.sub.cq to B.sub.cq×T.sub.cq.sup.min, where B.sub.cq is a first target coefficient of the setup slack, 1≤B.sub.cq≤1.1, and the value of the setup slack found through binary search is denoted as T.sub.su.sup.B; step 1.4. gradually reducing the hold slack with T.sub.su.sup.A as a fixed setup slack, where hold slack obtained when transistor-level simulation fails is minimum hold slack in the timing constraint range, and it is recorded in this case that the hold slack is T.sub.hd.sup.G; step 1.5. searching for the value of the hold slack by using a binary method with T.sub.su.sup.A as a fixed setup slack, where an interval in which the search is started is [T.sub.hd.sup.G, T.sub.hd.sup.A], performing simulation on the hold slack by using the transistor-level simulation tool to obtain the clock terminal-to-output terminal delay T.sub.cq, and setting a target value of the clock terminal-to-output terminal delay T.sub.cq to F.sub.cq×T.sub.cq.sup.min where F.sub.cq is a first target coefficient of the hold slack, 1≤F.sub.cq≤1.1, and the value of the hold slack found through binary search is denoted as T.sub.hd.sup.F; and step 1.6. searching for the value of the hold slack by using a binary method with T.sub.su.sup.B as a fixed setup slack, where an interval in which the search is started is [T.sub.hd.sup.F, T.sub.hd.sup.A], performing simulation on the hold slack by using the transistor-level simulation tool to obtain the clock terminal-to-output terminal delay T.sub.cq, and setting the target value of the clock terminal-to-output terminal delay T.sub.cq to D.sub.cq×T.sub.cq.sup.min, where D.sub.cq is a second target coefficient of the hold slack, B.sub.cq≤D.sub.cq≤1.1, and the value of the hold slack found through binary search is denoted as T.sub.hd.sup.D; step 1.7. searching for the value of the setup slack by using a binary method with T.sub.hd.sup.F as a fixed hold slack, where an interval in which the search is started is [T.sub.su.sup.B, T.sub.su.sup.A], performing simulation on the setup slack by using the transistor-level simulation tool to obtain the clock terminal-to-output terminal delay T.sub.cq, and setting the target value of the clock terminal-to-output terminal delay T.sub.cq to H.sub.cq×T.sub.cq.sup.min, where H.sub.cq is a second target coefficient of the setup slack, F.sub.cq≤H.sub.cq≤1.1, and the value of the setup slack found through binary search is denoted as T.sub.su.sup.H; step 1.8. forming a constraint condition by using the following formulas for a simulation range of the pair of the hold slack T.sub.hd and the setup slack T.sub.su under the combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.LK; $\begin{array}{cc}\{\begin{array}{c}{T}_{\mathrm{hd}}^G\le T_{\mathrm{hd}}\le T_{\mathrm{hd}}^D\\ T_{\mathrm{su}}^C\le T_{\mathrm{su}}\le T_{\mathrm{su}}^H\\ \frac{T_{\mathrm{su}}-T_{\mathrm{su}}^H}{T_{\mathrm{su}}^B-T_{\mathrm{su}}^H}\le \frac{T_{\mathrm{hd}}-T_{\mathrm{hd}}^F}{T_{\mathrm{hd}}^D-T_{\mathrm{hd}}^F}\\ \frac{T_{\mathrm{hd}}-T_{\mathrm{hd}}^G}{T_{\mathrm{hd}}^F-T_{\mathrm{hd}}^G}\le \frac{T_{\mathrm{su}}-T_{\mathrm{su}}^B}{T_{\mathrm{su}}^C-T_{\mathrm{su}}^B}\end{array},& \left(1\right)\end{array}$ the foregoing formula is the timing constraint range of the model established in a case of the combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk.

2. The flexible modeling method for a timing constraint of a register according to claim 1, where step 2 specifically includes the following steps: step 2.1. setting that T.sub.step is the sampling interval of both setup slack and hold slack, extracting the N combination pairs of setup slack and hold slack with the set T.sub.step as intervals for both setup slack and hold slack, and performing simulation by using a transistor-level simulation tool to respectively obtain the N clock terminal-to-output terminal delays of the register, where in this case, the obtained each group of simulation data includes a total of seven parameters including the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, the output terminal state, and the clock terminal-to-output terminal delay; step 2.2. giving that a threshold of the clock terminal-to-output terminal delay is M.sub.th×T.sub.cq.sup.min, where M.sub.th is a delay threshold coefficient, and 1≤M.sub.th≤10; and eliminating these corresponding groups of simulation data when transistor-level simulation fails and the clock terminal-to-output terminal delay is greater than M.sub.th×T.sub.cq.sup.min, storing data obtained after elimination as training and test samples of a neural network model, and repeating the foregoing process under each different combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.LK; and step 2.3. subsequently combining all simulation data under all combinations of the output terminal state S.sub.Q, the input terminal transition time T.sub.di, the clock terminal transition time T.sub.ckj, and the output load capacitance C.sub.LK of the register together to obtain the N.sub.s groups of model training sample data, where each group of training sample data includes the total of seven parameters including the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, the output terminal state, and the clock terminal-to-output terminal delay of the register.

3. The flexible modeling method for a timing constraint of a register according to claim 1, where steps of the binary search in step 1.3 are as follows: the simulation is performed at a middle position (T.sub.su.sup.C+T.sub.su.sup.A)/2 of the search interval to obtain the clock terminal-to-output terminal delay, and if in this case, the clock terminal-to-output terminal delay is B.sub.cq×T.sub.cq.sup.min, the search process ends; if in this case, the clock terminal-to-output terminal delay is greater than B.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.su.sup.C+T.sub.su.sup.A)/2, T.sub.su.sup.A]; if in this case, the clock terminal-to-output terminal delay is less than B.sub.cq×T.sub.cq.sup.min, the search interval is updated to [T.sub.su.sup.C,(T.sub.su.sup.C+T.sub.su.sup.A)/2]; then the foregoing process is repeated with the new search interval, the search interval is halved each time, and the search ends when a clock terminal-to-output terminal delay obtained through simulation by using the transistor-level simulation tool at a middle position in a search process is B.sub.cq×T.sub.cq.sup.min; and when a middle position of the last binary search interval, that is, the clock terminal-to-output terminal delay, is B.sub.cq×T.sub.cq.sup.min, the corresponding setup slack is denoted as T.sub.su.sup.B.

4. The flexible modeling method for a timing constraint of a register according to claim 1, where steps of the binary search in step 1.5 are as follows: the simulation is performed at a middle position (T.sub.hd.sup.G+T.sub.hd.sup.A)/2 of the search interval to obtain the clock terminal-to-output terminal delay, and if in this case, the clock terminal-to-output terminal delay is F.sub.cq×T.sub.cq.sup.min, the search process ends; if in this case, the clock terminal-to-output terminal delay is greater than F.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.hd.sup.G+T.sub.hd.sup.A)/2, T.sub.hd.sup.A]; if in this case, the clock terminal-to-output terminal delay is less than F.sub.cq×T.sub.cq.sup.min, the search interval is updated to [T.sub.hd.sup.G(T.sub.hd.sup.G+T.sub.hd.sup.A)/2]; then the foregoing process is repeated with the new search interval, the search interval is halved each time, and the search ends when a clock terminal-to-output terminal delay obtained through simulation by using the transistor-level simulation tool at a middle position in a search process is F.sub.cq×T.sub.cq.sup.min; and when a middle position of the last binary search interval, that is, the clock terminal-to-output terminal delay, is F.sub.cq×T.sub.cq.sup.min, the corresponding hold slack is denoted as T.sub.hd.sup.F.

5. The flexible modeling method for a timing constraint of a register according to claim 1, where steps of the binary search in step 1.6 are as follows: the simulation is performed at a middle position (T.sub.hd.sup.F+T.sub.hd.sup.A)/2 of the search interval to obtain the clock terminal-to-output terminal delay, and if in this case, the clock terminal-to-output terminal delay is D.sub.cq×T.sub.cq.sup.min, the search process ends; if in this case, the clock terminal-to-output terminal delay is greater than D.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.hd.sup.F+T.sub.hd.sup.A)/2, T.sub.hd.sup.A]; if in this case, the clock terminal-to-output terminal delay is less than D.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.hd.sup.F, T.sub.hd.sup.F+T.sub.hd.sup.A)/2]; then the foregoing process is repeated with the new search interval, and each time the search interval is halved, and the search ends when a clock terminal-to-output terminal delay obtained through simulation by using the transistor-level simulation tool at a middle position in a search process is D.sub.cq×T.sub.cq.sup.min; and when a middle position of the last binary search interval, that is, the clock terminal-to-output terminal delay, is D.sub.cq×T.sub.cq.sup.min, the corresponding hold slack is denoted as T.sub.hd.sup.D.

6. The flexible modeling method for a timing constraint of a register according to claim 1, where steps of the binary search in step 1.7 are as follows: the simulation is performed at a middle position (T.sub.su.sup.B+T.sub.su.sup.A)/2, of the search interval to obtain the clock terminal-to-output terminal delay, and if in this case, the clock terminal-to-output terminal delay is H.sub.cq×T.sub.cq.sup.min, the search process ends; if in this case, the clock terminal-to-output terminal delay is greater than H.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.su.sup.B+T.sub.su.sup.A)/2, T.sub.su.sup.A]; if in this case, the clock terminal-to-output terminal delay is less than H.sub.cq×T.sub.cq.sup.min, the search interval is updated to [T.sub.su.sup.B, (T.sub.su.sup.B+T.sub.su.sup.A)/2]; then the foregoing process is repeated with the new search interval, and each time the search interval is halved, and the search ends when a clock terminal-to-output terminal delay obtained through simulation by using the transistor-level simulation tool at a middle position in a search process is H.sub.cq×T.sub.cq.sup.min; and when a middle position of the last binary search interval, that is, the clock terminal-to-output terminal delay, is H.sub.cq×T.sub.cq.sup.min, the corresponding setup slack is denoted as T.sub.su.sup.H.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram of a mutually independent relationship between setup slack, hold slack, and a clock terminal-to-output terminal delay of a register in the prior art:

(2) FIG. 2 is a schematic diagram of a simulation range required for a register flexible timing constraint model according to the present invention; and

(3) FIG. 3 is a schematic structural diagram of a neural network model for obtaining a register clock terminal-to-output terminal delay T.sub.cq through inference according to the present invention.

DETAILED DESCRIPTION

(4) For better understanding of the objective, structure, and function of the present invention, a flexible modeling method for a timing constraint of a register of the present invention is further described below in detail with reference to the accompanying drawings.

(5) A flexible modeling method for a timing constraint of a register of the present invention includes the following steps:

(6) Step 1. Perform simulation in a case of each combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk respectively to obtain a timing constraint range for establishing a model, the timing constraint range being a polygon DHIJKE shown in FIG. 2, where S.sub.Q represents an output terminal state of a register; T.sub.di represents p types of input terminal transition time T.sub.d of the register, i is an integer, and 1≤i≤p; T.sub.ckj represents q types of clock terminal transition time T.sub.ck of the register, j is an integer, and 1≤j≤q; and C.sub.Lk represents m types of output load capacitance C.sub.L of the register, k is an integer, and 1≤k≤m.

(7) In a conventional timing constraint model of a register, it is assumed that a register operates in a region (that is, a stable region) with a constant register delay, that is, a clock terminal-to-output terminal delay T.sub.cq. An assumed operating point of the register is obtained when the setup slack or the hold slack is sufficiently large. In this case, a corresponding clock terminal-to-output terminal delay is minimum T.sub.cq of the register when the setup slack and the hold slack are changed, and is denoted as T.sub.cq.sup.min. In addition, when the hold slack is set to a sufficiently large value, the setup slack is gradually reduced. Generally, the setup slack when T.sub.cq just reaches 110%×T.sub.cq.sup.min is set as the setup time, corresponding to setup slack at a point L in FIG. 2. Similarly, when the setup slack is set to a sufficiently large value, the hold slack is gradually reduced. Generally, the hold slack when T.sub.cq just reaches 110%×T.sub.cq.sup.min is set as the hold time, corresponding to hold slack at a point O in FIG. 2.

(8) Step 1 specifically includes the following steps:

(9) Step 1.1. Under each combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk, perform simulation by using the transistor-level simulation tool first to obtain clock terminal-to-output terminal delays T.sub.cq when the setup slack has a sufficiently large value T.sub.su(max) and the hold slack has a sufficiently large value T.sub.hd(max), where the sufficiently large value of the setup slack refers to that in this case, if T.sub.su continues to increase, T.sub.cq no longer continues to decrease, and the sufficiently large value of the hold slack refers to that in this case, if T.sub.hd continues to increase, T.sub.cq no longer continues to decrease, specifically, when the setup slack increases from T.sub.su(max) to δ.sub.su×T.sub.su(max) and the hold slack increases from T.sub.hd(max) to δ.sub.hd×T.sub.hd(max), T.sub.cq remains unchanged, where δ.sub.su is a setup slack verification coefficient, 1≤δ.sub.su≤1.1, δ.sub.hd is a hold slack verification coefficient, 1≤δ.sub.hd≤1.1, and in this case, the register operates in a stable region, and it is denoted in this case that T.sub.cq is T.sub.cq.sup.min, the hold slack is T.sub.hd.sup.A, and the setup slack is T.sub.su.sup.A, corresponding to a point A shown in FIG. 2.

(10) Step 1.2. Gradually reduce the setup slack with T.sub.hd.sup.A as a fixed hold slack, where setup slack obtained when transistor-level simulation fails is minimum setup slack in the timing constraint range, and it is denoted in this case that the setup slack is T.sub.su.sup.C, corresponding to a point C shown in FIG. 2.

(11) Step 1.3. Search for the value of the setup slack by using a binary method with T.sub.hd.sup.A as a fixed hold slack, where an interval in which the search is started is [T.sub.su.sup.C, T.sub.su.sup.A], performing simulation on the specific setup slack by using the transistor-level simulation tool to obtain T.sub.cq, and setting a target value of T.sub.cq to B.sub.cq×T.sub.cq.sup.min, where B.sub.cq is a first target coefficient of the setup slack, 1≤B.sub.cq≤1.1, and the value of the setup slack found through binary search is denoted as T.sub.su.sup.B, corresponding to a point B shown in FIG. 2. Specific steps of the binary search are as follows: an interval in which the search is started is [T.sub.su.sup.C, T.sub.su.sup.A], simulation is performed at a middle position (T.sub.su.sup.C+T.sub.su.sup.A)/2 of the search interval to obtain the clock terminal-to-output terminal delay, and if in this case, the clock terminal-to-output terminal delay is B.sub.cq×T.sub.cq.sup.min, the search process ends; if in this case, the clock terminal-to-output terminal delay is greater than B.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.su.sup.C+T.sub.su.sup.A)/2, T.sub.su.sup.A]; if in this case, the clock terminal-to-output terminal delay is less than B.sub.cq×T.sub.cq.sup.min, the search interval is updated to [T.sub.su.sup.C, (T.sub.su.sup.C+T.sub.su.sup.A)/2]; then the foregoing process is repeated with the new search interval, the search interval is halved each time, and the search ends when a clock terminal-to-output terminal delay obtained through simulation by using the transistor-level simulation tool at a middle position in a search process is B.sub.cq×T.sub.cq.sup.min; and when a middle position of the last binary search interval, that is, the clock terminal-to-output terminal delay, is B.sub.cq×T.sub.cq.sup.min, the corresponding setup slack is denoted as T.sub.su.sup.B, corresponding to the point B shown in FIG. 2.

(12) Step 1.4. Gradually reduce the hold slack with T.sub.su.sup.A as a fixed setup slack, where hold slack obtained when transistor-level simulation fails is minimum hold slack in the timing constraint range, and it is recorded in this case that the hold slack is T.sub.hd.sup.G, corresponding to a point G shown in FIG. 2.

(13) Step 1.5. Search for the value of the hold slack by using a binary method with T.sub.su.sup.A as a fixed setup slack, where an interval in which the search is started is [T.sub.hd.sup.G, T.sub.hd.sup.A], perform simulation on the specific hold slack by using the transistor-level simulation tool to obtain the clock terminal-to-output terminal delay T.sub.cq, and set a target value of the clock terminal-to-output terminal delay T.sub.cq to F.sub.cq×T.sub.cq.sup.min, where F.sub.cq is a first target coefficient of the hold slack, 1≤F.sub.cq≤1.1, and the value of the hold slack found through binary search is denoted as T.sub.hd.sup.F, corresponding to a point F shown in FIG. 2. Specific steps of the binary search are as follows: an interval in which the search is started is [T.sub.hd.sup.G, T.sub.hd.sup.A], simulation is performed at a middle position (T.sub.hd.sup.G+T.sub.hd.sup.A)/2 of the search interval to obtain the clock terminal-to-output terminal delay, and if in this case, the clock terminal-to-output terminal delay is F.sub.cq×T.sub.cq.sup.min, the search process ends; if in this case, the clock terminal-to-output terminal delay is greater than F.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.hd.sup.G+T.sub.hd.sup.A)/2, T.sub.hd.sup.A]; if in this case, the clock terminal-to-output terminal delay is less than F.sub.cq×T.sub.cq.sup.min, the search interval is updated to [T.sub.hd.sup.G, (T.sub.hd.sup.G+T.sub.hd.sup.A)/2]; then the foregoing process is repeated with the new search interval, the search interval is halved each time, and the search ends when a clock terminal-to-output terminal delay obtained through simulation by using the transistor-level simulation tool at a middle position in a search process is F.sub.cq×T.sub.cq.sup.min; and when a middle position of the last binary search interval, that is, the clock terminal-to-output terminal delay, is F.sub.cq×T.sub.cq.sup.min, the corresponding hold slack is denoted as T.sub.hd.sup.F, corresponding to the point F shown in FIG. 2.

(14) Step 1.6. Search for the value of the hold slack by using a binary method with T.sub.su.sup.B as a fixed setup slack, where an interval in which the search is started is [T.sub.hd.sup.F, T.sub.hd.sup.A], perform simulation on the specific hold slack by using the transistor-level simulation tool to obtain the clock terminal-to-output terminal delay T.sub.cq, and set the target value of the clock terminal-to-output terminal delay T.sub.cq to D.sub.cq×T.sub.cq.sup.min, where D.sub.cq is a second target coefficient of the hold slack, B.sub.cq≤D.sub.cq≤1.1, and the value of the hold slack found through binary search is denoted as T.sub.hd.sup.D, corresponding to a point D shown in FIG. 2. Specific steps of the binary search are as follows: an interval in which the search is started is [T.sub.hd.sup.F, T.sub.hd.sup.A], simulation is performed at a middle position (T.sub.hd.sup.F+T.sub.hd.sup.A)/2 of the search interval to obtain the clock terminal-to-output terminal delay, and if in this case, the clock terminal-to-output terminal delay is D.sub.cq×T.sub.cq.sup.min, the search process ends; if in this case, the clock terminal-to-output terminal delay is greater than D.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.hd.sup.F+T.sub.hd.sup.A)/2, T.sub.hd.sup.A]; if in this case, the clock terminal-to-output terminal delay is less than D.sub.cq×T.sub.cq.sup.min, the search interval is updated to [T.sub.dd.sup.F, (T.sub.hd.sup.F+T.sub.hd.sup.A)/2]; then the foregoing process is repeated with the new search interval, and each time the search interval is halved, and the search ends when a clock terminal-to-output terminal delay obtained through simulation by using the transistor-level simulation tool at a middle position in a search process is D.sub.cq×T.sub.cq.sup.min; and when a middle position of the last binary search interval, that is, the clock terminal-to-output terminal delay, is D.sub.cq×T.sub.cq.sup.min, the corresponding hold slack is denoted as T.sub.hd.sup.D, corresponding to the point D shown in FIG. 2.

(15) Step 1.7. Search for the value of the setup slack by using a binary method with T.sub.hd.sup.F as a fixed hold slack, where an interval in which the search is started is [T.sub.su.sup.B, T.sub.su.sup.A], performing simulation on the specific setup slack by using the transistor-level simulation tool to obtain the clock terminal-to-output terminal delay T.sub.cq, and setting the target value of the clock terminal-to-output terminal delay T.sub.cq to H.sub.cq×T.sub.cq.sup.min, where H.sub.cq, is a second target coefficient of the setup slack, F.sub.cq≤H.sub.cq≤1.1, and the value of the setup slack found through binary search is denoted as T.sub.su.sup.H, corresponding to a point H shown in FIG. 2. Specific steps of the binary search are as follows: an interval in which the search is started is [T.sub.su.sup.B, T.sub.su.sup.A], simulation is performed at a middle position (T.sub.su.sup.B+T.sub.su.sup.A)/2 of the search interval to obtain the clock terminal-to-output terminal delay, and if in this case, the clock terminal-to-output terminal delay is H.sub.cq×T.sub.cq.sup.min, the search process ends; if in this case, the clock terminal-to-output terminal delay is greater than H.sub.cq×T.sub.cq.sup.min, the search interval is updated to [(T.sub.su.sup.B+T.sub.su.sup.A)/2, T.sub.su.sup.A]; if in this case, the clock terminal-to-output terminal delay is less than H.sub.cg×T.sub.cq.sup.min, the search interval is updated to [T.sub.su.sup.B, (T.sub.su.sup.B+T.sub.su.sup.A)/2]; then the foregoing process is repeated with the new search interval, and each time the search interval is halved, and the search ends when a clock terminal-to-output terminal delay obtained through simulation by using the transistor-level simulation tool at a middle position in a search process is H.sub.cq×T.sub.cq.sup.min; and when a middle position of the last binary search interval, that is, the clock terminal-to-output terminal delay, is H.sub.cq×T.sub.cq.sup.min, the corresponding setup slack is denoted as T.sub.su.sup.H, corresponding to the point H shown in FIG. 2.

(16) Step 1.8. Form a constraint condition by using the following formulas for a simulation range of the pair of the hold slack T.sub.hd and the setup slack T.sub.su under the combination of S.sub.Q, T.sub.di, T.sub.cjk, and C.sub.Lk:

(17) $\begin{array}{cc}\{\begin{array}{c}{T}_{\mathrm{hd}}^G\le T_{\mathrm{hd}}\le T_{\mathrm{hd}}^D\\ T_{\mathrm{su}}^C\le T_{\mathrm{su}}\le T_{\mathrm{su}}^H\\ \frac{T_{\mathrm{su}}-T_{\mathrm{su}}^H}{T_{\mathrm{su}}^B-T_{\mathrm{su}}^H}\le \frac{T_{\mathrm{hd}}-T_{\mathrm{hd}}^F}{T_{\mathrm{hd}}^D-T_{\mathrm{hd}}^F}\\ \frac{T_{\mathrm{hd}}-T_{\mathrm{hd}}^G}{T_{\mathrm{hd}}^F-T_{\mathrm{hd}}^G}\le \frac{T_{\mathrm{su}}-T_{\mathrm{su}}^B}{T_{\mathrm{su}}^C-T_{\mathrm{su}}^B}\end{array},& \left(1\right)\end{array}$

(18) the foregoing formula is the timing constraint range of the model established in a case of the combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk, that is, a region of the polygon DHIJKE shown in FIG. 2.

(19) Step 2. Under the obtained timing constraint range under each combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk, set that T.sub.step is a sampling interval of both setup slack and hold slack, extract N combination pairs of setup slack and hold slack with the set T.sub.step as intervals for both setup slack and hold slack, where as shown in FIG. 2, the combination pairs of setup slack and hold slack are combinations of setup slack and hold slack corresponding to N intersections of transverse dotted lines and vertical dotted lines in the polygon DHIJKE shown in FIG. 2, perform simulation by using a transistor-level simulation tool to respectively obtain N clock terminal-to-output terminal delays of the register, and subsequently combining all simulation data under all combinations of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk together to obtain N.sub.s groups of model training sample data, where each group of training sample data includes parameters including the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, the output terminal state, and the clock terminal-to-output terminal delay of the register.

(20) Step 2 specifically includes the following steps:

(21) Step 2.1. Set that T.sub.step is the sampling interval of both setup slack and hold slack, as shown in FIG. 2, extract the N combination pairs of setup slack and hold slack with the set T.sub.step as intervals for both setup slack and hold slack, and perform simulation by using a transistor-level simulation tool to respectively obtain the N clock terminal-to-output terminal delays of the register, where in this case, the obtained each group of simulation data includes a total of seven parameters including the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, the output terminal state, and the clock terminal-to-output terminal delay.

(22) Step 2.2. Give that a threshold of the clock terminal-to-output terminal delay is M.sub.th×T.sub.cq.sup.min, where M.sub.th is a delay threshold coefficient, and 1≤M.sub.th≤10; and eliminate these corresponding groups of simulation data when transistor-level simulation fails and the clock terminal-to-output terminal delay is greater than M.sub.th×T.sub.cq.sup.min, store data obtained after elimination as training and test samples of a neural network model, and repeat the foregoing process under each different combination of S.sub.Q, T.sub.di, T.sub.ckj, and C.sub.Lk.

(23) Step 2.3. Subsequently combine all simulation data under all combinations of the output terminal state S.sub.Q, the input terminal transition time T.sub.di, the clock terminal transition time T.sub.ckj, and the output load capacitance C.sub.Lk of the register together to obtain the N.sub.s groups of model training sample data, where each group of training sample data includes the total of seven parameters including the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, the output terminal state, and the clock terminal-to-output terminal delay of the register.

(24) Step 3. Use the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and the output terminal state of the register as model features, use the corresponding clock terminal-to-output terminal delays of the register obtained in step 2 as model labels, perform training by using a neural network, and establish a mutually independent timing model of the register. The structure of the neural network model is shown in FIG. 3. Parameters of an input layer of a neural network includes the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and the output terminal state of the register. The neural network in FIG. 3 includes two hidden layers (in fact, a quantity of hidden layers and a quantity of neurons in each hidden layer may be adjusted according to a specific case). An output layer is the register clock terminal-to-output terminal delay.

(25) Step 4. Obtain timing constraints by using a static timing analysis tool, the timing constraints including the output terminal state, the input terminal transition time, the clock terminal transition time, and the output load capacitance of the register, and perform inference by using the mutually independent timing model of the register obtained in step 3 to obtain a clock terminal-to-output terminal delay of the register when the setup slack is T.sub.su.sup.t and a clock terminal-to-output terminal delay of the register when the hold slack is T.sub.hd.sup.t. As shown in FIG. 3, the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and the output terminal state of the register are used as inputs of the neural network model, and the clock terminal-to-output terminal delay is calculated and outputted by using the neural network.

(26) It may be understood that the present invention is described by using a number of embodiments. It is known to those skilled in the art that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific cases and materials without departing from the spirit and scope of the present invention. Accordingly, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application fall within the scope protected by the present invention.