DIGITAL DELTA SIGMA MODULATOR WITH INHERENT SPUR IMMUNITY AFTER NONLINEAR DISTORTION

Abstract

A digital delta-sigma modulator (DDSM) is disclosed with an input signal x[n], an output signal y[n], a quantization error signal e[n] and a dither signal d[n], having an equation described in the z-domain by

Y(z)=STF(z)X(z)+DTF(z)D(z)−NTF(z)E(z)

wherein Y(z), X(z), D(z) and E(z) are z-transforms of the output signal, the input signal, the dither signal, and the quantization error signal, and wherein STF(z), DTF(z) and NTF(z) correspond to a transfer function of the input signal, a transfer function of the dither signal, and a transfer function of the quantization error signal, and wherein the transfer function of the quantization error signal is of the form:

[00001]$\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

where A, Q and K are constants, coefficients c.sub.i are real valued and c.sub.K≠0 and wherein at least one of the zeroes z.sub.j of

[00002]$\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

satisfies z.sub.j≠+1 for j=1, 2, . . . , K

Claims

1. A digital delta-sigma modulator (DDSM) with an input signal x[n], an output signal y[n], a quantization error signal e [n] and a dither signal d[n], having an equation described in the z-domain by
Y(z)=STF(z)X(z)+DTF(z)D(z)−NTF(z)E(z) wherein Y(z), X(z), D(z) and E(z) are z-transforms of the output signal, the input signal, the dither signal, and the quantization error signal, and wherein STF(z), DTF(z) and NTF(z) correspond to a transfer function of the input signal, a transfer function of the dither signal, and a transfer function of the quantization error signal, and wherein the transfer function of the quantization error signal is of the form: $\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right),$ where A, Q and K are constants, coefficients c.sub.i are real valued and c.sub.K≠0 and wherein at least one of the zeroes z.sub.j of $\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$ satisfies z.sub.j≠+1 for j=1, 2, . . . , K.

2. The digital delta-sigma modulator of claim 1, wherein the coefficients c.sub.i are equal to −1,0 or 1.

3. The digital delta-sigma modulator of claim 1, wherein R coefficients c.sub.i are equal to −1, (R−1) coefficients c.sub.i are equal to +1 and the other (K−2R+1) coefficients c.sub.i are equal to zero, with $R\le \frac{K+1}{2}.$

4. The digital delta-sigma modulator of claim 1 wherein the coefficients c.sub.i are valued such that the noise transfer function can be represented in the form: $\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1-z^{-1}\right)\left(1+\underset{i=1}{\overset{K-1}{.Math.}}{d}_i{z}^{-i}\right)$ and wherein $\underset{i=1}{\overset{K}{.Math.}}.Math.c_i.Math.\le -1+2\underset{i=1}{\overset{K-1}{.Math.}}.Math.d_i.Math.$

5. The digital delta-sigma modulator of claim 1 wherein the z-domain equation is implemented with a multi-bit single-quantizer DDSM architecture.

6. The digital delta-sigma modulator of claim 1, wherein the z-domain equation is implemented with a multistage noise shaping cascaded DDSM architecture comprising an error cancellation network and L≥2 error feedback modulator (EFM) stages, wherein an error output e.sub.j of stage j is applied as an input to stage (j+1) and wherein outputs y.sub.j of the L stages are combined in the error cancellation network to provide the output y.

7. The digital delta-sigma modulator of claim 6, wherein the L Error Feedback Modulator (EFM) stages comprise a first portion and a second portion, wherein the first portion comprises (L−1) error feedback modulator stages and the second portion comprises the Lth error feedback modulator stage, wherein the first portion and the error cancellation network implement the noise transfer function
NTF.sub.A(z)=A.sub.Az.sup.−Q.sup.A(1−z.sup.−1).sup.s wherein A.sub.A, Q.sub.A are constants and S is equal to Σ.sub.i=1.sup.L-1 s.sub.i, where s.sub.i is the order of the EFM.sub.i wherein the noise transfer function NTF.sub.i(z)=A.sub.iz.sup.−Q.sup.i(1−z.sup.−1).sup.s.sup.i where A.sub.i and Q.sub.i are constants with i=1, 2, . . . (L−1), and wherein the second portion implements the noise transfer function $NT{F}_B\left(z\right)=A_B{z^{-Q_B}\left(1-z^{-1}\right)}^{-S}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$ wherein A.sub.B, Q.sub.B are constants.

8. The digital delta-sigma modulator of claim 6, wherein the L Error Feedback Modulator (EFM) stages comprise a first portion and a second portion, wherein the first portion comprises (L−1) error feedback modulator stages and the second portion comprises the Lth error feedback modulator stage, wherein the first portion and the error cancellation network implement the noise transfer function $NT{F}_A\left(z\right)=\frac{{\left(1-z^{-1}\right)}^S}{M}$ wherein S is equal to Σ.sub.i=1.sup.L-1 s.sub.i, where s.sub.i is the order of the EFM.sub.i wherein the noise transfer function NTF.sub.i(z)=M.sup.−1(1−z.sup.−1).sup.s.sup.i with i=1, 2, . . . (L−1), and wherein the second portion implements the noise transfer function $NT{F}_B\left(z\right)=\frac{{\left(1-z^{-1}\right)}^{-S}}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

9. The digital delta-sigma modulator of claim 6, wherein L=2.

10. The digital delta-sigma modulator of claim 1, wherein the z-domain equation is implemented with an error cancellation network and a nested cascaded structure comprising a plurality of error feedback modulator (EFM) stages connected in a plurality of levels.

11. The digital delta-sigma modulator of claim 10, wherein the nested cascaded structure comprises T levels of L error feedback modulator (EFM) stages comprising a first portion and a second portion, wherein the first portion comprises (L−1) error feedback modulator stages of each level and the second portion comprises the Lth error feedback modulator stage of each level, wherein the first portion and the error cancellation network implement the noise transfer function
NTF.sub.A(z)=A.sub.Az.sup.−Q.sup.A(1−z.sup.−1).sup.s where A.sub.A, Q.sub.A are constants and S is equal to E.sub.j=1.sup.L-1 s.sub.j, where s.sub.j is the order of the EFM.sub.i,j wherein the noise transfer function NTF.sub.i,j(z)=A.sub.i,jz.sup.−Q.sup.i,j(1−z.sup.−1).sup.s.sup.j where A.sub.i,j and Q.sub.i,j are constants with i=1, 2, . . . T and j=1, 2, . . . (L−1), and wherein the second portion implements the noise transfer function $NT{F}_B\left(z\right)=A_B{z^{-Q_B}\left(1-z^{-1}\right)}^{-S}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$ wherein A.sub.B, Q.sub.B are constants.

12. The digital delta-sigma modulator of claim 10, wherein the nested cascaded structure comprises T levels of L error feedback modulators (EFM) stages comprising a first portion and a second portion, wherein the first portion comprises (L−1) error feedback modulator stages of each level and the second portion comprises the Lth error feedback modulator stage of each level, wherein the first portion and the error cancellation network implement the noise transfer function $NT{F}_A\left(z\right)=\frac{{\left(1-z^{-1}\right)}^S}{M}$ where S is equal to Σ.sub.j=1.sup.L-1 s.sub.j, where s.sub.j is the order of the EFM.sub.i,j wherein the noise transfer function NTF.sub.i,j(z)=M.sub.i.sup.−1(1−z.sup.−1).sup.s.sup.j with i=1, 2, . . . T and j=1, 2, . . . (L−1), and wherein the second portion implements the noise transfer function $NT{F}_B\left(z\right)=\frac{{\left(1-z^{-1}\right)}^{-S}}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

13. A system comprising a digital-to-analog converter and the digital delta-sigma modulator of claim 1 for providing a sequence of integers to control a DCO or DAC.

14. A fractional-N PLL device, comprising: a phase-locked loop comprising a digitally controlled oscillator, wherein the phase-locked loop generates an output frequency from the digitally controlled oscillator; and the digital delta-sigma modulator of claim 1 for providing a sequence of integers to control the DCO to produce a desired frequency.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present disclosure will be more clearly understood from the following description of an embodiment thereof, given by way of example only, with reference to the accompanying drawings, in which:

[0045] FIG. 1 shows a block diagram of a digital-intensive fractional-N PLL with a DCO;

[0046] FIG. 2(a) shows the block diagram of a conventional DCO controller based on a single quantizer digital delta-sigma modulator with shaped additive dither;

[0047] FIG. 2(b) shows the linearized model of the conventional DCO controller of FIG. 2(a);

[0048] FIG. 3 shows a block diagram of a conventional DCO controller based on a Multi stAge noise SHaping (MASH) digital delta-sigma modulator with shaped additive dither;

[0049] FIG. 4(a) shows a block diagram of a conventional Error Feedback Modulator (EFM);

[0050] FIG. 4(b) shows an implementation of the conventional Error Feedback Modulator (EFM) of FIG. 4(a);

[0051] FIG. 5 shows a block diagram of a conventional DCO controller based on a nested cascaded MASH digital delta-sigma modulator with shaped additive dither;

[0052] FIG. 6 shows a block diagram of a conventional additive LSB-dithered MASH 1-1 DCO controller with unfiltered additive dither;

[0053] FIG. 7 shows simulated spectra of the unfiltered dither and shaped quantization noise introduced by the DCO controller of FIG. 6;

[0054] FIG. 8 shows a simplified phase domain model of the phase noise introduced into the fractional-N frequency synthesizer by the DCO controller of FIG. 6 in the presence of a nonlinear distortion;

[0055] FIG. 9 shows simulated power spectral densities of (a) the output y[n] of the DCO controller of FIG. 6 and (b) the output y.sup.NL[n] of the DCO controller of FIG. 6 after nonlinear distortion;

[0056] FIG. 10 shows a block diagram of a conventional additive LSB-dithered MASH 1-1 DCO controller with bit rotation decoding;

[0057] FIG. 11 shows simulated power spectral densities of the output of the DCO controller in FIG. 6 after nonlinear distortion in the case of (a) where bit rotation is applied and (b) where bit rotation is not applied;

[0058] FIG. 12 shows a block diagram of an embodiment of a single quantizer inherently spur immune INIS-DDSM DCO controller in accordance with the present disclosure;

[0059] FIG. 13 shows a block diagram of an embodiment of an L-stage inherently spur immune INIS-DDSM DCO controller in accordance with the present disclosure, where the first (L−1) stages and the error cancellation network are configured to implement a noise transfer function NTF.sub.A(z) and the Lth stage is an error feedback modulator with noise transfer function NTF.sub.B(z);

[0060] FIG. 14 shows a block diagram of an embodiment of the error feedback modulator in the Lth stage of the L-stage inherently spur immune cascaded INIS-DDSM DCO controller in accordance with the present disclosure;

[0061] FIG. 15 shows a block diagram of an embodiment of a two-stage inherently spur immune cascaded INIS-DDSM DCO controller in accordance with the present disclosure, where the first stage is a first-order error feedback modulator with a noise transfer function M.sup.−1(1−z.sup.−1) and the second stage is an error feedback modulator with noise transfer function M.sup.−1(1−z.sup.−2−z.sup.−3);

[0062] FIG. 16 shows a block diagram of an embodiment of a T-level and L-stage inherently spur immune nested cascaded DCO controller in accordance with the present disclosure, wherein each level comprises (L−1) cascaded stages that together and with the error cancellation network implement a noise transfer function NTF.sub.A(z) and the remaining stages, one for each level, are configured to implement a noise transfer function NTF.sub.B(z);

[0063] FIG. 17 shows a block diagram of an embodiment of a two-level, two-stage inherently spur immune nested cascaded DCO controller in accordance with the present disclosure, where for each level i the first stage is a first-order error feedback modulator with a noise transfer function M.sub.i.sup.−1(1−z.sup.−1) and the second stage is an error feedback modulator with noise transfer function M.sub.i.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5);

[0064] FIG. 18 shows the simulated power spectral density of the output of a DCO controller distorted by a memoryless nonlinearity in the case of (a) a MASH 1-1 DCO controller with bit rotation and (b) the cascaded INIS-DDSM with K=4, R=2 shown in FIG. 15;

[0065] FIG. 19 shows the simulated power spectral density of the output of a DCO controller distorted by a memoryless nonlinearity in the case of (a) a Successive Requantizer (SR) DCO controller with spur immunity and (b) the nested cascaded INIS-DDSM with K=6, R=3 shown in FIG. 17; and

[0066] FIG. 20 shows the simulated power spectral density of the output of a DCO controller distorted by a memoryless nonlinearity in the case of (a) a MASH 1-1 DCO controller without bit rotation, (b) a MASH 1-1 DCO controller with bit rotation and (c) the cascaded INIS-DDSM with K=4, R=2 shown in FIG. 15.

DETAILED DESCRIPTION

[0067] The present disclosure provides a DDSM-based DAC controller that, among other applications, it is suitable for use as a DCO controller with a digital-intensive PLL-based fractional-N frequency synthesizer which provides Immunity from Nonlinearity-Induced Spurs, denoted INIS-DDSM. When used as a DCO controller, this modulator eliminates the spurs that arise due to interaction between the quantization error introduced by the DCO controller and a memoryless nonlinearity in the DCO. Furthermore, it does not exhibit the wandering spur phenomenon. The present disclosure will now be described in conjunction with FIG. 12 onwards.

[0068] The digital delta sigma modulator (DDSM) of the disclosure implements the z domain governing equation

Y(z)=STF(z)X(z)+DTF(z)D(z)−NTF(z)E(z),

where Y(z), X(z), D(z) and E(z) are the z transforms of the output, primary input, secondary (dither) input, and quantization error of the DDSM, and wherein STF(z), DTF(z) and NTF(z) are the transfer functions from the primary input, dither input and quantization error to the output and wherein NTF(z) is of the form:

[00017]$\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

where A, Q and K are constants, all the coefficients c.sub.i are real valued and c.sub.K≠0, and at least one of the zeroes z.sub.j of

[00018]$\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

satisfies z.sub.j≠+1 for j=1, 2, . . . , K.

[0069] Taking A z.sup.−Q to be equal to 1/M, the DCO controller of the disclosure thus implements a Noise Transfer Function

[00019]$\mathrm{NTF}\left(z\right)=\frac{1}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

[0070] In one embodiment, the coefficients c.sub.i are equal to −1, 0 or 1.

[0071] In one embodiment, the coefficients c.sub.i are valued such that the noise transfer function can be represented in the form:

[00020]$\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1-z^{-1}\right)\left(1+\underset{i=1}{\overset{K-1}{.Math.}}{d}_i{z}^{-i}\right)$

and wherein

[00021]$\underset{i=1}{\overset{K}{.Math.}}.Math.c_i.Math.\le -1+2\underset{i=1}{\overset{K-1}{.Math.}}.Math.d_i.Math.$

[0072] In one embodiment, R number of the coefficients c.sub.i are equal to −1, (R−1) number of the coefficients c.sub.i are equal to +1 and the other (K−2R+1) number of the coefficients c.sub.i are equal to zero, with

[00022]$R\le \frac{K+1}{2}.$

[0073] FIG. 12 shows a first embodiment of the present disclosure where the DCO controller comprises a single Error Feedback Modulator (EFM) stage that constitutes a single quantizer digital delta-sigma modulator.

[0074] FIG. 13 shows a second embodiment of the present disclosure where the DCO controller comprises an error cancellation network and a cascade of L number single quantizer or Error Feedback Modulator (EFM) stages, wherein the L Error Feedback Modulator (EFM) stages comprise a first portion and a second portion. The first portion comprises (L−1) stages and the second portion comprises the Lth stage. The first portion, together with the error cancellation network, implements a Noise Transfer Function

[00023]${\mathrm{NTF}}_A\left(z\right)=\frac{{\left(1-z^{-1}\right)}^S}{M}$

where S is equal to Σ.sub.i=1.sup.L-1 s.sub.i, where s.sub.i is the order of the EFM.sub.i wherein the noise transfer function NTF.sub.i(z)=M.sup.−1(1−z.sup.−1).sup.s.sup.i with i=1, 2, . . . (L−1). The second portion, comprising the Lth stage, is configured to implement a Noise Transfer Function

[00024]${\mathrm{NTF}}_B\left(z\right)=\frac{{\left(1-z^{-1}\right)}^{-S}}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right),$

so as to give the overall Noise Transfer Function for the modulator set out previously.

[0075] Each of the L stages may be implemented with pipelined combinatorial logic. The outputs of the L stages are combined in the error cancellation network to yield the output y.

[0076] DDSMs with constant inputs are known to suffer from limit cycles. Therefore, a binary dither signal, denoted d[n], is added into the signal chain to prevent limit cycle behavior.

[0077] In one embodiment, R number of the coefficients c.sub.i are equal to −1, (R−1) number of the coefficients c.sub.i are equal to +1 and the other (K−2R+1) number of the coefficients c.sub.i are equal to zero, with

[00025]$R\le \frac{K+1}{2}.$

[0078] For example, with K=6 and R=3, the Noise Transfer Function

NTF(z)=M.sup.−1(1−z.sup.−1+z.sup.−2−z.sup.−3−z.sup.−4+z.sup.−6),

can be implemented in the multistage cascaded structure of FIG. 13 by partitioning factors of the NTF between a number of different stages.

[0079] By choosing S=1, the NTF can be realized by a cascade of two stages wherein the NTF of one stage is

NTF(z)=M.sup.−1(1−z.sup.−1)

and the NTF of the other stage is

NTF(z)=M.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5).

[0080] By choosing S=2, the NTF can be expressed as

NTF(z)=M.sup.−1(1−z.sup.−1).sup.2(1+z.sup.−1+2z.sup.−2+2z.sup.−3+z.sup.−4),

and implemented with a three-stage cascaded structure wherein two identical EFM stages have NTFs of

NTF(z)=M.sup.−1(1−z.sup.−1)

and the NTF of the third stage is

NTF(z)=M.sup.−1(1+z.sup.−1+2z.sup.−2+2z.sup.−3+z.sup.−4)

Moreover, the same NTF can be implemented with a two-stage cascaded structure wherein one stage has NTF of

NTF(z)=M.sup.−1(1−z.sup.−1).sup.2

and the second stage has NTF of

NTF(z)=M.sup.−1(1+z.sup.−1+2z.sup.−2+2z.sup.−3+z.sup.−4).

[0081] It should be clear that a number of different, but equivalent, partitions of the NTF are possible. The spurious tone immunity derives from the structure of the NTF rather than any particular implementation.

[0082] FIG. 14 shows an implementation of the Lth stage of FIG. 13. The output Y(z) is defined by

Y(z)=STF(z)X(z)−NTF.sub.B(z)E(z)

[0083] FIG. 15 shows an implementation of the DCO controller in FIG. 13 with L=2 and S=1. Here, the dither signal d[n] has been added at the first stage to implement unfiltered LSB dithering.

[0084] In the embodiment of the two-stage cascade in FIG. 15, K=4 and R=2. In particular, the first stage, EFM.sub.1 has a noise transfer function

NTF.sub.1(z)=M.sup.−1(1−z.sup.−1)

and the second stage, EFM.sub.2, has noise transfer function

NTF.sub.2(z)=M.sup.−1(1−z.sup.−2−z.sup.−3),

giving an overall Noise Transfer Function for the modulator of

NTF(z)=M.sup.−1(1−z.sup.−1)(1−z.sup.−2−z.sup.−3).

[0085] FIG. 16 shows a third embodiment of the present disclosure where the DCO controller comprises an error cancellation network and T levels of L cascaded single quantizer stages comprising a first portion and a second portion. The first portion comprises (L−1) number error feedback modulator stages of each level and the second portion comprises the Lth error feedback modulator stage of each level. The first portion together with the error cancellation network, implement the Noise Transfer Function

[00026]${\mathrm{NTF}}_A\left(z\right)=\frac{{\left(1-z^{-1}\right)}^S}{M}$

where S is equal to Σ.sub.j=1.sup.L-1 s.sub.j, where s.sub.j is the order of the EFM.sub.i,j wherein the noise transfer function NTF.sub.i,j(z)=M.sup.−1(1−z.sup.−1).sup.s.sup.j with i=1, 2, . . . T and j=1, 2, . . . (L−1). The second portion implements the Noise Transfer Function

[00027]${\mathrm{NTF}}_B\left(z\right)=\frac{{\left(1-z^{-1}\right)}^{-S}}{M}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right),$

so as to give the overall Noise Transfer Function for the modulator set out previously.

[0086] The outputs of the L stages of the first cascade are combined in the error cancellation network to yield the output y.

[0087] In one embodiment, R number of the coefficients c.sub.i are equal to −1, (R−1) number of the coefficients c.sub.i are equal to +1 and the other (K−2R+1) number of the coefficients c.sub.i are equal to zero, with

[00028]$R\le \frac{K+1}{2}.$

[0088] Once again, it should be clear that a number of different, but equivalent, partitions of the NTF over T levels are possible. The spurious tone immunity derives from the structure of the NTF rather than the particular implementation.

[0089] Digital delta sigma modulators with constant inputs are known to suffer from cycles. Therefore, a binary dither signal, denoted d[n], is added into the signal chain to prevent cycle behavior.

[0090] FIG. 17 shows an implementation of the DCO controller in FIG. 16 with T=2, L=2 and S=1. The 8-bit input word x[n] added to the filtered dither is partitioned into two smaller 4-bit words {circumflex over (x)}.sub.i[n]. The outputs of the stages of the second cascade are added to the inputs of the stages of the first cascade.

[0091] In the embodiment of the two-stage nested cascade in FIG. 17, K=6 and R=3. In particular, the first stage of both levels are EFM1s and have noise transfer functions

NTF.sub.1,1(z)=M.sub.1.sup.−1(1−z.sup.−1)

NTF.sub.2,1(z)=M.sub.2.sup.−1(1−z.sup.−1)

and the remaining stages have noise transfer functions

NTF.sub.1,2(z)=M.sub.1.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5)

NTF.sub.2,2(z)=M.sub.2.sup.−1(1+z.sup.−2−z.sup.−4−z.sup.−5).

giving an overall Noise Transfer Function for the modulator of

NTF(z)=M.sup.−1(1−z.sup.−1)(1+z.sup.−2−z.sup.−4−z.sup.−5)

[0092] FIG. 18 shows a comparison of the power spectral density of the distorted output of the DCO controller, y.sup.NL[n] with two different DCO controllers: (a) the MASH 1-1 with bit rotation and (b) the cascaded INIS-DDSM with K=4, R=2 shown in FIG. 15.

[0093] In FIG. 18, x=1 and M=2.sup.8, and the nonlinearity is the following polynomial function

[x]=0.025+0.933x−0.0875x.sup.2+0.0542x.sup.3.

[0094] The spurs and folded noise caused by interaction between the output y of the DCO controller and the nonlinearity [⋅] in the loop can be minimized by choosing NTF.sub.A(z) and NTF.sub.B(z) as described.

[0095] By comparison with the MASH 1-1 with bit rotation DCO controller, it can be seen from FIG. 18 that the use of an INIS-DDSM results in the elimination of spurs and a lower folded noise floor in the spectrogram of y.sup.NL[n].

[0096] FIG. 19 shows a comparison of the power spectral density of the distorted output of the DCO controller, y.sup.NL[n] with two different DCO controllers: (a) the Successive Requantizer and (b) the nested cascaded INIS-DDSM with K=6, R=3 shown in FIG. 17.

[0097] In each case, the memoryless nonlinearity is the following polynomial function

N(x)=0.025+0.949x−0.113x.sup.2+0.0477x.sup.3+0.0256x.sup.4−0.00896x.sup.5

[0098] Furthermore, x=1 and M=2.sup.8.

[0099] It can be seen from FIG. 19 that the use of the noise transfer function NTF(z)=M.sup.−1(1−z.sup.−1)(1+z.sup.−2−z.sup.−4−z.sup.−5) results in the elimination of spurs with a low folded noise floor and a lower PSD of y.sup.NL[n] in the range [0.005,0.05] of the normalized frequency.

[0100] FIG. 20 shows a comparison of the power spectral density of the distorted output of the DCO controller, y.sup.NL[n] with three different DCO controllers: (a) the MASH 1-1 without bit rotation, (b) the MASH 1-1 with bit rotation and (c) the cascaded INIS-DDSM with K=4, R=2 shown in FIG. 15.

[0101] In FIG. 20, the first input x[n] is a highly oversampled sinusoidal signal,

[00029]$x\left[n\right]=\mathrm{round}\left(10+10\sin \left(\frac{2\pi \left[n\right]}{2000}\right)\right),$

where round(⋅) represents the rounding to the nearest integer function, M=2.sup.10, and the nonlinearity is the polynomial function

N[x]=0.025+0.933x−0.0875x.sup.2+0.0542x.sup.3.

[0102] The case of the MASH 1-1 without bit rotation exhibits the lowest folded noise but it also shows many spurious tones. The latter can be mitigated by using bit rotation, at the cost of an elevated noise floor.

[0103] The spurs and folded noise caused by interaction between the output y of the DCO controller and the nonlinearity [-] in the loop can be minimized by choosing NTF.sub.A(z) and NTF.sub.B(z) as described.

[0104] By comparison with the MASH 1-1 DCO controller with bit rotation, it can be seen from FIG. 20 that the use of an INIS-DDSM results in the elimination of spurs and a lower folded noise floor in the spectrogram of y.sup.NL[n].

[0105] When used as a DCO controller, the INIS DDSM can be appreciated for improving the noise performance in terms of mitigation of spurs and reduction of folded noise in cases of both constant and slowly time-varying inputs

[0106] When incorporated in a fractional-N frequency synthesizer, the DDSM-based DCO controller has an output y[n] with a range that has a spread P, where P represents the number of capacitance steps driven by y[n]. In the presence of mismatch between the capacitances of the P capacitors, the signal y[n] encounters a memoryless nonlinearity that can be always expressed as a polynomial function with order P.

[0107] That being said, the INIS DCO controller of the present disclosure with noise transfer function NTF(z)=M.sup.−1(1+Σ.sub.i=1.sup.K c.sub.iz.sup.−i) which satisfies the conditions described above and with a given R does not exhibit spurs if

[00030]$R\ge \frac{P+1}{2}.$

Furthermore, the INIS-DDSM of the present disclosure is characterized by having an output y[n] that has a spread P=(2R−1). It follows that

[00031]$R=\frac{P+1}{2}$

and, therefore, the DCO controller is inherently immune to any memoryless nonlinearity that is faced by y[n].

[0108] Accordingly, the use of a DDSM based DCO controller having the above described noise transfer function results in the generation of a signal that is characterised by an improved spur immunity performance when distorted by static polynomial nonlinearities. Thus, it will be appreciated that the DCO controller of the present disclosure, when used with a fractional-N frequency synthesizer, provides a signal that is immune from spurs and less prone to produce folded noise than a frequency synthesizer which uses a conventional dithered digital delta-sigma modulator. Through the minimization of nonlinearity-induced folded noise and the mitigation of spurs, it enables the frequency synthesizer to generate cleaner carriers for a range of applications including communications, radar and instrumentation.

[0109] In the specification the terms “comprise, comprises, comprised and comprising” or any variation thereof and the terms include, includes, included and including” or any variation thereof are considered to be totally interchangeable and they should all be afforded the widest possible interpretation and vice versa.

[0110] The present disclosure is not limited to the embodiments hereinbefore described but may be varied in both construction and detail.