VOLTAGE REFERENCE GENERATOR AND TRIMMING SYSTEM

Abstract

Embodiments of the present disclosure may relate to a voltage reference generator comprising: a local heater structured to generate continuous controlled temperature and uniform thermal profile, at multiple points further comprising a Bipolar Junction, Transistors, and a heating element. Embodiments may additionally include temperature compensated resistances adopted to generate constant temperature compensated voltage reference current using an operational amplifier, a transistor, and two or more resistors, positive and negative. The embodiments may further include, current mirrors comprising a plurality of MOS transistors configured to mirror current flowing in the PMOS transistor. Further embodiments may include, digital modulators structured to generate modulated control signals, the control signals being structured to control a temperature by trimming change in the voltage reference, and a Digital to Analog Converter configured to generate output current proportional to a current reference mirrored in one or more of the plurality of transistors.

Claims

1. A Voltage reference Generator comprising: a local heater structured to generate continuous controlled temperature and uniform thermal profile, at multiple points further comprising a Bipolar Junction, Transistors, and a heating element; temperature compensated resistances adopted to generate constant temperature compensated voltage reference current using an operational amplifier, a PMOS transistor, and two or more resistors, positive and negative; current mirrors comprising a plurality of MOS transistors configured to mirror current flowing in the PMOS transistor; digital modulators structured to generate modulated control signals; one or more control signals including modulated digital bits being structured to control the temperature generated from the local heater in conjunction with variable resistances, by trimming change in the voltage reference; and a Digital to Analog Converter configured to generate output current proportional to a current reference mirrored in one or more of the plurality of transistors.

2. A voltage reference generator of claim 1, wherein one or more of the plurality of transistors is generating heat by thermal effect from ohmic loss of current flowing through a drain to source terminals of the one or more of the plurality of transistors.

3. A voltage reference generator of claim 1, where-in digital modulators include one or more of a pulse width modulator and a pulse density modulator.

4. A voltage reference generator of claim 1, further comprising: a Circuit comprising: a first chopped operational amplifier and output terminal of the first chopped operational amplifier is coupled with gate terminal of a first transistor and drain terminal of the first transistor is coupled to first terminal resistance and second terminal of said first resistance is further coupled to first terminal of second resistance and third resistance and current output terminal of current DAC, a second terminal of said second resistance and third resistance is coupled to first terminal of fourth variable resistance and fifth variable resistance and sixth variable resistance and input terminals of the said first chopped operational amplifier, said sixth resistance is coupled to first bipolar transistor and second bipolar transistor is coupled to second terminal of second resistance and a third bipolar transistor emitter is coupled to second terminal of said fourth resistance and fifth resistance, said third bipolar transistor is coupled to a second transistor, gate terminals of the second, a third, and a fourth transistor are coupled to a second chopped amplifier output terminal and positive terminal of said second chopped amplifier is coupled to drain terminal of said fourth transistor and first terminal of a seventh resistance with positive temperature coefficient and second terminal of said seventh resistance is coupled to first terminal of eighth resistance; and a drain terminal of said third transistor is coupled to current reference input terminal of the said current DAC the current DAC output terminal is coupled to first resistance.

5. A method for calibrating a Voltage Reference Circuit of claim 4 comprising a first sensing transistor and second sensing transistor and third sensing transistor biased with temperature independent current and on chip heating element configured to generate high resolution temperature steps, the method comprising: performing a first voltage calibration while heater is off or at lowest modulation index of using control 1 by changing one or more current mode DAC inputs to a value where reference voltage is at desired value at one temperature point; performing a second voltage calibration by activating heater with control 3 input to heater then monitoring the change in reference voltage by changing the modulation index of control 3 input then decreasing this change by changing a first variable resistor with control 2 and repeat the second voltage calibration—until there is change in output voltage more than acceptable accuracy with change in heater control input; and performing a third voltage calibration by activating heater with control 3 input to heater then monitoring the change in reference voltage by changing the modulation index of control 3 input then decreasing this change by changing a second variable resistor with control 4 and repeat the third voltage calibration until there is change in output voltage more than acceptable accuracy with change in heater control input.

6. The method of claim 5, wherein the modulation index is defined by a ratio of high time of control input to sum of high time and low time period of control input where high time indicated a duration where heater is on and low time indicates where heater is off and further sum of high time and low time is a total modulation interval.

7. The method of claim 5, wherein the acceptable accuracy is a ratio of variation in reference voltage of a device with temperature and nominal value of the reference voltage expressed in percentage.

8. The method of claim 5, wherein the control signals being structured so that the modulation index values achieved during calibration process are stored in memory to be used in future when device is in normal use for reference voltage vs temperature curve compensation.

Description

BRIEF DESCRIPTION OF FIGURES

[0030] FIG. 1: Prior Art

[0031] FIG. 2: Present Invention with curvature compensation

[0032] FIG. 3: Curvature compensation impact and precision improvement

[0033] FIG. 4: Trimming Controls impact on transfer curve

[0034] FIG. 5: Digital Modulator and Heating Time Constant as Filter

[0035] FIG. 6: Resistance Trimming Implementation

DETAILED DESCRIPTION OF INVENTION

[0036] Voltage reference generation prior art shown in FIG. 1 has output reference voltage V.sub.REF is generated by defined by following equation

[00001]$\begin{array}{cc}{V}_{\mathrm{REF}}=V_{BE2}+{\Delta V}_{\mathrm{BE}}*\alpha & \left(1\right)\end{array}$$\begin{array}{cc}{V}_{\mathrm{REF}}=V_{BE2}+V_T*\ln \left(N\right)*\frac{R1}{R2}& \left(2\right)\end{array}$

[0037] In equation 1 and 2 V.sub.BE2 is base to emitter voltage difference of the Bipolar Junction Transistor (BJT) Q2 and ΔV.sub.BE is the difference V.sub.BE of the transistor Q1 and Q2, VT is a constant proportional to temperature and N is the base area ratio of Q1 and Q2.

[0038] As it clear from the equation 2 that if all other variables are like operational amplifier (opamp) offset and resistance mismatch is ignored then V.sub.REF temperature dependence is defined by the V.sub.BE voltage of the BJT. It is well known that V.sub.BE of the BJT is defined by saturation current (Is) and collector current (Ic) by following equation.

[00002]$\begin{array}{cc}{V}_{BE}=V_T\ln \left(\frac{I_C}{I_S+\Delta I_S}\right)& \left(3\right)\end{array}$

[0039] It can be proven that any change in Ic and Is is actually proportional to temperature and it can be cancelled by adjusting the resistance R2. In CMOS process current gain beta is highly process dependent and it has non-linear temperature impact on V.sub.BE and this needs curvature compensation to improve the accuracy of the generated reference voltage. Another component is the base resistance of the BJT which is also one of the contributors to the accuracy of the V.sub.BE with temperature. The impact of the current gain beta and base resistance is required to be compensated using curvature compensation. This kind of curvature compensation needs voltage information at multiple temperature points and discrete temperature points might miss the actual peaks of the change in V.sub.REF as shown in FIG. 3.

[0040] The present invention is described with the help FIG. 2 wherein Voltage reference Generator comprises Local heater (101) which consists a ohmic heating element (104) made from MOS transistor MN1, where MOS transistor MN1 is generating heat by thermal effect from ohmic loss of current flowing through the drain to source terminals of MOS MN1, temperature compensated resistances (102) consisting two or more resistances of positive (RP) and negative (RN) temperature coefficients with their values pre-determined in a way that total temperature coefficient of combined resistance is lower than their individual temperature coefficients, current mirrors (103) consisting of plurality of MOS transistors M2,M3,M4, where in current flowing in M4 is generated by V.sub.REF/(RP+RN) using operational amplifier Op2 and further mirrored to MOS M2 and M3, current mirrored in MOS M3 is reference current IREF for current DAC (105) which is further used to generate current output i.e. proportional to IREF using control signal CTRL1 and further current mirrored through MOS M2 is used to bias BJT Q3 which has its emitter coupled to drain of MOS M2 and emitter of BJT Q3 is further coupled to first terminal of variable resistance R3a and R3b, R3a and R3b resistance can be simultaneously changed by signal CTRL4, The second terminal of resistance R3a is coupled to emitter terminal of BJT Q2 and first terminal of resistance R1a, further the second terminal of resistance R3b is coupled to first terminal of variable resistance RV controlled by CTRL2 and first terminal of resistance Rib, further the second terminal of variable resistance Rv is coupled to emitter of BJT Q1 and further the second terminals of resistances R1a, R1b are coupled to further output of said DAC (105) and first terminal of resistance Ro, second terminal of resistance Ro is coupled to drain terminal of MOS M1 generating reference voltage output V.sub.REF, gate terminal of MOS M1 is coupled to output terminal of operational amplifier OP1, differential input terminals of operational amplifier OP1 are coupled to first terminals of resistance R1a,R1b, signals CTRL1 CTRL2, CTRL3, CTRL4 can be digital bits which are pulse width modulated (PWM) or pulse density modulated (PDM) in order to control the temperature generated from the local heater (101) in order to achieve continuous temperature control. By application of pulse modulation to the heating elements the total heat generated proportional to the modulation index D defined by high time Tx and Low time TL of the control signals

[00003]$\begin{array}{cc}D=\frac{T_H}{T_L+T_H}& \left(4\right)\end{array}$

[0041] As shown in FIG. 5 the example structure of a digital modulator 401 is shown where input 403 is a digital number of 12 bits which can change from 0-4095 and generate 4096 different scenarios of modulation index D to control the heating element 402, similar arrangement is applicable for all other control signals.

[0042] Present invention is able use the trimming control CTRL1, CTRL2 and CTRL4 to achieve acceptable change in V.sub.REF when on-chip heater is used to change the die temperature using CTRL3 signal and MN1. For example, the V.sub.REF voltage is measured and change in V.sub.REF is served and CTRL2 and CTRL4 are changed in the direction so that change in V.sub.REF is minimum when heater control modulation factor changed from lowest value to highest value. Same process is repeated at increased value of the CTRL3 using input 403. For those skilled in the art, it is true that there could be multiple optimization schemes possible for the control of CTRL1, CTRL2 and CTRL4 and present invention is not limited to use of any of these like Multi-Layer (ML) least mean square (LMS) algorithm, etc. CTRL1, CTRL2 and CTRL4 are controlled by Pulse Width Modulators (PWM) and/or Pulse Density Modulators (PDM) signals be generated by modulators such as delta sigma modulators. The modulation index of the modulator controls the density of the PWM/PDM signals and hence the heater average power which is resulting in temperature increase.

[0043] The calibration is conducted by: [0044] (a) performing the first voltage calibration while heater is off or at lowest modulation index of using control 1 by changing the said current mode DAC inputs to a value where reference voltage is at desired value at one temperature point, [0045] (b) Performing the second voltage calibration by activating heater with control 3 input to heater then monitoring the change in reference voltage by changing the modulation index of control 3 input then minimising this change by changing the first variable resistor with control 2 and repeat the process until there is change in output voltage more than acceptable accuracy with change in heater control input, [0046] (c) Performing the third voltage calibration by activating heater with control 3 input to heater then monitoring the change in reference voltage by changing the modulation index of control 3 input then minimising this change by changing the second variable resistor with control 4 and repeat the process until there is change in output voltage more than acceptable accuracy with change in heater control input.

[0047] Performing the second voltage calibration by activating heater with highest modulation index with control input to heater and changing the first variable resistor to minimise the proportional change in voltage with heater control modulation index then increasing the control input to the heater and changing the first variable resistor to further minimise the change in V.sub.REF voltage with change in temperature

[0048] Present invention as shown in FIG. 2 where Opamp OP1 is chopped for its intrinsic offset and output of the Opamp OP1 is coupled with gate terminal of PMOS M1 and drain terminal of PMOS M1 is coupled first terminal of R0 and second terminal of R0 is further coupled to first terminal of resistance R1a, R1b and current DAC [105] output, second terminal of R1a and R1b is coupled to first terminal of R3a, R3b, Rv and Op1 input terminals. BJT Q1 is coupled to second terminal of Rv and Q2 is coupled to second terminal of R1a and Q3 emitter is coupled to second terminal of R3a, R3b. BJT Q3 is coupled to PMOS M2. Gate terminals of PMOS M2, M3, M4 are coupled to chopped Opamp OP2 output and positive terminal of OP2 is coupled to Drain Terminal of PMOS M4 and Resistance Rp with positive temperature coefficient and second terminal of resistance R.sub.P is coupled to R.sub.N. Drain terminal of M3 is coupled to current reference input terminal of the current DAC [105].

[0049] Present invention is using a constant temperature compensated current generated using OP2, PMOS M4 and resistors RP, RN. This compensated current is mirrored using PMOS M2 and biasing the transistor Q3. Emitter of transistor Q3 is further coupled to input terminals of OPAMP OP1.

[00004]$\begin{array}{cc}{V}_{REF}=V_{BE0}-\left(V_{BE0}-V_{BE2\left(T0\right)}\right)*\frac{T}{T0}-\left(\gamma -1\right)*V_T*\ln \left(N\right)*\frac{R1+2R0}{Rv}*\frac{R3}{R1+2R0}& \left(3\right)\end{array}$

[0050] Where γ is a process dependent constant and V.sub.BE0 is V.sub.BE at absolute temperature. If R3 is trimmed in such a way that

[00005]$\frac{R3}{R1+2R0}$

is able to cancel the component (γ−1) and in component

[00006]$\frac{R1+2R0}{Rv},$

resistance Rv adjusted in such a way that

[00007]$\left(V_{\mathrm{BE}0}-V_{\mathrm{BE}2\left(T0\right)}\right)*\frac{T}{T0}$

is cancelled then V.sub.REF is independent of the temperature and it is equal to V.sub.BE0 which is bandgap voltage of silicon and best precision is achieved.

[0051] Present invention has application of 4 control signals to perform the trimming of the proposed circuit and achieve desired precision of the generated voltage.

[0052] As shown in FIG. 2 the signals named CTRL1, CTRL2, CTRL3 and CTRL 4 are generated using pulse density modulation as shown in FIG. 5 and FIG. 6. Where examples at FIG. 5 and FIG. 6 using second order delta sigma modulators for illustration purpose but they are not limited to it and someone skilled in the art can apply any other modulator architecture to improve the precision of the trimming circuit.

[0053] As shown in FIG. 7 the signal CTRL1 is used to change the V.sub.REF voltage independent of temperature using the current DAC 105 and CTRL2 is used change the slope of the output voltage V.sub.REF using the trimming of Rv, with temperature. Signal CTRL4 is used to cancel the (γ−1) component of the equation 3.

[0054] DAC 105 is a current mode DAC where reference current is temperature compensated current derived from

[00008]$\frac{V\mathrm{REF}}{RP+RN}$

and based on digital codes it is changing the V.sub.REF voltage by R.sub.0*I.sub.DAC where I.sub.DAC is the current at output of the DAC 105.

[0055] Control signal CTRL3 is the output of the digital delta sigma modulator 401 and it may have lower resolution as compared to input signal DIN 403. As thermal time constant can be much higher as compared to modulator clock period the complete arrangement is an electro thermal filter with much higher precision for the control of the temperature. Signal DIN 403 and temperature generated by the heater are proportional in nature but not linear. Present invention enables precise temperature control by changing the modulation index of the PWM/PDM signals generated from the delta sigma modulators, as compared to prior arts [1-8] hence enables to find each temperature point with maxima and minima to trim the resistances for better accuracy.

[0056] Present invention also enables the independent control of the output V.sub.REF for slope and offset as shown in FIG. 7 using CTRL1 and CTRL2 control signals and also enables curvature compensation using trimming of the resistance R3a, R3b using control signal CTRL4.

[0057] Control signals CTRL2 and CTRL4 are inputs of resistive DAC implemented in Rv and R3a, R3b by switching the resistances on and off in digital proportion hence producing a variable resistance.

[0058] The method for calibrating the Voltage Reference Circuit comprising a first sensing transistor Q1 and second sensing transistor Q2 and third sensing transistor Q3 biased with temperature independent current generated by M2 and on chip heating element MN1 configured to generate high resolution temperature steps with modulated third input CTRL3. First variable resistor Rv coupled to first sensing transistor Q1 and second pair of variable resistors R3a, R3b coupled to second sensing transistor Q2 and third pair of resistors R1a, R1b coupled to said second pair of resistors R3a, R3b and current mode digital to analog converter 105 with temperature independent reference current 103. The calibration method is performed by doing the first voltage calibration while heater is off by changing the said current mode digital to analog converter 105 input CTRL1 to adjust the output voltage at desired level then performing the second voltage calibration by activating heater 104 on with first control input CTRL3 to heater and changing the first variable resistor Rv to minimise the proportional change in voltage with heater at first modulation index value then increasing the modulation index to the second value of the heater 104 and changing the first variable resistor Rv to further minimise the proportional change in voltage V.sub.REF and repeat the process until there is change in output voltage more than first tolerance with increase in heater control input. Then performing the third voltage calibration by starting the heater 104 with third modulation index and minimise the overall change in voltage by changing the second pair of resistors R3a, R3b control CTRL4 and repeat the process until change in voltage is lower than second tolerance.