COMMON-MODE INSENSITIVE CURRENT-SENSING TOPOLOGY IN FULL-BRIDGE DRIVER

Abstract

A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated. The current sensing circuitry may also include a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated. The system may also include measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current.

Claims

1. A system comprising: a Class-D stage comprising: a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage; a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage; a first low-side switch coupled between a ground voltage and the first output terminal; and a second low-side switch coupled between the ground voltage and the second output terminal; and current sensing circuitry comprising: a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated; a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated; and measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current.

2. The system of claim 1, wherein the measurement circuitry comprises an amplifier configured to amplify a difference between the first sense voltage and the second sense voltage to generate a combined sense voltage.

3. The system of claim 1, wherein the Class-D stage further comprises: a third sense resistor coupled between the first low-side switch and the ground voltage, such that an output current through the load causes a third sense voltage proportional to the output current across the third sense resistor when the first low-side switch is activated; and a fourth sense resistor coupled between the second low-side switch and the ground voltage, such that an output current through the load causes a fourth sense voltage proportional to the output current across the fourth sense resistor when the second low-side switch is activated; wherein the measurement circuitry is configured to measure the third sense voltage and the fourth sense voltage to determine the output current.

4. The system of claim 3, wherein the measurement circuitry further comprises: a first amplifier configured to amplify a difference between the first sense voltage and the second sense voltage to generate a high-side sense voltage; and a second amplifier configured to amplify a difference between the third sense voltage and the fourth sense voltage to generate a low-side sense voltage.

5. The system of claim 4, wherein the measurement circuitry further comprises a combiner configured to combine the high-side sense voltage and the low-side sense voltage to generate a combined sense voltage indicative of the output current.

6. The system of claim 1, further comprising a calibration subsystem comprising a first calibration resistor and a second calibration resistor and configured to calibrate for mismatch between common mode phases of the Class-D stage.

7. The system of claim 6, wherein the first calibration resistor is coupled between the first sense resistor and an amplifier and the second calibration resistor is coupled between the second sense resistor and the amplifier.

8. The system of claim 6, wherein the first calibration resistor and the second calibration resistor comprise feedback resistors of an amplifier.

9. The system of claim 6, wherein the calibration subsystem is further configured to: calibrate a first variable resistance of the first calibration resistor when the second sense resistor is in a fully-differential current path of the output current; and calibrate a second variable resistance of the second calibration resistor when the first sense resistor is in the fully-differential current path of the output current.

10. The system of claim 6, wherein the calibration subsystem is further configured to: calibrate a first variable resistance of the first calibration resistor when a polarity of the output current is a first polarity; and calibrate a second variable resistance of the first calibration resistor when the polarity of the output current is a second polarity.

11. The system of claim 10, wherein the calibration subsystem is further configured to alternate between calibration of the first variable resistance and the second variable resistance, and vice versa, at zero crossings of the output current.

12. A method, in a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal, comprising: measuring a first sense voltage with a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes the first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated; measuring a second sense voltage with a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes the second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated; and determining the output current based on both of the first sense voltage and the second sense voltage.

13. The method of claim 12, further comprising amplifying a difference between the first sense voltage and the second sense voltage to generate a combined sense voltage.

14. The method of claim 11, further comprising: measuring a third sense voltage with a third sense resistor coupled between the first low-side switch and the ground voltage, such that an output current through the load causes the third sense voltage proportional to the output current across the third sense resistor when the first low-side switch is activated; measuring a fourth sense voltage with a fourth sense resistor coupled between the second low-side switch and the ground voltage, such that an output current through the load causes the fourth sense voltage proportional to the output current across the third sense resistor when the second low-side switch is activated; and determining the output current based on the first sense voltage, the second sense voltage, the third sense voltage, and the fourth sense voltage.

15. The method of claim 14, further comprising: amplifying a difference between the first sense voltage and the second sense voltage to generate a high-side sense voltage; and amplifying a difference between the third sense voltage and the fourth sense voltage to generate a low-side sense voltage.

16. The method of claim 15, further comprising combining the high-side sense voltage and the low-side sense voltage to generate a combined sense voltage indicative of the output current.

17. The method of claim 12, further comprising calibrating for mismatch between common mode phases of the Class-D with a calibration subsystem comprising a first calibration resistor and a second calibration resistor and configured to calibrate for mismatch between common mode phases of the Class-D stage.

18. The method of claim 17, wherein the first calibration resistor is coupled between the first sense resistor and an amplifier and the second calibration resistor is coupled between the second sense resistor and the amplifier.

19. The method of claim 17, wherein the first calibration resistor and the second calibration resistor comprise feedback resistors of an amplifier.

20. The method of claim 17, further comprising: calibrating a first variable resistance of the first calibration resistor when the second sense resistor is in a fully-differential current path of the output current; and calibrating a second variable resistance of the second calibration resistor when the first sense resistor is in the fully-differential current path of the output current.

21. The method of claim 17, further comprising: calibrating a first variable resistance of the first calibration resistor when a polarity of the output current is a first polarity; and calibrating a second variable resistance of the first calibration resistor when the polarity of the output current is a second polarity.

22. The method of claim 21, further comprising alternating between calibration of the first variable resistance and the second variable resistance, and vice versa, at zero crossings of the output current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

[0012] FIG. 1 illustrates an example circuit topology for a Class-D driver and transducer, as is known in the prior art;

[0013] FIG. 2 illustrates an example personal mobile device, in accordance with embodiments of the present disclosure;

[0014] FIG. 3 illustrates a block diagram of selected components of an example integrated circuit of a personal mobile device for driving a transducer, in accordance with embodiments of the present disclosure;

[0015] FIG. 4 illustrates a block and circuit diagram of selected components of an example Class-D stage and measurement circuit, in accordance with embodiments of the present disclosure;

[0016] FIG. 5 depicts a Class-D amplifier in various example phases of its switches for a positive output current and the path of electrical current flow in each of the example phases, in accordance with embodiments of the present disclosure;

[0017] FIG. 6 depicts example waveforms for PWM control signals, output current generated based on the PWM control signals, and a sense voltage that may be generated based on current flowing through the sense resistors of FIG. 4 in the various phases depicted in FIG. 5, in accordance with embodiments of the present disclosure;

[0018] FIG. 7 illustrates the selected components of the example Class-D stage and measurement circuit of FIG. 4 including calibration resistors, in accordance with embodiments of the present disclosure;

[0019] FIG. 8 depicts a Class-D amplifier in various example phases of its switches for negative and positive output currents and the path of electrical current flow in each of the example phases, in accordance with embodiments of the present disclosure;

[0020] FIG. 9 illustrates a block and circuit diagram of selected components of an example Class-D stage and AFEs and combiner that may be used to implement measurement circuitry, in accordance with embodiments of the present disclosure; and

[0021] FIG. 10 depicts example waveforms for PWM control signals, output current generated based on the PWM control signals, and a sense voltage that may be generated based on current flowing through the sense resistors of FIG. 8 in various phases of its operation, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

[0022] FIG. 2 illustrates an example personal mobile device 11, in accordance with embodiments of the present disclosure. FIG. 2 depicts personal mobile device 11 having a speaker 17. Speaker 17 is merely an example, and it is understood that personal mobile device 11 may be used in connection with a variety of transducers including magnetic coil loudspeakers, piezo speakers, haptic feedback transducers, and others. In addition or alternatively, personal mobile device 11 may be coupled to a headset 13 in the form of a pair of earbud speakers 18A and 18B. Headset 13 depicted in FIG. 2 is merely an example, and it is understood that personal mobile device 11 may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers. A plug 14 may provide for connection of headset 13 to an electrical terminal of personal mobile device 11. Personal mobile device 11 may provide a display to a user and receive user input using a touch screen 12, or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal mobile device 11. As also shown in FIG. 2, personal mobile device 11 may include an integrated circuit (IC) 19 for generating an analog signal for transmission to speaker 17, headset 13, and/or another transducer.

[0023] FIG. 3 illustrates a block diagram of selected components of an example IC 19 of a personal mobile device for driving a transducer, in accordance with embodiments of the present disclosure. As shown in FIG. 3, a microcontroller core 28 may supply a digital input signal DIG_IN to a digital-to-analog converter (DAC) 24, which may convert the digital input signal to an analog input signal V.sub.IN. In some embodiments, analog signal V.sub.IN may comprise a pulse-width modulated signal. In addition, although analog signal V.sub.IN is shown in FIG. 3 as a single-ended signal, in some embodiments analog signal V.sub.IN may comprise a differential signal. DAC 24 may supply analog signal V.sub.IN to an amplifier 26 which may amplify or attenuate analog input signal V.sub.IN to provide a differential output signal V.sub.OUT, which may operate a speaker, a headphone transducer, a piezoelectric transducer, a haptic feedback transducer, a line level signal output, and/or other suitable output. In some embodiments, DAC 24 may be an integral component of amplifier 26, particularly in embodiments in which analog input signal V.sub.IN is a pulse-width modulated signal for driving switches of amplifier 26. In these and other embodiments, amplifier 26 may comprise a Class-D driver stage. A power supply 20 may provide the power supply rail inputs of amplifier 26.

[0024] As also depicted in FIG. 3, IC 19 may also include measurement circuitry 30. Measurement circuitry 30 may comprise any suitable system, device, or apparatus configured to receive one or more signals indicative of a physical quantity associated with amplifier 26 (e.g., an electrical current driven to a load of amplifier 26) and condition the one or more signals for further processing.

[0025] Although FIGS. 2 and 3 contemplate that IC 19 resides in a personal mobile device, systems and methods described herein may also be applied to electrical and electronic systems and devices other than a personal mobile device, including transducer systems for use in a computing device larger than a personal mobile device, such as an automobile, a building, or other structure.

[0026] FIG. 4 illustrates a block and circuit diagram of selected components of an example Class-D stage 32 and an analog front end (AFE) 30A that may be used to implement measurement circuitry 30, in accordance with embodiments of the present disclosure. In some embodiments, Class-D stage 32 may implement all or a portion of amplifier 26 described with respect to FIG. 3.

[0027] As shown in FIG. 4, Class-D stage 32 may drive output voltage V.sub.OUT to transducer 40 and include a high-side switch 42A coupled to supply voltage V.sub.SUPPLY and a low-side switch 44A coupled (via sense resistor 46A) to ground for driving a positive polarity output of Class-D stage 32. High-side switch 42A and low-side switch 44A may be controlled by complementary pulse-width modulation signals PWM.sub.P.sub.+ and PWM.sub.P.sub.−, respectively. Class-D stage 32 may also include a low-side switch 42B coupled to supply voltage V.sub.SUPPLY and a low-side switch 44B coupled (via sense resistor 46B) to ground for driving a negative polarity output of Class-D stage 32. High-side switch 42B and low-side switch 44B may be controlled by complementary pulse-width modulation signals PWM.sub.N.sub.+ and PWM.sub.N.sub.−, respectively.

[0028] In operation of Class-D stage 32, when low-side switch 44A is activated (e.g., on, closed, enabled), a sense voltage V.sub.SNS1 may form across sense resistor 46A which is negative and equal in magnitude to the product of output current I.sub.OUT through transducer 40 and resistance R.sub.SNS1 of sense resistor 46A. Likewise, when low-side switch 44B is activated (e.g., on, closed, enabled), a sense voltage V.sub.SNS2 may form across sense resistor 46B which is equal to the product of output current I.sub.OUT through transducer 40 and resistance R.sub.SNS2 of sense resistor 46B. Thus, in either case, the sense voltages V.sub.SNS1 and V.sub.SNS2 may be proportional to output current I.sub.OUT, and thus may be indicative of output current I.sub.OUT.

[0029] As shown in FIG. 4, AFE 30A may comprise a differential gain amplifier comprising an operational amplifier 52, input resistors 48, and feedback resistors 50. Thus, the differential gain amplifier may generate a differential output voltage V.sub.SNS which is an amplified version of the difference between sense voltages V.sub.SNS1 and V.sub.SNS2, the differential gain amplifier having a gain set by a ratio of resistances of feedback resistors 50 to input resistors 48. In some embodiments, AFE 30A and measurement circuitry 30 may include additional components not explicitly shown in FIG. 4, including, without limitation, filters (e.g., anti-aliasing filters), an analog-to-digital converter, and/or other components.

[0030] Current sense operation of Class-D amplifier 32 and measurement circuitry 30 may be illustrated in FIGS. 5 and 6. FIG. 5 depicts Class-D amplifier 32 in various example phases of switches 42A, 42B, 44A, and 44B for positive output current I.sub.OUT and the path of electrical current flow in each of the example phases. FIG. 6 depicts example waveforms for PWM control signals PWM.sub.P and PWM.sub.N (e.g., PWM.sub.P=PWM.sub.P.sub.+−PWM.sub.P.sub.−; PWM.sub.N=PWM.sub.N.sub.+−PWM.sub.N.sub.−), output current I.sub.OUT generated based on PWM control signals PWM.sub.P and PWM.sub.N, and sense voltage V.sub.SNS that may be generated based on current flowing through sense resistors 46A and 46B in the various phases.

[0031] In FIG. 6, the phases labeled NP may correspond to when high-switch 42A and low-side switch 44B are activated and high-side switch 42B and low-side switch 44A are deactivated, and a fully differential current flows through transducer 40 and sense resistor 46B. The phases labeled NN may correspond to when low-side switches 44A and 44B are activated and high-side switches 42A and 42B are deactivated and a common-mode current through transducer 40 flows through both sense resistors 46A and 46B. The phase labeled PP may correspond to when low-side switches 44A and 44B are deactivated and high-side switches 42A and 42B are activated and a common-mode current flows through transducer 40 but neither of sense resistors 46A and 46B.

[0032] From FIGS. 5 and 6, it is seen that current is sensed only in phases NP (which senses fully differential current) and phases NN (which senses common-mode current through low-side switches 44A and 44B) but not the common-mode current through high-side switches 42A and 42B in phase PP. Thus, the solid-line waveform for sense voltage V.sub.SNS may represent an actual output of measurement circuitry 30, while the dotted-line waveform represents an actual current. As is further seen, sense voltage V.sub.SNS in phase PP may be zero, despite the existence of non-zero current I.sub.OUT during such phase, while in phases NN, sensed voltage V.sub.SNS may represent twice the amount of the actual current I.sub.OUT. As described in greater detail below, this 2× factor of sensed voltage V.sub.SNS during phases NN may compensate for the lack of common-mode current measurement during phase PP, as to provide adequate energy balance, as the duration of phases NN and PP should be equal during operation of Class-D stage 32.

[0033] Accordingly, the topology shown in FIG. 4 may not suffer from the common-mode leakage disadvantages of existing approaches for current sensing in a Class-D stage, as the topology of FIG. 4 should experience no common-mode voltage variance at either terminal of sense resistors 46A and 46B. Further, through use of the topology of measurement circuit 30 shown in FIG. 4, the topology of Class-D stage 32 may be highly insensitive to any routing resistance mismatch to ground between sense resistors 46A and 46B.

[0034] Referring back to FIG. 6, if the phases NN and PP are matched in duration, then the 2× factor of sensed voltage V.sub.SNS during phases NN may compensate for the lack of common-mode measured energy during phases PP. However, while matching durations for phases NN and phases PP are ideal, switch drivers for switches 42A, 42B, 44A, and 44B and mismatches among switches 42A, 42B, 44A, and 44B may impose non-idealities preventing durations for phases NN and phases PP from matching. Accordingly, if the average common-mode current for phases PP is lower than the average common-mode current for phases NN, then the multiplicative factor of sensed voltage V.sub.SNS during phases NN may need to be lower than 2×. Likewise, if the average common-mode current for phases PP is higher than the average common-mode current for phases NN, then the multiplicative factor of sensed voltage V.sub.SNS during phases NN may need to be higher than 2×. Accordingly, applying calibration to sense resistors 46A and 46B may be desirable to ensure measurement accuracy and precision.

[0035] However, applying a fixed calibration on either or both of sense resistors 46A and 46B may affect measurement of fully-differential common-mode current, which may be undesirable. Therefore, as described in greater detail below, the present disclosure may implement a calibration scheme in which calibration is applied to sense resistor 46A when sense resistor 46B is in the fully-differential current path, and in which calibration is applied to sense resistor 46B when sense resistor 46A is in the fully-differential current path.

[0036] FIG. 7 illustrates the selected components of the example Class-D stage 32 and measurement circuitry 30 of FIG. 4 including calibration resistors MA and MB, in accordance with embodiments of the present disclosure. As shown in FIG. 7, calibration resistor MA may have a variable controlled resistance R.sub.CAL1 and may be coupled between an input resistor 48 and the terminal of sense resistor 46A coupled to low-side switch 42A. Similarly, calibration resistor MB may have a variable controlled resistance R.sub.CAL2 and may be coupled between an input resistor 48 and the terminal of sense resistor 46B coupled to low-side switch 42B. In operation, calibration resistor MA may be controlled by an appropriate subsystem (e.g., microcontroller core 28) to set variable resistance R.sub.CAL1 to compensate for mismatches between the durations of phases NN and PP as shown in FIG. 6. Similarly, calibration resistor MB may be controlled by an appropriate subsystem (e.g., microcontroller core 28) to set variable resistance R.sub.CAL2 to compensate for mismatches between durations of phases NN and PP similar to that shown in FIG. 6.

[0037] Although the foregoing contemplates varying resistances of calibration resistors MA and MB to compensate for mismatches between the durations of phases NN and PP, in some embodiments, in addition to or in lieu of using calibration resistors MA and MB to compensate for mismatches, feedback resistors 50 may have variable resistances (or may be fixed but in series with a variable resistor) that may be varied to compensate for mismatches between the durations of phases NN and PP.

[0038] FIG. 8 further illustrates the times at which compensation may be applied using calibration resistor 54A and the times at which compensation may be applied using calibration resistor 54B. FIG. 8 depicts Class-D amplifier 32 in various example phases of switches 42A, 42B, 44A, and 44B for both negative and positive output current I.sub.OUT and the path of electrical current flow in each of the example phases. From FIG. 8, it may be seen that for negative current I.sub.OUT, sense resistor 46A is in the fully-differential current sensing path, while sense resistor 46B is not in the fully-differential current sensing path. Accordingly, when output current I.sub.OUT is negative, compensation may be applied to sense resistor 46B by controlling variable resistance R.sub.CAL2 of calibration resistor MB to offset mismatch between the durations of NN phases and PP phases of Class-D stage 32. Similarly, when output current I.sub.OUT is positive, compensation may be applied to sense resistor 46A by controlling variable resistance R.sub.CAL1 of calibration resistor MA to offset mismatch between the durations of NN phases and PP phases of Class-D stage 32. Accordingly, alternation between calibration of calibration resistor MA and calibration of calibration resistor MB may occur at a zero-crossing of output current I.sub.OUT. In some instances, a polarity of digital input signal DIG_IN may be indicative of the polarity of output current I.sub.OUT. Accordingly, a sign bit of digital input signal DIG_IN indicating its polarity may serve as a control signal for alternating between calibration of calibration resistor MA and calibration of calibration resistor MB.

[0039] While using sense resistors 46A and 46B on a low-side of Class-D stage 32 has advantages, among the disadvantages of the approach of using only low-side sense resistors 46A and 46B are that any energy mismatches between the NN phases and the PP phases may lead to measurement error. For example, such energy mismatch may create a significant current-to-voltage gain error.

[0040] FIG. 9 illustrates a block and circuit diagram of selected components of an example Class-D stage 32 and AFEs 30A and combiner 30B that may be used to implement measurement circuitry 30, in accordance with embodiments of the present disclosure. In some embodiments, Class-D stage 32 may implement all or a portion of amplifier 26 described with respect to FIG. 3.

[0041] As shown in FIG. 9, Class-D stage 32 may drive output voltage V.sub.OUT to transducer 40 and include a high-side switch 42A coupled (via sense resistor 46C) to supply voltage V.sub.SUPPLY and a low-side switch 44A coupled (via sense resistor 46A) to ground for driving a positive polarity output of Class-D stage 32. High-side switch 42A and low-side switch 44A may be controlled by complementary pulse-width modulation signals PWM.sub.P.sub.+ and PWM.sub.P.sub.−, respectively. Class-D stage 32 may also include a low-side switch 42B coupled (via sense resistor 46D) to supply voltage V.sub.SUPPLY and a low-side switch 44B coupled (via sense resistor 46B) to ground for driving a negative polarity output of Class-D stage 32. High-side switch 42B and low-side switch 44B may be controlled by complementary pulse-width modulation signals PWM.sub.N.sub.+ and PWM.sub.N.sub.−, respectively.

[0042] In operation of Class-D stage 32, when low-side switch 44A is activated (e.g., on, closed, enabled), a sense voltage V.sub.SNS1 may form across sense resistor 46A which is negative and equal in magnitude to the product of output current I.sub.OUT through transducer 40 and resistance R.sub.SNS1 of sense resistor 46A. Likewise, when low-side switch 44B is activated (e.g., on, closed, enabled), a sense voltage V.sub.SNS2 may form across sense resistor 46B which is equal to the product of output current I.sub.OUT through transducer 40 and resistance R.sub.SNS2 of sense resistor 46B. Further, when high-side switch 42A is activated (e.g., on, closed, enabled), a sense voltage V.sub.SNS3 may form across sense resistor 46C which is negative and equal in magnitude to the product of output current I.sub.OUT through transducer 40 and resistance R.sub.SNS3 of sense resistor 46C. Moreover, when high-side switch 42B is activated (e.g., on, closed, enabled), a sense voltage V.sub.SNS4 may form across sense resistor 46D which is equal to the product of output current I.sub.OUT through transducer 40 and resistance R.sub.SNS4 of sense resistor 46D. Thus, in all of these cases, the sense voltages V.sub.SNS1, V.sub.SNS2, V.sub.SNS3, and V.sub.SNS4 may each be proportional to output current I.sub.OUT, and thus may be indicative of output current I.sub.OUT.

[0043] As shown in FIG. 9, one AFE 30A may generate a differential output voltage V.sub.SNSN which is an amplified version of the difference between sense voltages V.sub.SNS1 and V.sub.SNS2, while another AFE 30A may generate a differential output voltage V.sub.SNSP which is an amplified version of the difference between sense voltages V.sub.SNS3 and V.sub.SNS4. Thus, differential output voltage V.sub.SNSN may be proportional to the sum I.sub.NP+2I.sub.PP, where I.sub.NP is output current I.sub.OUT during NP phases and I.sub.PP is output current I.sub.OUT during PP phases. Likewise, differential output voltage V.sub.SNSP may be proportional to the sum I.sub.NP+2I.sub.NN, where I.sub.NN is output current I.sub.OUT during NN phases. Accordingly, combiner 30B may sum differential output voltage V.sub.SNSN and differential output voltage V.sub.SNSP to generate sensed voltage V.sub.SNS indicative of output current I.sub.OUT across all phases. For example, by simply summing differential output voltage V.sub.SNSN and differential output voltage V.sub.SNSP, sensed voltage V.sub.SNS may be proportional to the sum 2I.sub.NP+2I.sub.NN+2I.sub.PP, which represents two times output current I.sub.OUT across all phases. Accordingly, combiner 30B may be configured to divide the sum of differential output voltage V.sub.SNSN and differential output voltage V.sub.SNSP by a factor of two (or any other appropriate factor) in order to generate sensed voltage V.sub.SNS.

[0044] In some embodiments, measurement circuitry 30 may include additional components other than AFEs 30A and combiner 30B not explicitly shown in FIG. 9, including, without limitation, filters (e.g., anti-aliasing filters), an analog-to-digital converter, and/or other components.

[0045] FIG. 10 depicts example waveforms for PWM control signals PWM.sub.P and PWM.sub.N (e.g., PWM.sub.P=PWM.sub.P.sub.+−PWM.sub.P.sub.−; PWM.sub.N=PWM.sub.N.sub.+−PWM.sub.N.sub.−), output current I.sub.OUT generated based on PWM control signals PWM.sub.P and PWM.sub.N, differential voltage V.sub.SNSN that may be generated based on current flowing through sensor resistors 46A and 46B in the various phases, differential voltage V.sub.SNSP that may be generated based on current flowing through sensor resistors 46C and 46D in the various phases, and sensed voltage V.sub.SNS that may be generated by the summation of differential voltage V.sub.SNSN and differential voltage V.sub.SNSP as described above (e.g., by combiner 30B).

[0046] As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

[0047] This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

[0048] Although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above.

[0049] Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale.

[0050] All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.

[0051] Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description.

[0052] To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.