Abstract
A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.
Claims
1. A marching memory, comprising: an array of memory units deployed along a row direction, each memory unit having a sequence of bit-level cells aligned in a column direction perpendicular to the row direction, configured to operate with a power supplied by a single clock signal supply line, each bit-level cell having: a transfer-transistor having a first main-electrode connected to the clock signal supply line serving as an oscillating power supply line through a first R-C delay element, which makes a first exponential transient response, potentials of the power supply line swinging periodically between the logical levels of “0” and “1”, a second main-electrode opposing to the first main-electrode, and a control-electrode configured to control a current flowing between the first and the second-main electrodes, connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units along the row direction, through a second R-C delay element, which makes a second exponential transient response; a reset-transistor having a first main-electrode connected to the second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential; and a capacitor configured to store signal charge as information of the bit-level cell, connected in parallel with the reset-transistor, wherein an output node connecting the second main-electrode of the transfer-transistor and the first main-electrode of the reset-transistor serves as an output terminal of the bit-level cell, and the output terminal of the bit-level cell delivers the signal charge stored in the capacitor to a second neighboring bit-level cell disposed at output side of the array of the memory units along the row direction.
2. The marching memory of claim 1, wherein in each of the bit-level cells, when a clock signal is applied to the control-electrode of the reset-transistor, the reset-transistor discharges the signal charge stored in the capacitor.
3. The marching memory of claim 1, wherein in each of the bit-level cells, after the signal charge stored in the capacitor has been discharged, the transfer-transistor becomes active delayed by a first delay time determined by the first R-C delay element, and when the signal charge stored in the first neighboring bit-level cell is fed to the control-electrode of the transfer-transistor, the transfer-transistor transfers the signal charge stored in the first neighboring bit-level cell, further delayed by a second delay time determined by the second R-C delay element to the capacitor.
4. The marching memory of claim 3, wherein the first delay time is a quarter of clock period of the clock signal, and the second delay time is a half of the clock period.
5. The marching memory of claim 1, wherein in the transfer-transistor, the control-electrode controls the current flowing between the first main-electrode and the second main-electrode electro-statically.
6. The marching memory of claim 1, wherein in the reset-transistor, the control-electrode controls the current flowing between the first main-electrode and the second main-electrode electro-statically.
7. The marching memory of claim 1, wherein the transfer-transistor and the reset-transistor are made of an insulated-gate transistor, including a MOS transistor, a MIS transistor and a high electron mobility transistor.
8. The marching memory of claim 7, wherein the transfer-transistor and the reset-transistor are made of a nMOS transistor, and the clock signal of positively high-level is applied to the control electrode of the nMOS transistor to achieve a conductive state.
9. The marching memory of claim 7, wherein the transfer-transistor and the reset-transistor are made of a pMOS transistor, and the clock signal of negatively high-level is applied to the control electrode of the pMOS transistor to achieve a conductive state.
10. A complex marching memory, comprising: a plurality of marching memory blocks being deployed spatially in a two dimensional matrix such that each horizontal array of the marching memory blocks shares a common horizontal-core line, while each vertical array of marching memory blocks shares a common vertical-core line, each of the marching memory blocks including an array of memory units deployed along a row direction in each of the marching memory blocks, each of the memory units having a sequence of bit-level cells aligned in a column direction perpendicular to the row direction for storing information of byte size or word size defined in the column direction, wherein each of the bit-level cells operates with a power supplied by a single clock signal supply line, and each of the memory units transfers synchronously with a clock signal, step by step, toward an output side of a corresponding marching memory block from an input side of the corresponding marching memory block, and each of the marching memory blocks is randomly accessed at a desired intersection of the horizontal-core line and the vertical-core line.
11. The complex marching memory of claim 10, wherein each of the bit-level cells comprises: a transfer-transistor having a first main-electrode connected to a clock signal supply line, configured to supply the clock signal through a first R-C delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell disposed at input side of the array of memory units along the row direction, through a second R-C delay element; a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential; and a capacitor configured to store a signal charge as information of the bit-level cell, connected in parallel with the reset-transistor, wherein an output node connecting the second main-electrode of the transfer-transistor and the first main-electrode of the reset-transistor serves as an output terminal of the bit-level cell, and the output terminal of the bit-level cell delivers the signal charge stored in the capacitor to a second neighboring bit-level cell disposed at output side of the array of memory units along the row direction.
12. The complex marching memory of claim 11, wherein in each of the bit-level cells, when the clock signal is applied to the control-electrode of the reset-transistor, the reset-transistor discharges the signal charge stored in the capacitor.
13. The complex marching memory of claim 11, wherein in each of the bit-level cells, after the signal charge stored in the capacitor has been discharged, the transfer-transistor becomes active delayed by a first delay time determined by the first delay element, and when the signal charge stored in the first neighboring bit-level cell is fed to the control-electrode of the transfer-transistor, the transfer-transistor transfers the signal charge stored in the first neighboring bit-level cell, further delayed by a second delay time determined by the second delay element to the capacitor.
14. A complex marching memory, comprising: a plurality of marching memory blocks being deployed spatially in a two dimensional matrix such that each horizontal array of the marching memory blocks shares a common horizontal-core line, while each vertical array of marching memory blocks shares a common vertical-core line, each of the marching memory blocks including an array of memory units deployed along a row direction in each of the marching memory blocks, each of the memory units having a sequence of bit-level cells aligned in a column direction perpendicular to the row direction for storing information of byte size or word size defined in the column direction, wherein each of the bit-level cells operates with a power supplied by a single clock signal supply line, and each of the memory units transfers synchronously with a first clock signal, step by step, toward a first edge side of corresponding marching memory block from a second edge side of the corresponding marching memory block opposing to the first edge side, and further, each of the memory units transfers synchronously with a second clock signal, step by step, toward the second edge side from the first edge side, and each of the marching memory blocks is randomly accessed at a desired intersection of the horizontal-core line and the vertical-core line.
15. A computer system, comprising a processor; and a marching main memory, configured to provide the processor with stored information actively and sequentially so that the processor can execute arithmetic and logic operations with the stored information, in addition results of processing in the processor are sent out to the marching main memory, except that in case of instructions movement, there is only one way of instructions flow from the marching main memory to the processor, the marching main memory includes an array of memory units deployed along a row direction, each of the memory units having a sequence of bit-level cells aligned in a column direction perpendicular to the row direction, configured to operate with a power supplied by a single clock signal supply line, each of the bit-level cells comprising: a transfer-transistor having a first main-electrode connected to the clock signal supply line serving as an oscillating power supply line through a first R-C delay element, which makes a first exponential transient response, potentials of the power supply line swinging periodically between the logical levels of “0” and “1”, a second main-electrode opposing to the first main-electrode, and a control-electrode configured to control a current flowing between the first and the second-main electrodes, connected to an output terminal of a first neighboring bit-level cell disposed at input side of the array of the memory units along the row direction through a second R-C delay element, which makes a second exponential transient response; a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential; and a capacitor configured to store a signal charge as information of the bit-level cell, connected in parallel with the reset-transistor; wherein an output node connecting the second main-electrode of the transfer-transistor and the first main-electrode of the reset-transistor serves as an output terminal of the bit-level cell, and the output terminal of the bit-level cell delivers the signal charge stored in the capacitor to a second neighboring bit-level cell disposed at output side of the array of the memory units along the row direction.
16. A computer system, comprising: a processor; and a marching main memory configured to provide the processor with stored information actively and sequentially so that the processor can execute arithmetic and logic operations with the stored information, in addition results of processing in the processor are sent out to the marching main memory, except that in case of instructions movement, there is only one way of instructions flow from the marching main memory to the processor, the marching main memory comprising a plurality of marching memory blocks being deployed spatially in a two dimensional matrix such that each horizontal array of the marching memory blocks shares a common horizontal-core line, while each vertical array of marching memory blocks shares a common vertical-core line, each of the marching memory blocks having an array of memory units deployed along a row direction, each of the memory units having a sequence of bit-level cells aligned in a column direction perpendicular to the row direction so as to store information of byte size or word size defined in the column direction, wherein each of the bit-level cells operates with a power supplied by a single clock signal supply line, and each of the marching memory blocks is randomly accessed at a desired intersection of the horizontal-core line and the vertical-core line.
17. The computer system of claim 16, wherein each of the bit-level cells comprises: a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first R-C delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell disposed at input side of the array of memory units along the row direction through a second R-C delay element; a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential; and a capacitor configured to store a signal charge as information of the bit-level cell and connected in parallel with the reset-transistor, wherein an output node connecting the second main-electrode of the transfer-transistor and the first main-electrode of the reset-transistor serves as an output terminal of the bit-level cell, and the output terminal of the bit-level cell delivers the signal charge stored in the capacitor to a second neighboring bit-level cell disposed at output side of the array of memory units along the row direction.
18. A computer system, comprising: a processor; and a bidirectional marching main memory configured to provide the processor with stored information actively and sequentially so that the processor can execute arithmetic and logic operations with the stored information, in addition results of processing in the processor are sent out to the bidirectional marching main memory, except that in case of instructions movement, there is only one way of instructions flow from the bidirectional marching main memory to the processor, the bidirectional marching main memory comprising a plurality of bidirectional marching memory blocks being deployed spatially in a two dimensional matrix such that each horizontal array of the marching memory blocks shares a common horizontal-core line, while each vertical array of marching memory blocks shares a common vertical-core line, each of the bidirectional marching memory blocks having an array of memory units deployed along a row direction in each of the bidirectional marching memory blocks, each of the memory units having a sequence of bit-level cells arranged in a column direction perpendicular to the row direction so as to store information of byte size or word size defined in the column direction, wherein each of the memory units transfers synchronously with a first clock signal, step by step, toward a first edge side of corresponding marching memory block from a second edge side of the corresponding marching memory block opposing to the first edge side, and further, each of the memory units transfers synchronously with a second clock signal, step by step, toward the second edge side from the first edge side, and each of the marching memory blocks is randomly accessed at a desired intersection of the horizontal-core line and the vertical-core line.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The invention will now be described by way of example, with reference to the accompanying figures, of which:
(2) FIG. 1 is a schematic block diagram of an organization of a conventional computer system;
(3) FIG. 2 is a schematic block diagram of a fundamental organization of a computer system according to the present invention;
(4) FIG. 3 is a block diagram of an array of memory units implementing a marching main memory and a transfer of information in the marching main memory in the computer system shown in FIG. 2;
(5) FIG. 4 is a transistor-level schematic view of the cell-array in the marching main memory;
(6) FIG. 5 is an enlarged transistor-level schematic view of the cell-array in the marching main memory having four neighboring bit-level cells;
(7) FIG. 6 is an enlarged transistor-level schematic view of a single bit-level cell in the marching main memory;
(8) FIG. 7A is a graph of the response of the transistor to the waveform of a clock signal where a signal “1” is transferred from the previous stage;
(9) FIG. 7B is a graph of the response of the transistor to the waveform of the clock signal where a signal “0” is transferred from the previous stage;
(10) FIG. 7C is a graph of the responses of the transistors to the waveform of a clock signal;
(11) FIG. 8 is schematic view a bit-level cell used in the marching main memory;
(12) FIG. 9 is a plan view of the bit-level cell shown in FIG. 8;
(13) FIG. 10 is a cross-sectional view of the bit-level cell shown in FIG. 9, taken on line A-A;
(14) FIG. 11 is a transistor-level schematic view of the single bit-level cell in combination with an inter-unit cell of the marching main memory;
(15) FIG. 12 is a plan view of the bit-level cell in FIG. 11;
(16) FIG. 13 is a transistor-level schematic view of two neighboring bit-level cells in the cell-array in combination with corresponding inter-unit cells in the marching main memory;
(17) FIG. 14(a) is a timing diagram of a response of the bit-level cell of FIG. 13, and FIG. 14(b) is a next timing diagram of a next response of the next bit-level cell of FIG. 13 to a waveform of a clock signal.
(18) FIG. 15 is a graph of the responses of the transistors to the waveform of a clock signal applied to the marching main memory;
(19) FIGS. 16(a)-(d) are schematic views of four modes of signal-transferring operations of the bit-level cells in FIGS. 11 and 13;
(20) FIG. 17 is a transistor-level schematic view of the single bit-level cell in combination with an inter-unit cell adapted for a marching main memory;
(21) FIG. 18 is a transistor-level schematic view of two neighboring bit-level cells of the cell-array in combination with corresponding inter-unit cells in the marching main memory;
(22) FIG. 19 is a transistor-level schematic view of the single bit-level cell in combination with an inter-unit cell adapted for a marching main memory;
(23) FIG. 20 is a transistor-level schematic view of two neighboring bit-level cells having a cell-array in combination with corresponding inter-unit cells in the marching main memory cells;
(24) FIG. 21 is a diagram of the responses of the transistors to the waveform of a clock signal applied to the marching main memory;
(25) FIGS. 22(a)-(d) is a schematic view of four modes of signal-transferring operations of the bit-level cell shown in FIGS. 20 and 21;
(26) FIG. 23 is a schematic view of gate-level representation of the cell-array shown in FIG. 4;
(27) FIG. 24 is an array of memory units implementing a reverse directional marching main memory having a reverse directional transfer of information;
(28) FIG. 25(a) is a transistor-level schematic view of a circuit configuration of a cell array implementing i-th row of the reverse directional marching main memory shown in FIG. 24, and FIG. 25(b) is a diagram of the response of the transistor to the waveform of a clock signal applied to the reverse directional marching main memory shown in FIG. 24;
(29) FIG. 26 is a gate-level schematic view of the cell-array implementing i-th row in the reverse directional marching main memory shown in FIG. 25(a);
(30) FIG. 27 is a diagram of a time-domain relationship between the memory unit streaming time in a marching main memory and the clock cycle in a processor (CPU);
(31) FIG. 28 is block diagram of an organization of the computer system in which the memory bottleneck is eliminated between the processor (CPU) and the marching memory structure, including the marching main memory;
(32) FIG. 29(a) is a diagram of a forward data stream flowing from the marching memory structure to the processor (CPU) and backward data stream flowing from the processor (CPU) to the marching memory structure, and FIG. 29(b) is a diagram of bandwidths established between the marching memory structure and the processor (CPU) under an ideal condition where the memory unit streaming time of the marching memory structure is equal to the clock cycle of the processor (CPU);
(33) FIG. 30(a) is a schematic view of an extremely high-speed magnetic tape system; FIG. 30(b) is a schematic view of the computer system in FIG. 2 compared with the tape system in FIG. 30(b);
(34) FIG. 31(a) is a block diagram of a forward marching behavior of information marching (shifts) side by side toward right-hand direction in a one-dimensional marching main memory;
(35) FIG. 31(b) is a block diagram of the one-dimensional marching main memory in a staying state;
(36) FIG. 31(c) is a block diagram of a reverse-marching behavior of information marching (shifts) side by side toward left-hand direction in the one-dimensional marching main memory;
(37) FIG. 32 is a transistor-level schematic view of a one-dimensional marching main memory circuit having the bidirectional transferring behavior show in FIGS. 31(a)-(c) to store and transfer bi-directionally instructions or scalar data;
(38) FIG. 33 is a transistor-level schematic view of a one-dimensional marching main memory circuit having isolation transistors between memory units to achieve the bidirectional transferring behavior shown in FIGS. 31(a)-(c);
(39) FIG. 34 is a schematic view of a gate-level circuit design of the one-dimensional marching main memory shown in FIG. 32;
(40) FIG. 35(a) is a block diagram of a bidirectional transferring mode of instructions in a one-dimensional marching main memory adjacent to a processor;
(41) FIG. 35(b) is a block diagram of a bidirectional transferring mode of scalar data in a one-dimensional marching main memory adjacent to an ALU;
(42) FIG. 35(c) is a block diagram of a uni-directional transferring mode of vector/streaming data in a one-dimensional marching main memory adjacent to a pipeline;
(43) FIG. 36(a) is a schematic diagram of an inner configuration of existing memory;
(44) FIG. 36(b) is a schematic diagram of an inner configuration of present one-dimensional marching main memory where the positioning of individual memory unit identifies the starting point and ending point of a set of successive memory units in vector/streaming data;
(45) FIG. 37(a) is a schematic diagram of an inner configuration of present one-dimensional marching main memory where the positioning of individual memory unit identifies the starting point and ending point of a set of successive memory units in vector instruction,
(46) FIG. 37(b) is a schematic diagram of an inner configuration of present one-dimensional marching main memory for scalar data.
(47) FIG. 37(c) is a schematic diagram of an inner configuration of present one-dimensional marching main memory where position indexes identify the starting point and ending point of a set of successive memory units in vector/streaming data;
(48) FIG. 38(a) is a schematic view of present marching main memory having a plurality of pages for vector/streaming data case;
(49) FIG. 38(b) is a schematic view of one of the pages in FIG. 38(a);
(50) FIG. 38(c) is a schematic view of one of the files implemented by a plurality of memory units for vector/streaming data case;
(51) FIG. 39(a) is a schematic view of present marching main memory having a plurality of pages for its own position index as an address;
(52) FIG. 39(b) is a schematic view of one of the pages in FIG. 39(a);
(53) FIG. 39(c) is a schematic view of one of the files and the driving positions of the file implemented by a plurality of memory units for programs/scalar data case;
(54) FIG. 40(a) is a diagram of the speed/capability of the existing memory compared with the marching main memory;
(55) FIG. 40(b) is a diagram of the speed/capability of the marching main memory compared with the existing memory shown in FIG. 40(a);
(56) FIG. 41(a) is a diagram of the speed/capability of a worst case of the existing memory for scalar instructions compared with the marching main memory;
(57) FIG. 41(b) is a diagram of the speed/capability of the marching main memory compared with the worst case of the existing memory shown in FIG. 41(a);
(58) FIG. 42(a) is a diagram of the speed/capability the existing memory for scalar instructions compared with the marching main memory;
(59) FIG. 42(b) is a diagram of the speed/capability of the marching main memory compared with the existing memory in FIG. 42(a);
(60) FIG. 43(a) is a diagram of the speed/capability of the existing memory for scalar data case compared with the marching main memory;
(61) FIG. 43(b) is a diagram of the speed/capability of the marching main memory compared with the existing memory in FIG. 43(a);
(62) FIG. 44(a) is a diagram of the speed/capability of a best case of the existing memory for streaming data and data parallel case compared with the marching main memory;
(63) FIG. 44(b) is a diagram of the speed/capability of the marching main memory compared with the best case of the existing memory shown in FIG. 44(a);
(64) FIG. 45 is a block diagram of an array of two-dimensional memory units implementing a marching main memory;
(65) FIG. 46 is a block diagram of the array of two-dimensional memory units storing and transferring data or instructions while implementing the marching main memory;
(66) FIG. 47 is another block diagram of the array of two-dimensional memory units storing and transferring data or instructions while implementing the marching main memory;
(67) FIG. 48 is another block diagram of the array of two-dimensional memory units storing and transferring data or instructions while implementing the marching main memory;
(68) FIG. 49 is a block diagram of the array of two-dimensional memory units storing and transferring data or instructions while implementing the marching main memory;
(69) FIG. 50 is a block diagram of the array of two-dimensional memory units storing and transferring data or instructions while implementing the marching main memory;
(70) FIG. 51 is another block diagram of the array of two-dimensional memory units storing and transferring data or instructions while implementing the marching main memory;
(71) FIG. 52(a) is a diagram of a device's level of energy consumption in current microprocessors separated into static and dynamic energy consumptions;
(72) FIG. 52(b) is a diagram of a net and overhead of the power consumption in the energy consumption shown in FIG. 52(a);
(73) FIG. 52(c) is a diagram of a net energy consumption in the current microprocessors;
(74) FIG. 53 is a pie diagram of actual energy consumption distribution over a processor;
(75) FIG. 54(a) is a diagram of energy consumption in conventional cache-based architecture separated into static and dynamic energy consumptions;
(76) FIG. 54(b) is a diagram of energy consumption in a computer system with the marching cache memory separated into static and dynamic energy consumption;
(77) FIG. 55 is a schematic block diagram of an organization of a computer system;
(78) FIG. 56 shows a schematic block diagram illustrating an organization of a computer system according to the present invention;
(79) FIG. 57(a) is a schematic block diagram of a combination of arithmetic pipelines and marching register;
(80) FIG. 57(b) is a block diagram of an array of marching cache units;
(81) FIG. 58 is a schematic block diagram of a computer system having a single processor core, a marching-cache memory and a marching-register file;
(82) FIG. 59 is a schematic block diagram of a computer system having a single arithmetic pipeline, a marching-cache memory and a marching-vector register;
(83) FIG. 60 is a schematic block diagram of a computer system having a plurality of processor cores, a marching-cache memory and a marching-register file;
(84) FIG. 61 is a schematic block diagram of a computer system having a plurality of arithmetic pipelines, a marching-cache memory and a marching-vector register file;
(85) FIG. 62(a) is a schematic block diagram of a conventional computer system having a plurality of arithmetic pipelines, a plurality of conventional cache memories, a plurality of conventional-vector register files (RFs) and a conventional main memory, and having a bottleneck;
(86) FIG. 62(b) is a schematic block diagram of a computer system having a plurality of arithmetic pipelines, a plurality of marching cache memories, a plurality of marching-vector register files and a marching main memory, but without a bottleneck;
(87) FIG. 63 is a schematic block diagram of a high performance computing (HPC) system according to the present invention;
(88) FIG. 64 is a schematic block diagram of a computer system according to the present invention;
(89) FIG. 65(a) is a cross-sectional view of a three-dimensional marching main memory;
(90) FIG. 65(b) is a cross-sectional view of a three-dimensional marching-cache;
(91) FIG. 65(c) is a cross-sectional view of a three-dimensional marching-register file;
(92) FIG. 66 is a perspective view of a three-dimensional representation of the computer system in FIG. 64;
(93) FIG. 67 is a perspective view of another three-dimensional representation of the computer system in FIG. 64;
(94) FIG. 68 is a cross-sectional view of the three-dimensional representation in FIG. 67;
(95) FIG. 69 is a cross-sectional view of the three-dimensional representation of the computer system in FIG. 64;
(96) FIG. 70 is a cross-sectional schematic view of the three-dimensional representation of control paths;
(97) FIG. 71 is a cross-sectional schematic view of the three-dimensional representation of data-paths for scalar data;
(98) FIG. 72 is a cross-sectional schematic view of the three-dimensional representation of data-paths for vector/streaming data;
(99) FIG. 73 is a cross-sectional schematic view of the three-dimensional representation of the combination of the scalar data-path and the control path;
(100) FIG. 74 is a cross-sectional schematic view of a bit-level parallel processing of scalar/vector data in MISD architecture;
(101) FIG. 75 is a schematic diagram of parallel processing of vector data in SIMD architecture;
(102) FIG. 76 is a schematic diagram of conventional chaining in vector processing;
(103) FIG. 77 is a schematic diagram of parallel processing of scalar/vector data in MISD architecture;
(104) FIG. 78 is a schematic diagram of parallel processing of scalar/vector data in MISD architecture;
(105) FIG. 79(a) is a plan view of conventional DRAM on a single semiconductor chip;
(106) FIG. 79(b) is a corresponding plan view of an inner layout of a complex marching memory, which is on the same single semiconductor chip of the conventional DRAM in FIG. 79(a);
(107) FIG. 80(a) is a schematic diagram of an outer shape of a single marching memory block, FIG. 80(b) is a partial plan view of the marching memory block shown in FIG. 80(a), which has one thousand columns, where the marching memory's access time (cycle time) is defined to a single column, and FIG. 80(c) is a schematic diagram of the conventional DRAM's memory cycle for writing in or reading out the content of the conventional DRAM's one memory element; and
(108) FIG. 81 shows a schematic plan view of a complex marching memory module.
DETAILED DESCRIPTION
(109) Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. Generally, as is conventional in the representation of semiconductor devices, it will be appreciated that the various drawings are not drawn to scale from one figure to another, nor inside a given figure, and in particular, that the layer thicknesses are arbitrarily drawn for facilitating the reading of the drawings. In the following description specific details are set forth, such as specific materials, processes and equipment in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known manufacturing materials, processes and equipment are not set forth in detail in order to prevent unnecessary obscuring of the present invention. Prepositions, such as “on”, “over”, “under”, “beneath”, and “normal” are defined with respect to a planar surface of the substrate, regardless of the orientation in which the substrate is actually held. A layer is on another layer even if there are intervening layers.
(110) Although nMOS transistors are shown as transfer-transistors and reset-transistors in transistor-level representations of bit-level cells in FIGS. 4, 5, 6, 8, 11, 13, 16-20, 22, 25 and 32, etc., pMOS transistors can be used as the transfer-transistors and the reset-transistors, if the opposite polarity of the clock signal is employed.
Fundamental Organization of Computer System
(111) As shown in FIG. 2, a computer system pertaining to an exemplary embodiment of the present invention encompasses a processor 11 and a marching main memory 31. The processor 11 includes a control unit 111 having a clock generator 113 that generates a clock signal, and an arithmetic logic unit (ALU) 112 that executes arithmetic and logic operations synchronized with the clock signal. As shown in FIG. 3, the marching main memory 31 encompasses an array of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, each of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n having a unit of information including word size of data or instructions, input terminals of the array and output terminals of the array. As shown in FIG. 3, the marching main memory 31 stores the information in each of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n and transfers the information synchronously with the clock signal, step by step, toward the output terminals, so as to provide the processor 11 with the stored information actively and sequentially so that the ALU 112 can execute the arithmetic and logic operations with the stored information.
(112) As shown in FIG. 2, the marching main memory 31 and the processor 11 are electrically connected by a plurality of joint members 54. Each of joint members 54 may be include a first terminal pin attached to the marching main memory 31, a second terminal pin attached to the processor 11, and an electrical conductive bump interposed between the first and second terminal pins. The material of the electrical conductive bumps, solder balls includes gold (Au) bumps, silver (Ag) bumps, copper (Cu) bumps, nickel-gold (Ni—Au) alloy bumps or nickel-gold-indium (Ni—Au—In) alloy bumps or other common electrically conductive material. The resultant data of the processing in the ALU 112 are sent out to the marching main memory 31 through the joint members 54. Therefore, as represented by bidirectional arrow PHI.sub.12 (Φ.sub.12), data are transferred bi-directionally between the marching main memory 31 and the processor 11 through the joint members 54. On the contrary, as represented by uni-directional arrow ETA.sub.11 (η.sub.11), as to the instructions movement, there is only one way of instruction-flow from the marching main memory 31 to the processor 11.
(113) As shown in FIG. 2, the organization of the computer system further includes an external secondary memory 41 such as disk, an input unit 61, an output unit 62 and input/output (I/O) interface circuit 63. Similar to a conventional von Neumann computer, the signals or data are received by the input unit 61, and the signals or data are sent from the output unit 62. For example, the input unit 61 may include known keyboards and known mice, and the output unit 62 may include known monitors and printers. Known devices for communication between computers, such as modems and network cards, typically serve for both the input unit 61 and the output unit 62. Note that the designation of a device as either the input unit 61 or the output unit 62 depends on the perspective. The input unit 61 takes as input physical movement that the human user provides and converts it into signals that the computer system can understand. For example, the input unit 61 converts incoming data and instructions into a pattern of electrical signals in binary code, and the output from the input unit 61 is fed to the marching main memory 31 through the I/O interface circuit 63. The output unit 62 takes input signals that the marching main memory 31 provides through the I/O interface circuit 63. The output unit 62 then converts these signals into representations that human users can see or read, reversing the process of the input unit 61 by translating the digitized signals into a form intelligible to the user. The I/O interface circuit 63 is required whenever the processor 11 drives the input unit 61 and the output unit 62. The processor 11 can communicate with the input unit 61 and the output unit 62 through the I/O interface circuit 63. If in the case of different data formatted being exchanged, the I/O interface circuit 63 converts serial data to parallel form and vice-versa. There is provision for generating interrupts and the corresponding type numbers for further processing by the processor 11 if required.
(114) The secondary memory 41 stores data and information on a more long-term basis than the marching main memory 31. While the marching main memory 31 is concerned mainly with storing programs currently executing and data currently being employed, the secondary memory 41 is generally intended for storing anything that needs to be kept even if the computer is switched off or no programs are currently executing. Examples of the secondary memory 41 include known hard disks (or hard drives) and known external media drives (such as CD-ROM drives). These storage methods are most commonly used to store the computer's operating system, the user's collection of software and any other data the user wishes. While the hard drive is used to store data and software on a semi-permanent basis and the external media drives are used to hold other data, this setup varies wildly depending on the different forms of storage available and the convenience of using each. As represented by bidirectional arrow PHI.sub.1 (Φ.sub.1), data are transferred bi-directionally between the secondary memory 41 and the marching main memory 31 and the processor 11 through existing wire connection 53.
(115) Although the illustration is omitted, in the computer system of the exemplary embodiment shown in FIG. 2, the processor 11 may includes a plurality of arithmetic pipelines configured to receive the stored information through the output terminals from the marching main memory 31, and as represented by bidirectional arrow PHI.sub.12, data are transferred bi-directionally between the marching main memory 31 and the plurality of arithmetic pipelines through the joint members 54.
(116) In the computer system of the exemplary embodiment shown in FIG. 2, there are no buses consisting of the data bus and address bus because the whole computer system has no global wires, even in any data exchange between the processor 11 and the marching main memory 31. The advantage of this computer system over conventional computer systems is that the bottleneck is eliminated by eliminating the use of global wires and buses. The computer system in FIG. 2 only uses short local wires within the marching main memory 31 or connecting portions of the marching main memory 31 with a corresponding ALU 112. As there are no global wires, which generate time delay and stray capacitances between these wires, the computer system of the exemplary embodiment can achieve much higher processing speed and lower power consumption.
Cell Array for the Marching Main Memory
(117) In most conventional computers, the unit of address resolution is either a character (e.g. a byte) or a word. If the unit is a word, then a larger amount of memory can be accessed using an address of a given size. On the other hand, if the unit is a byte, then individual characters can be addressed (i.e. selected during the memory operation). Machine instructions are normally fractions or multiples of the architecture's word size. This is a natural choice since instructions and data usually share the same memory subsystem. FIGS. 4 and 5 correspond to transistor-level representations of the cell array implementing the marching main memory 31 shown in FIG. 3, and FIG. 23 corresponds to a gate-level representation of the cell array implementing marching main memory 31 shown in FIG. 3.
(118) In FIG. 4, the first column of the m*n matrix, which is implemented by a vertical array of cell M.sub.11, M.sub.21, M.sub.31, . . . , M.sub.m−1,1, M.sub.m1, represents the first memory unit U.sub.1 shown in FIG. 3. Here, “m” is an integer determined by word size. Although the choice of a word size is of substantial importance, when computer architecture is designed, word sizes are naturally multiples of eight bits, with 16, 32, and 64 bits being commonly used. Similarly, the second column of the m*n matrix, which is implemented by a vertical array of cell M.sub.12, M.sub.22, M.sub.32, . . . , M.sub.m−1,2, M.sub.m2, represents the second memory unit U.sub.2, the third column of the m*n matrix, which is implemented by a vertical array of cell M.sub.13, M.sub.23, M.sub.33, . . . , M.sub.m−1,3, M.sub.m3, represents the third memory unit U.sub.3, . . . , the (n−1)-th column of the m*n matrix, which is implemented by a vertical array of cell M.sub.1, n−1, M.sub.2, n−1, M.sub.3, n−1, . . . M.sub.m−1,n−1, M.sub.m,n−1, represents the (n−1)-th memory unit U.sub.n−1, and the n-th column of the m*n matrix, which is implemented by a vertical array of cell M.sub.1, n, M.sub.2, n, M.sub.3, n, . . . , M.sub.m−1, n, M.sub.m,n, represents the n-th memory unit U.sub.n.
(119) As shown in FIG. 4, the first memory unit U.sub.1 of word-size level is implemented by a vertical array of bit-level cell M.sub.11, M.sub.21, M.sub.31, . . . , M.sub.m−1,1, M.sub.m1 in the first column of the m*n matrix. The first-column cell M.sub.11 on the first row encompasses a first nMOS transistor Q.sub.111 having a drain electrode connected to a clock signal supply line through a first delay element D in and a gate electrode connected to the output terminal of a first bit-level input terminal through a second delay element D.sub.112; a second nMOS transistor Q.sub.112 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.111, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.11 configured to store the information of the cell M.sub.11, connected in parallel with the second nMOS transistor Q.sub.112, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.111 and the drain electrode of the second nMOS transistor Q.sub.112 serves as an output terminal of the cell M.sub.11, configured to deliver the signal stored in the capacitor C.sub.11 to the next bit-level cell M.sub.12. The first-column cell M.sub.21 on the second row encompasses a first nMOS transistor Q.sub.211 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.211 and a gate electrode connected to the output terminal of a second bit-level input terminal through a second delay element D.sub.212; a second nMOS transistor Q.sub.212 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.211, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.21 configured to store the information of the cell M.sub.21, connected in parallel with the second nMOS transistor Q.sub.212, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.211 and the drain electrode of the second nMOS transistor Q.sub.212 serves as an output terminal of the cell M.sub.21, configured to deliver the signal stored in the capacitor C.sub.21 to the next bit-level cell M.sub.22. The first-column cell M.sub.31 on the third row encompasses a first nMOS transistor Q.sub.311 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.311 and a gate electrode connected to the output terminal of a third bit-level input terminal through a second delay element D.sub.312; a second nMOS transistor Q.sub.312 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.311, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.31 configured to store the information of the cell M.sub.31, connected in parallel with the second nMOS transistor Q.sub.312, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.311 and the drain electrode of the second nMOS transistor Q.sub.312 serves as an output terminal of the cell M.sub.31, configured to deliver the signal stored in the capacitor C.sub.31 to the next bit-level cell M.sub.31 . . . . The first-column cell M.sub.(m−1)1 on the (m−1)-th row encompasses a first nMOS transistor Q.sub.(m−1)11 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.(m−1)11 and a gate electrode connected to the output terminal of a (m−1)-th bit-level input terminal through a second delay element D.sub.(m−1)12; a second nMOS transistor Q.sub.(m−1)12 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.(m−1)11, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.(m−1)1 configured to store the information of the cell M.sub.(m−1)1, connected in parallel with the second nMOS transistor Q.sub.(m−1)12, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.(m−1)11 and the drain electrode of the second nMOS transistor Q.sub.(m−1)12 serves as an output terminal of the cell M.sub.(n−1)1, configured to deliver the signal stored in the capacitor C.sub.(m−1)1 to the next bit-level cell M.sub.(m−1)12. The first-column cell M.sub.m1 on the m-th row encompasses a first nMOS transistor Q.sub.m11 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.m11 and a gate electrode connected to the output terminal of a m-th bit-level input terminal through a second delay element D.sub.m12; a second nMOS transistor Q.sub.m12 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.m11, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.m1 configured to store the information of the cell M.sub.m1, connected in parallel with the second nMOS transistor Q.sub.m12, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.m11 and the drain electrode of the second nMOS transistor Q.sub.m12 serves as an output terminal of the cell M.sub.m1, configured to deliver the signal stored in the capacitor C.sub.m1 to the next bit-level cell M.sub.m2.
(120) As shown in FIG. 4, the second memory unit U.sub.2 of word-size level is implemented by a vertical array of bit-level cell M.sub.12, M.sub.22, M.sub.32, . . . , M.sub.m−1,2, M.sub.m2 in the second column of the m*n matrix. The second column cell M.sub.12 on the first row encompasses a first nMOS transistor Q.sub.121 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.121 and a gate electrode connected to the output terminal of the previous bit-level cell Mu through a second delay element D.sub.122; a second nMOS transistor Q.sub.122 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.121, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.12 configured to store the information of the cell M.sub.12, connected in parallel with the second nMOS transistor Q.sub.122, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.121 and the drain electrode of the second nMOS transistor Q.sub.122 serves as an output terminal of the cell M.sub.12, configured to deliver the signal stored in the capacitor C.sub.12 to the next bit-level cell M.sub.13. The second column cell M.sub.22 on the second row encompasses a first nMOS transistor Q.sub.221 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.221 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.21 through a second delay element D.sub.222; a second nMOS transistor Q.sub.222 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.221, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.22 configured to store the information of the cell M.sub.22, connected in parallel with the second nMOS transistor Q.sub.222, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.221 and the drain electrode of the second nMOS transistor Q.sub.222 serves as an output terminal of the cell M.sub.22, configured to deliver the signal stored in the capacitor C.sub.22 to the next bit-level cell M.sub.23. The second column cell M.sub.32 on the third row encompasses a first nMOS transistor Q.sub.321 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.321 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.31 through a second delay element D.sub.322; a second nMOS transistor Q.sub.322 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.321, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.32 configured to store the information of the cell M.sub.32, connected in parallel with the second nMOS transistor Q.sub.322, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.321 and the drain electrode of the second nMOS transistor Q.sub.322 serves as an output terminal of the cell M.sub.32, configured to deliver the signal stored in the capacitor C.sub.32 to the next bit-level cell M.sub.33 . . . . The second column cell M.sub.(n−1)2 on the (m−1)-th row encompasses a first nMOS transistor Q.sub.(m−1)21 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.(m−1)21 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.(n−1)1 through a second delay element D.sub.(m−1)22; a second nMOS transistor Q.sub.(m−1)22 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.(m−1)21, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.(n−1)2 configured to store the information of the cell M.sub.(n−1)2, connected in parallel with the second nMOS transistor Q.sub.(m−1)22, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.(n−1)21 and the drain electrode of the second nMOS transistor Q.sub.(m−1)22 serves as an output terminal of the cell M.sub.(n−1)2, configured to deliver the signal stored in the capacitor C.sub.(n−1)2 to the next bit-level cell M.sub.(n−1)3. The second column cell M.sub.m2 on the m-th row encompasses a first nMOS transistor Q.sub.m21 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.m21 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.m1 through a second delay element D.sub.m22; a second nMOS transistor Q.sub.m22 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.m21, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.m2 configured to store the information of the cell M.sub.m2, connected in parallel with the second nMOS transistor Q.sub.m22, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.m21 and the drain electrode of the second nMOS transistor Q.sub.m22 serves as an output terminal of the cell M.sub.m2, configured to deliver the signal stored in the capacitor C.sub.m2 to the next bit-level cell M.sub.m3.
(121) As shown in FIG. 4, the third memory unit U.sub.3 of word-size level is implemented by a vertical array of bit-level cell M.sub.13, M.sub.23, M.sub.33, . . . , M.sub.m−1,3, M.sub.m3 in the third column of the m*n matrix. The third-column cell M.sub.13 on the first row encompasses a first nMOS transistor Q.sub.131 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.131 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.12 through a second delay element D.sub.132; a second nMOS transistor Q.sub.132 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.131, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.13 configured to store the information of the cell M.sub.13, connected in parallel with the second nMOS transistor Q.sub.132, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.131 and the drain electrode of the second nMOS transistor Q.sub.132 serves as an output terminal of the cell M.sub.13, configured to deliver the signal stored in the capacitor C.sub.13 to the next bit-level cell. The third-column cell M.sub.23 on the second row encompasses a first nMOS transistor Q.sub.231 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.231 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.22 through a second delay element D.sub.232; a second nMOS transistor Q.sub.232 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.231, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.23 configured to store the information of the cell M.sub.23, connected in parallel with the second nMOS transistor Q.sub.232, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.231 and the drain electrode of the second nMOS transistor Q.sub.232 serves as an output terminal of the cell M.sub.23, configured to deliver the signal stored in the capacitor C.sub.23 to the next bit-level cell. The third-column cell M.sub.33 on the third row encompasses a first nMOS transistor Q.sub.331 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.331 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.32 through a second delay element D.sub.332; a second nMOS transistor Q.sub.332 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.331, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.33 configured to store the information of the cell M.sub.33, connected in parallel with the second nMOS transistor Q.sub.332, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.331 and the drain electrode of the second nMOS transistor Q.sub.332 serves as an output terminal of the cell M.sub.33, configured to deliver the signal stored in the capacitor C.sub.33 to the next bit-level cell.
(122) The third-column cell M.sub.(n−1)3 on the (m−1)-th row encompasses a first nMOS transistor Q.sub.(m−1)31 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.(m−1)31 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.(n−1)2 through a second delay element D.sub.(m−1)32; a second nMOS transistor Q.sub.(m−1)32 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.(m−1)31, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.(n−1)3 configured to store the information of the cell M.sub.(n−1)3, connected in parallel with the second nMOS transistor Q.sub.(m−1)32, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.(m−1)31 and the drain electrode of the second nMOS transistor Q.sub.(m−1)32 serves as an output terminal of the cell M.sub.(n−1)3, configured to deliver the signal stored in the capacitor C.sub.(n−1)3 to the next bit-level cell. The third-column cell M.sub.m3 on the m-th row encompasses a first nMOS transistor Q.sub.m31 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.m31 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.m2 through a second delay element D.sub.m32; a second nMOS transistor Q.sub.m32 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.m31, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.m3 configured to store the information of the cell M.sub.m3, connected in parallel with the second nMOS transistor Q.sub.m32, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.m31 and the drain electrode of the second nMOS transistor Q.sub.m32 serves as an output terminal of the cell M.sub.m3, configured to deliver the signal stored in the capacitor C.sub.m3 to the next bit-level cell.
(123) As shown in FIG. 4, the n-th memory unit of word-size level is implemented by a vertical array of bit-level cell M.sub.1n, M.sub.2n, M.sub.3n, . . . , M.sub.m−1,n, M.sub.mn in the n-th column of the m*n matrix. The n-th-column cell M.sub.1n on the first row encompasses a first nMOS transistor Q.sub.1n1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.1n1 and a gate electrode connected to the bit-level output terminal of the previous bit-level cell M.sub.1(n−1) through a second delay element D.sub.1n2; a second nMOS transistor Q.sub.1n2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.1n1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.1n configured to store the information of the cell M.sub.1n, connected in parallel with the second nMOS transistor Q.sub.1n2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.1n1 and the drain electrode of the second nMOS transistor Q.sub.1n2 serves as a bit-level output terminal of the cell M.sub.1n, configured to deliver the signal stored in the capacitor C.sub.1n to a first bit-level output terminal. The n-th-column cell M.sub.2n on the second row encompasses a first nMOS transistor Q.sub.2n1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.2n1 and a gate electrode connected to the bit-level output terminal of the previous bit-level cell M.sub.2(n−1) through a second delay element D.sub.2n2; a second nMOS transistor Q.sub.2n2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.2n1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.2n configured to store the information of the cell M.sub.2n, connected in parallel with the second nMOS transistor Q.sub.2n2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.2n1 and the drain electrode of the second nMOS transistor Q.sub.2n2 serves as a bit-level output terminal of the cell M.sub.2n, configured to deliver the signal stored in the capacitor C.sub.2n to a second bit-level output terminal. The n-th-column cell M.sub.3n on the third row encompasses a first nMOS transistor Q.sub.3n1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.3n1 and a gate electrode connected to the bit-level output terminal of the previous bit-level cell M.sub.3(n−1) through a second delay element D.sub.3n2; a second nMOS transistor Q.sub.3n2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.3n1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.3n configured to store the information of the cell M.sub.3n, connected in parallel with the second nMOS transistor Q.sub.3n2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.3n1 and the drain electrode of the second nMOS transistor Q.sub.3n2 serves as a bit-level output terminal of the cell M.sub.3n, configured to deliver the signal stored in the capacitor C.sub.3n to a third bit-level output terminal.
(124) The n-th-column cell M.sub.(m−1)n on the (m−1)-th row encompasses a first nMOS transistor Q.sub.(m−1)n1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.(m−1)n1 and a gate electrode connected to the bit-level output terminal of the previous bit-level cell M.sub.(m−1)(n−1) through a second delay element D.sub.(m−1)n2; a second nMOS transistor Q.sub.(m−1)n2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.(m−1)n1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.(m−1)n configured to store the information of the cell M.sub.(m−1)n, connected in parallel with the second nMOS transistor Q.sub.(m−1)n2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.(m−1)n1 and the drain electrode of the second nMOS transistor Q.sub.(m−1)n2 serves as a bit-level output terminal of the cell M.sub.(m−1)n, configured to deliver the signal stored in the capacitor C.sub.(m−1)n to a (m−1)-th bit-level output terminal. The n-th-column cell M.sub.mn on the m-th row encompasses a first nMOS transistor Q.sub.mn1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.mn1 and a gate electrode connected to the bit-level output terminal of the previous bit-level cell M.sub.m(n−1) through a second delay element D.sub.mn2; a second nMOS transistor Q.sub.mn2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.mn1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.mn configured to store the information of the cell M.sub.mn, connected in parallel with the second nMOS transistor Q.sub.mn2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.mn1 and the drain electrode of the second nMOS transistor Q.sub.mn2 serves as a bit-level output terminal of the cell M.sub.mn, configured to deliver the signal stored in the capacitor C.sub.mn to a m-th bit-level output terminal.
(125) As shown in FIG. 5, a bit-level cell M.sub.ij of the j-th column and on the i-th row, in the representative 2*2 cell-array of the marching main memory used in the computer system pertaining to the exemplary embodiment of the present invention, encompasses a first nMOS transistor Q.sub.ij1 having a drain electrode connected to a clock signal supply line through a first delay element D.sub.ij1 and a gate electrode connected to the output terminal of the previous bit-level cell through a second delay element D.sub.ij2; a second nMOS transistor Q.sub.ij2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.ij1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.ij configured to store the information of the bit-level cell M.sub.ij, connected in parallel with the second nMOS transistor Q.sub.ij2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.ij1 and the drain electrode of the second nMOS transistor Q.sub.ij2 serves as an output terminal of the bit-level cell M.sub.ij, configured to deliver the signal stored in the capacitor C.sub.ij to the next bit-level cell M.sub.i(j+1).
(126) A column bit-level cell M.sub.i(j+1) of the (j+1)-th column and on the i-th row encompasses a first nMOS transistor Q.sub.i(j+1)1 having a drain electrode connected to clock signal supply line through a first delay element D.sub.i(j+1)1 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.ij through a second delay element D.sub.i(j+1)2; a second nMOS transistor Q.sub.i(j+1)2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.i(j+1)1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.i(j+1) configured to store the information of the bit-level cell M.sub.i(j+1), connected in parallel with the second nMOS transistor Q.sub.i(j+1)2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.i(j+1)1 and the drain electrode of the second nMOS transistor Q.sub.i(j+1)2 serves as an output terminal of the bit-level cell M.sub.i(j+1), configured to deliver the signal stored in the capacitor C.sub.i(j+1) to the next cell.
(127) And, a bit-level cell M.sub.(i+1)j of the j-th column and on the (i+1)-th row encompasses a first nMOS transistor Q.sub.(i+1)j1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.(i+1)j1 and a gate electrode connected to the output terminal of the previous bit-level cell through a second delay element D.sub.(i+1)j2; a second nMOS transistor Q.sub.(i+1)j2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.(i+1)j1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.(i+1)j configured to store the information of the bit-level cell M.sub.(i+1)j, connected in parallel with the second nMOS transistor Q.sub.(i+1)j2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.(i+1)j1 and the drain electrode of the second nMOS transistor Q.sub.(i+1)j2 serves as an output terminal of the bit-level cell M.sub.(i+1)j, configured to deliver the signal stored in the capacitor C.sub.(i+1)j to the next bit-level cell M.sub.(i+1)(j+1).
(128) Furthermore, a bit-level cell M.sub.(i+1)(j+1) of the (j+1)-th column and on the (i+1)-th row encompasses a first nMOS transistor Q.sub.(i+1)(j+1)1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.(i+1)(j+1)1 and a gate electrode connected to the output terminal of the previous bit-level cell M.sub.(i+1)j through a second delay element D.sub.(i+1)(j+1)2; a second nMOS transistor Q.sub.(i+1)(j+1)2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.(i+1)(j+1)1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.(i+1)(j+1) configured to store the information of the bit-level cell M.sub.(i+1)(j+1), connected in parallel with the second nMOS transistor Q.sub.(i+1)(j+1)2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.(i+1)(j+1)1 and the drain electrode of the second nMOS transistor Q.sub.(i+1)(j+1)2 serves as an output terminal of the bit-level cell M.sub.(i+1)(j+1), configured to deliver the signal stored in the capacitor C.sub.(i+1)(j+1) to the next cell.
(129) As shown in FIG. 6, the j-th bit-level cell M.sub.ij on the i-th row encompasses a first nMOS transistor Q.sub.ij1 having a drain electrode connected to a clock signal supply line through a first delay element D.sub.ij1 and a gate electrode connected to the output terminal of the previous cell through a second delay element D.sub.ij2; a second nMOS transistor Q.sub.ij2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.ij1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.ij configured to store the information of the bit-level cell M.sub.ij, connected in parallel with the second nMOS transistor Q.sub.ij2.
(130) In the circuit configuration shown in FIG. 6, the second nMOS transistor Q.sub.ij2 serves as a reset-transistor configured to reset the signal charge stored in the capacitor C.sub.ij, when a clock signal of high-level (or a logical level of “1”) is applied to the gate electrode of the second nMOS transistor Q.sub.ij2, discharging the signal charge already stored in the capacitor C.sub.ij.
(131) FIGS. 7A and 7B show a schematic example of the transistor-level responses of the bit-level cell M.sub.ij shown in FIG. 6, which is one of the bit-level cells used in the computer system, to a waveform of a clock signal shown by broken line. The clock signal shown by broken line swings periodically between the logical levels of “1” and “0” with the clock period TAU(Greek-letter).sub.clock. In FIGS. 7A and 7B, t.sub.1−t.sub.0 (=t.sub.2−t.sub.1=t.sub.3−t.sub.2=t.sub.4−t.sub.3) is defined to be a quarter of the clock period TAU.sub.clock(=TAU.sub.clock/4).
(132) As shown in FIG. 7A(a), at time “t.sub.0”, although the clock signal of high-level shown by the broken line is applied both to a drain electrode of the first nMOS transistor Q.sub.ij1 through a first ideal delay element D.sub.ij1 and to a gate electrode of the second nMOS transistor Q.sub.ij2, the second nMOS transistor Q.sub.ij2 keeps off-state until the first nMOS transistor Q.sub.ij1 will establish on-state at time “t.sub.1”, because the potential of the output node N.sub.out, connecting between a source electrode of the first nMOS transistor Q.sub.ij1 and a drain electrode of the second nMOS transistor Q.sub.ij2, is supposed to be a floating state, lying between the logical levels of “0” and “1”, between the time “t.sub.0” and the time “t.sub.1”.
(133) Owing to the first ideal delay element D.sub.ij1, because the turn on of the first nMOS transistor Q.sub.ij1 is delayed by t.sub.1−t.sub.0=TAU.sub.clock/4, the first nMOS transistor Q.sub.ij1 becomes active as a transfer-transistor at time “t.sub.1”, and the potential of the output node N.sub.out becomes the logical level “1”. Here, it is assumed that the first ideal delay element D.sub.ij1 can achieve a delay of TAU.sub.clock/4 with very sharp leading edge, by which the rise time can be neglected. That is, as shown by solid line with very sharp leading edge and very sharp trailing edge in FIG. 7A(a), the clock signal applied at time “to” is delayed by t.sub.1−t.sub.0=TAU.sub.clock/4. Then, as shown in FIG. 7A(c)-(d), if the signal stored in the previous bit-level cell M.sub.i(j−1) is the logical level of “1”, the second nMOS transistor Q.sub.ij2 becomes active as a reset-transistor, and any signal charge stored in the capacitor C.sub.ij is driven to be discharged, at time “t.sub.2”.
(134) The first nMOS transistor Q.sub.ij1 becomes completely active as the transfer-transistor at time “t.sub.2”, delayed by a predetermined delay time t.sub.d2=t.sub.2−t.sub.0=TAU.sub.clock/2, determined by the second ideal delay element D.sub.ij2. Here, it is assumed that the second ideal delay element D.sub.ij2 can achieve a delay of TAU.sub.clock/2 with very sharp leading edge, by which the rise time can be neglected. Then, if the signal of the logical level of “1” stored in a previous bit-level cell M.sub.i(j−1) is fed from the previous bit-level cell M.sub.i(j−1) on the i-th row to the gate electrode of the first nMOS transistor Q.sub.ij1, at time “t.sub.2”, the signal charge stored in the capacitor C.sub.ij is completely discharged to establish the logical level of “0”, as shown in FIG. 7A(b), and the first nMOS transistor Q.sub.ij1 begins transferring the signal of the logical level of “1” stored in the previous bit-level cell M.sub.i(j−1), to the capacitor C.sub.ij so as to execute marching AND-gate operation as shown in FIG. 7A(c)-(d). That is, with an input signal of “1” provided by the clock signal and another input signal of “1” provided by the previous bit-level cell M.sub.i(j−1), the conventional 2-input AND operation of:
1+1=1
can be executed. By the way, if the signal charge stored in the capacitor C.sub.ij is of the logical level of “1”, the capacitor C.sub.ij can begin discharging at time “to”, because the second nMOS transistor Q.sub.ij2 can become active as the reset-transistor with the clock signal of the high-level shown by the broken line applied to the gate electrode of the second nMOS transistor Q.sub.ij2 at time “t.sub.0”, if the operation of the second nMOS transistor Q.sub.ij2 has no delay.
(135) Alternatively, as shown in FIG. 7B(c)-(d), if the signal stored in the previous bit-level cell M.sub.i(j−1) is the logical level of “0”, the first nMOS transistor Q.sub.ij1 keeps off-sate at any time “t.sub.0”, “t.sub.1”, “t.sub.2” and “t.sub.3”. As above-mentioned, if the signal charge stored in the capacitor C.sub.ij is of the logical level of “1”, although the first nMOS transistor Q.sub.ij1 keeps off-sate, the capacitor C.sub.ij can begin discharging at time “t.sub.0”, because the second nMOS transistor Q.sub.ij2 can become active as the reset-transistor with the clock signal of the high-level shown by the broken line applied to the gate electrode of the second nMOS transistor Q.sub.ij2 at time “t.sub.0”, and the marching AND-gate operation of:
1+0=0
is executed as shown in FIG. 7A(c)-(d), with an input signal of “1” provided by the clock signal and another input signal of “0” provided by the previous bit-level cell M.sub.i(j−1). However, if the signal charge stored in the capacitor C.sub.ij is of the logical level of “0”, because both of the first nMOS transistor Q.sub.ij1 and the second nMOS transistor Q.sub.ij2 keep the off-sate, the capacitor C.sub.ij keep the logical level of “0” at any time “t.sub.0”, “t.sub.1”, “t.sub.2” and “t.sub.3”, and the marching AND-gate operation of is executed as shown in FIG. 7A(c)-(d). The output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.ij1 and the drain electrode of the second nMOS transistor Q.sub.ij2 serves as an output terminal of the bit-level cell M.sub.ij, and the output terminal of the bit-level cell M.sub.ij delivers the signal stored in the capacitor C.sub.ij to the next bit-level cell on the i-th row.
(136) FIG. 7C shows an actual example of the response to the waveform of the clock signal, for a case that both of the first delay element D.sub.ij1 and the second delay element D.sub.ij2 are implemented by R-C delay circuit, as shown in FIG. 8. In a normal operation of the marching memory, the signal charge stored in the capacitor C.sub.ij is actually either of the logical level of “0” or“1”, and if the signal charge stored in the capacitor C.sub.ij is of the logical level of “1”, although the first nMOS transistor Q.sub.ij1 still keeps off-sate, the capacitor C.sub.ij can begin discharging at time “t.sub.0”, because the second nMOS transistor Q.sub.ij2 can become active when the clock signal of the high-level is applied to the gate electrode of the second nMOS transistor Q.sub.ij2, if an ideal operation of the second nMOS transistor Q.sub.ij2 with no delay can be approximated. Therefore, if the signal charge stored in the capacitor C.sub.ij is actually of the logical level of “1”, after the clock signal of high-level has been applied to the gate electrode of the second nMOS transistor Q.sub.ij2 and the signal charge stored in the capacitor C.sub.ij has been discharged, the first nMOS transistor Q.sub.ij1 becomes active as a transfer-transistor, delayed by a predetermined delay time to determined by the first delay element D.sub.ij1 implemented by the R-C delay circuit. And when the signal stored in a previous bit-level cell M.sub.i(j−1) is fed from the previous bit-level cell M.sub.i(j−1) on the i-th row to the gate electrode of the first nMOS transistor Q.sub.ij1, the first nMOS transistor Q.sub.ij1 transfers the signal stored in the previous bit-level cell M.sub.i(j−1), further delayed by a predetermined delay time t.sub.d2 determined by the second delay element D.sub.ij2 to the capacitor C.sub.ij. An output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.ij1 and the drain electrode of the second nMOS transistor Q.sub.ij2 serves as an output terminal of the bit-level cell M.sub.ij, and the output terminal of the bit-level cell M.sub.ij delivers the signal stored in the capacitor C.sub.ij to the next bit-level cell on the i-th row.
(137) As shown in FIG. 7C, the clock signal swings periodically between the logical levels of “1” and “0”, with a predetermined clock period (clock cycle time) TAU.sub.clock, and when the clock signal becomes the logical level of “1”, the second nMOS transistor Q.sub.ij2 begins to discharge the signal charge, which is already stored in the capacitor C.sub.ij at a previous clock cycle. And, after the clock signal of the logical level of “1” is applied and the signal charge stored in the capacitor C.sub.ij is completely discharged to the potential of the logical level of “0”, the first nMOS transistor Q.sub.ij1 becomes active as the transfer-transistor, delayed by the predetermined delay time t.sub.d1 determined by the first delay element D.sub.ij1. The delay time t.sub.d1 is set to be equal to ¼TAU.sub.clock in an exemplary embodiment. Thereafter, when the signal stored in the previous bit-level cell M.sub.i(j−1) on the i-th row is fed from the previous bit-level cell M.sub.i(j−1) to the gate electrode of the first nMOS transistor Q.sub.ij1, the first nMOS transistor Q.sub.ij1 transfers the signal stored in the previous bit-level cell M.sub.i(j−1), further delayed by the predetermined delay time t.sub.d2 determined by the second delay element D.sub.ij2 implemented by the R-C delay circuit to the capacitor C.sub.ij.
(138) For example, if the logical level of “1” stored in the previous bit-level cell M.sub.i(j−1) on the i-th row is fed from the previous bit-level cell M.sub.i(j−1) to the gate electrode of the first nMOS transistor Q.sub.ij1, the first nMOS transistor Q.sub.ij1 becomes conductive state, and the logical level of “1” is stored in the capacitor C.sub.ij. On the other hand, if the logical level of “0” stored in the previous bit-level cell M.sub.i(j−1) is fed from the previous bit-level cell M.sub.i(j−1) to the gate electrode of the first nMOS transistor Q.sub.ij1, the first nMOS transistor Q.sub.ij1 keeps cut-off state, and the logical level of “0” is maintained in the capacitor C.sub.ij. Therefore, the bit-level cell M.sub.ij can establish “a marching AND-gate” operation. The delay time t.sub.d2 shall be longer than the delay time t.sub.d1, and the delay time t.sub.d2 is set to be equal to ½TAU.sub.clock in an exemplary embodiment.
(139) Since the clock signal swings periodically between the logical levels of “1” and “0”, with the clock period TAU.sub.clock, the clock signal becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, and the output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.ij1 and the drain electrode of the second nMOS transistor Q.sub.ij2 cannot deliver the signal transferred from the previous bit-level cell M.sub.i(j−1) further to the next bit-level cell M.sub.i(j+1) at a time when time proceeds 1/2TAU.sub.clock, as the signal is blocked to be transferred to the gate electrode of the next first nMOS transistor Q.sub.i(j+1)1 delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second delay element D.sub.i(j+1)2. When the clock signal becomes the logical level of “1” again at a time when time proceeds TAU.sub.clock, the output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.ij1 and the drain electrode of the second nMOS transistor Q.sub.ij2, which is serving as the output terminal of the bit-level cell M.sub.ij, can deliver the signal stored in the capacitor C.sub.ij to the next bit-level cell M.sub.i(j+1) at the next clock cycle.
(140) Again referring to FIG. 4, when the clock signal shown in FIG. 7A(a) or FIG. 7C becomes the logical level of “1”, a sequence of the second nMOS transistors Q.sub.112, Q.sub.212, Q.sub.312, . . . , Q.sub.m−1,12, Q.sub.m12 in the first memory unit U.sub.1 begin to discharge the signal charges, respectively, which are already stored in the capacitors C.sub.11, C.sub.21, C.sub.31, . . . , C.sub.m−1,1, C.sub.m1, respectively, in the first memory unit U.sub.1 at a previous clock cycle. And, after the clock signal of the logical level of “1” is applied to the gate electrodes of the sequence of the second nMOS transistors Q.sub.112, Q.sub.212, Q.sub.312, . . . , Q.sub.m−1,12, Q.sub.m12, respectively, and the signal charges stored in the capacitors C.sub.11, C.sub.21, C.sub.31, . . . , C.sub.m−1,1, C.sub.m1 are completely discharged to the potential of the logical level of “0”, a sequence of the first nMOS transistors Q.sub.111, Q.sub.211, Q.sub.311, . . . , Q.sub.m−1,11, Q.sub.m11 becomes active as the transfer-transistors, delayed by the delay time to determined by the first delay elements D.sub.111, D.sub.211, D.sub.311, . . . , D.sub.m−1,11, D.sub.m11, respectively. Thereafter, when a sequence of signals of word size, which is multiples of eight bits, such as 16, 32, and 64 bits are entered to the gate electrodes of the sequence of the first nMOS transistors Q.sub.111, Q.sub.211, Q.sub.311, . . . , Q.sub.m−1,11, Q.sub.m11, the sequence of the first nMOS transistors Q.sub.111, Q.sub.211, Q.sub.311, . . . , Q.sub.m−1,11, Q.sub.m11 transfer the sequence of signals of word size to the capacitors C.sub.11, C.sub.21, C.sub.31, . . . , C.sub.m−1,1, C.sub.m1, delayed by the delay time t.sub.d2 determined by the second delay elements D.sub.112, D.sub.212, D.sub.312, . . . , D.sub.m−1,12, D.sub.m12, respectively.
(141) When the clock signal becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, each of the output nodes connecting the source electrodes of the first nMOS transistors Q.sub.111, Q.sub.211, Q.sub.311, . . . , Q.sub.m−1,11, Q.sub.m11 and the drain electrodes of the second nMOS transistors Q.sub.112, Q.sub.212, Q.sub.312, . . . , Q.sub.m−1,12, Q.sub.m12 cannot deliver the signals, which are entered to the gate electrodes of the first nMOS transistors Q.sub.111, Q.sub.211, Q.sub.311, . . . , Q.sub.m−1,11, Q.sub.m11, further to the next bit-level cell M.sub.12, M.sub.22, M.sub.32, . . . , M.sub.m−1,2, M.sub.m2 at a time when time proceeds 1/2TAU.sub.clock, as each of the signals is blocked to be transferred to the gate electrodes of the next first nMOS transistors Q.sub.121, Q.sub.221, Q.sub.321, . . . , Q.sub.m−1,21, Q.sub.m21 delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second delay element D.sub.122, D.sub.222, D.sub.322, . . . , D.sub.m−1,22, D.sub.m22.
(142) At a time when time proceeds TAU.sub.clock, when the next clock signal becomes the logical level of “1” again, a sequence of the second nMOS transistors Q.sub.122, Q.sub.222, Q.sub.322, . . . , Q.sub.m−1,22, Q.sub.m22 in the second memory unit U.sub.2 begin to discharge the signal charges, respectively, which are already stored in the capacitors C.sub.12, C.sub.22, C.sub.32, . . . , C.sub.m−1,2, C.sub.m2, respectively, in the second memory unit U.sub.2 at the previous clock cycle. And, after the clock signal of the logical level of “1” is applied to the gate electrodes of the sequence of the second nMOS transistors Q.sub.122, Q.sub.222, Q.sub.322, . . . , Q.sub.m−1,22, Q.sub.m22, respectively, and the signal charges stored in the capacitors C.sub.12, C.sub.22, C.sub.32, . . . , C.sub.m−1,2, C.sub.m2, are completely discharged to the potential of the logical level of “0”, a sequence of the first nMOS transistors Q.sub.121, Q.sub.221, Q.sub.321, . . . , Q.sub.m−1,21, Q.sub.m21 becomes active as the transfer-transistors, delayed by the delay time to determined by the first delay elements D.sub.121, D.sub.221, D.sub.321, . . . , D.sub.m−1,21, D.sub.m21, respectively. Thereafter, when the sequence of signals of word size stored in the previous capacitors C.sub.11, C.sub.21, C.sub.31, . . . , C.sub.m−1,1, C.sub.m1 are fed to the gate electrode of the sequence of the first nMOS transistors Q.sub.121, Q.sub.221, Q.sub.321, . . . , Q.sub.m−1,21, Q.sub.m21, the first nMOS transistor Q.sub.121, Q.sub.221, Q.sub.321, . . . , Q.sub.m−1,21, Q.sub.m21 transfer the sequence of signals of word size, delayed by the delay time t.sub.d2 determined by the second delay element D.sub.122, D.sub.222, D.sub.322, . . . , D.sub.m−1,22, D.sub.m22, to the capacitors C.sub.12, C.sub.22, C.sub.32, . . . , C.sub.m−1,2, C.sub.m2.
(143) When the clock signal becomes the logical level of “0” at a time when time further proceeds (1+1/2)TAU.sub.clock, each of the output nodes connecting the source electrodes of the first nMOS transistors Q.sub.121, Q.sub.221, Q.sub.321, . . . , Q.sub.m−1,21, Q.sub.m21 and the drain electrodes of the second nMOS transistors Q.sub.122, Q.sub.222, Q.sub.322, . . . , Q.sub.m−1,22, Q.sub.m2 cannot deliver the signals stored in the previous bit-level cell M.sub.11, M.sub.21, M.sub.31, . . . , M.sub.m−1,1, M.sub.m1 further to the next bit-level cell M.sub.12, M.sub.22, M.sub.32, . . . , M.sub.m−1,2, M.sub.m2 at a time when time proceeds (1+1/2)TAU.sub.clock, as each of the signals is blocked to be transferred to the gate electrode of the next first nMOS transistor Q.sub.131, Q.sub.231, Q.sub.331, . . . , Q.sub.m−1,31, Q.sub.m31 delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second delay element D.sub.132, D.sub.232, D.sub.332, . . . , D.sub.m−1,32, D.sub.m32.
(144) At a time when time further proceeds 2TAU.sub.clock, when the next clock signal becomes the logical level of “1” again, a sequence of the second nMOS transistors Q.sub.132, Q.sub.232, Q.sub.332, . . . , Q.sub.m−1,32, Q.sub.m32 in the third memory unit U.sub.3 begin to discharge the signal charges, respectively, which are already stored in the capacitors C.sub.13, C.sub.23, C.sub.33, . . . , C.sub.m−1,3, C.sub.m3, respectively, in the third memory unit U.sub.3 at the previous clock cycle. And, after the clock signal of the logical level of “1” is applied to the gate electrodes of the sequence of the second nMOS transistors Q.sub.132, Q.sub.232, Q.sub.332, . . . , Q.sub.m−1,32, Q.sub.m32, respectively, and the signal charges stored in the capacitors C.sub.13, C.sub.23, C.sub.33, . . . , C.sub.m−1,3, C.sub.m3, are completely discharged to the potential of the logical level of “0”, a sequence of the first nMOS transistors Q.sub.131, Q.sub.231, Q.sub.331, . . . , Q.sub.m−1,31, Q.sub.m31 becomes active as the transfer-transistors, delayed by the delay time to determined by the first delay elements D.sub.131, D.sub.231, D.sub.331, . . . , D.sub.m−1,31, D.sub.m31, respectively. Thereafter, when the sequence of signals of word size stored in the previous capacitors C.sub.12, C.sub.22, C.sub.32, . . . , C.sub.m−1,2, C.sub.m2 are fed to the gate electrode of the sequence of the first nMOS transistors Q.sub.131, Q.sub.231, Q.sub.331, . . . , Q.sub.m−1,31, Q.sub.m31, the first nMOS transistor Q.sub.131, Q.sub.231, Q.sub.331, . . . , Q.sub.m−1,31, Q.sub.m31 transfer the sequence of signals of word size, delayed by the delay time t.sub.d2 determined by the second delay element D.sub.132, D.sub.232, D.sub.332, . . . , D.sub.m−1,32, D.sub.m32, to the capacitors C.sub.13, C.sub.23, C.sub.33, . . . , C.sub.m−1,3, C.sub.m3.
(145) As shown in FIG. 8, each of the first delay element D and the second delay element D.sub.ij2 can be implemented by known “resistive-capacitive delay” or “R-C delay”. In the RC circuit, the value of the time constant (in seconds) is equal to the product of the circuit resistance (in ohms) and the circuit capacitance (in farads), i.e. t.sub.d1, t.sub.d2=R*C. Because the structure of the RC circuit is very simple, an RC circuit may be used for the first delay element D.sub.ij1 and the second delay element D.sub.ij2. However, the RC circuit is exemplary, and the first delay element D.sub.ij1 and the second delay element D.sub.ij2. can be implemented by another passive delay elements, or various active delay element, which may include active element of transistor, etc.
(146) FIG. 9 is an example of the top view of the actual planar pattern of the bit-level cell M.sub.ij of the j-th column and on the i-th row shown in FIG. 8, which has the first delay element D.sub.ij1 and the second delay element D.sub.ij2 implemented by the R-C delay circuit, and FIG. 10 shows the corresponding cross-sectional view taken on the line A-A of FIG. 9. As shown in FIG. 9, the first delay element D.sub.ij1 is implemented by a first meandering line 91 of conductive wire, and the second delay element D.sub.ij2 is implemented by a second meandering line 97 of conductive wire.
(147) In FIG. 9, the first nMOS transistor Q.sub.ij1 has a drain electrode region 93 connected to the first meandering line 91 via a contact plug 96a. The other end of the first meandering line 91 opposite to the end connected to the drain electrode region 93 of the first nMOS transistor Q.sub.ij1 is connected to the clock signal supply line. The drain electrode region 93 is implemented by an n.sup.+ semiconductor region. A gate electrode of the first nMOS transistor Q.sub.ij1 is implemented by the second meandering line 97. The other end of the second meandering line 97 opposite to the end serving as the gate electrode of the first nMOS transistor Q.sub.ij1 is connected to the output terminal of the previous cell.
(148) The second nMOS transistor Q.sub.ij2 has a drain electrode region implemented by a common n.sup.+ semiconductor region 94, which also serves as the source electrode region of the first nMOS transistor Q.sub.ij1, a gate electrode 98 connected to the clock signal supply line via a contact plug 96a, and a source electrode region 95 connected to the ground potential via a contact plug 96a. The source electrode region 95 is implemented by an n.sup.+ semiconductor region. Because the common n.sup.+ semiconductor region 94 is the output node connecting the source electrode region of the first nMOS transistor Q.sub.ij1 and the drain electrode region of the second nMOS transistor Q.sub.ij2, the common n.sup.+ semiconductor region 94 is connected to a surface wiring 92b via a contact plug 96d. The common n.sup.+ semiconductor region 94 serves as the output terminal of the bit-level cell M.sub.ij, and delivers the signal stored in the capacitor C.sub.ij to the next bit-level cell through the surface wiring 92b.
(149) As shown in FIG. 10, the drain electrode region 93, the common n.sup.+ semiconductor region 94, and the source electrode region 95 is provided at the surface of and in the upper portion of the p-type semiconductor substrate 81. Instead of the p-type semiconductor substrate 81, the drain electrode region 93, the common n.sup.+ semiconductor region 94, and the source electrode region 95 can be provided in the upper portion of the p-well, or p-type epitaxial layer grown on a semiconductor substrate. On the p-type semiconductor substrate 81, an element isolation insulator 82 is provided so as to define an active area of the p-type semiconductor substrate 81 as a window provided in the element isolation insulator 82. And the drain electrode region 93, the common n.sup.+ semiconductor region 94, and the source electrode region 95 is provided in the active area, surrounded by the element isolation insulator 82. At the surface of and on the active area, a gate insulating film 83 is provided. And the gate electrode of the first nMOS transistor Q.sub.ij1 implemented by the second meandering line 97 and the gate electrode 98 of the second nMOS transistor Q.sub.ij2 are provided on the gate insulating film 83.
(150) As shown in FIG. 10, a first interlayer dielectric film 84 is provided on the second meandering line 97 and the gate electrode 98. On a part of the first interlayer dielectric film 84, a bottom electrode 85 of the capacitor C.sub.ij configured to store the information of the bit-level cell M.sub.ij is provided. The bottom electrode 85 is made of conducting film, and a contact plug 96c is provided in the first interlayer dielectric film 84 so as to connect between the bottom electrode 85 and the source electrode region 95. And, on the bottom electrode 85, a capacitor insulating film 86 is provided.
(151) Furthermore, on the capacitor insulating film 86, a top electrode 87 of the capacitor C.sub.ij is provided so as to occupy an upper portion of the bottom electrode 85. The top electrode 87 is made of conducting film. Although the illustration is omitted in the cross-sectional view shown in FIG. 10, the top electrode 87 is electrically connected to the common n.sup.+ semiconductor region 94 so as to establish an electric circuit topology that the capacitor C.sub.ij is connected in parallel with the second nMOS transistor Q.sub.ij2. A variety of insulator films may be used as the capacitor insulating film 86. The miniaturized marching main memory may be required to occupy a small area of the bottom electrode 85 opposing the top electrode 87. However, to allow the marching main memory to function successfully, the capacitance between the bottom electrode 85 and the top electrode 87 via the capacitor insulating film 86 needs to maintain a constant value. In particular, with a miniaturized marching main memory with a minimum line width of approximately 100 nm or less, usage of a material with a dielectric constant e.sub.r greater than that of a silicon oxide (SiO.sub.2) film is used in an exemplary embodiment, considering the storage capacitance between the bottom electrode 85 and the top electrode 87. With an ONO film, for example, the ratio in thickness of the upper layer silicon oxide film, the middle layer silicon nitride film, and the underlayer silicon oxide film is selectable, however, a dielectric constant e.sub.r of approximately 5 to 5.5 can be provided. Alternatively, a single layer film made from any one of a strontium oxide (SrO) film with e.sub.r=6, a silicon nitride (Si.sub.3N.sub.4) film with e.sub.r=7, an aluminum oxide (Al.sub.2O.sub.3) film where e.sub.r=8-11, a magnesium oxide (MgO) film where e.sub.r=10, an yttrium oxide (Y.sub.2O.sub.3) film where e.sub.r=16-17, a hafnium oxide (HfO.sub.2) film where e.sub.r=22-23, a zirconium oxide (ZrO.sub.2) film where e.sub.r=22-23, a tantalum oxide (Ta.sub.2O.sub.5) film where e.sub.r=25-27, or a bismuth oxide (Bi.sub.2O.sub.3) film where e.sub.r=40, or a composite film embracing at least two of these plural layers thereof may be used. Ta.sub.2O.sub.5 and Bi.sub.2O.sub.3 show disadvantages in lacking thermal stability at the interface with the polysilicon. Furthermore, it may be a composite film made from a silicon oxide film and these films. The composite film may have a stacked structure of triple-levels or more. In other words, it should be an insulating film containing a material with the relative dielectric constant e.sub.r of 5 to 6 or greater in at least a portion thereof. However, in the case of a composite film, selecting a combination that results in having an effective relative dielectric constant e.sub.reff of 5 to 6 or greater measured for the entire film is used in an exemplary embodiment. Moreover, it may also be an insulating film made from an oxide film of a ternary compound such as a hafnium aluminate (HfAlO) film.
(152) Furthermore, a second interlayer dielectric film 87 is provided on the top electrode 87. And the first meandering line 91 is provided on second interlayer dielectric film 87. As shown in FIG. 10, the contact plug 96a is provided, penetrating the first interlayer dielectric film 84, the capacitor insulating film 86 and the second interlayer dielectric film 87 so as to connect between the first meandering line 91 and the drain electrode region 93
(153) In a topology shown in FIGS. 9 and 10, the capacitance C of the R-C delay is implemented by the stray capacitance associated with the first meandering line 91 and the second meandering line 97. Because both R and C are proportional to wire lengths of the first meandering line 91 and the second meandering line 97, the delay times t.sub.d1, t.sub.d2 can be easily designed by electing the wire lengths of the first meandering line 91 and the second meandering line 97. Furthermore, we can design the thickness, the cross section, or the resistivity of the first meandering line 91 and the second meandering line 97 to as to achieve desired value of the delay times t.sub.d1, t.sub.d2.
(154) For example, because the delay time t.sub.d2 shall be twice of the delay time t.sub.d1, the wire length of the second meandering line 97 can be designed as 2.sup.1/2 time of the wire length the first meandering line 91, if we use the same thickness, the same cross section, and the material having the same specific resistively for the first meandering line 91 and the second meandering line 97, and further the same effective thickness and the same effective dielectric constant for the insulating film implementing the stray capacitance for the R-C delay (=R*C). However, if we use different materials for the first meandering line 91 and the second meandering line 97, the wire lengths of the first meandering line 91 and the second meandering line 97 shall be determined depending on the resistivities of the first meandering line 91 and the second meandering line 97 so as to achieve the required values of the delay times t.sub.d1, t.sub.d2. For example, in a case that the second meandering line 97 is formed of polycrystalline silicon, and the first meandering line 91 is formed of refractory material such as tungsten (W), molybdenum (Mo), platinum (Pt), having a higher resistivity than the polycrystalline silicon, the wire lengths of the first meandering line 91 and the second meandering line 97 are determined depending on the resistivities of the first meandering line 91 and the second meandering line 97 so as to achieve the required values of the delay times t.sub.d1, t.sub.d2.
(155) Furthermore, although the first meandering line 91 and the second meandering line 97 are shown in FIG. 9, the shown meandering topology for resistor R is mere example, and other topologies such as a straight line configuration can be used depending upon the required values of resistor R and capacitance C. In a very high speed operation of the marching main memory 31, the delineation of extrinsic resistor elements R can be omitted, if parasitic resistance (stray resistance) and parasitic capacitance (stray capacitance) can achieve the required delay times t.sub.d1, t.sub.d2.
(156) In the configuration shown in FIGS. 4-6, although an isolation between a signal-storage state of the (j−1)-th bit-level cell M.sub.ij−1 on the i-th row and a signal-storage state of the j-th bit-level cell M.sub.ij on the i-th row can be established by a propagation delay accompanying the signal propagation path between the output terminal of the (j−1)-th bit-level cell M.sub.ij−1 and the gate electrode of the first nMOS transistor Q.sub.ij1 of the j-th bit-level cell the propagation delay is mainly ascribable to the value of the second delay element D.sub.ij2, in an exemplary embodiment, an inter-unit cell is inserted between the (j−1)-th bit-level cell M.sub.ij−1 and the j-th bit-level cell as shown in FIGS. 11 and 13.
(157) Although the inter-unit cell B.sub.ij is provided so as to isolate the signal-storage state of the j-th bit-level cell M.sub.ij in the j-th memory unit U.sub.j from the signal-storage state of the (j−1)-th bit-level cell M.sub.ij−1 in the (j−1)-th memory unit U.sub.j−1, the inter-unit cell B.sub.ij transfers a signal from the (j−1)-th bit-level cell M.sub.ij−1 to the j-th bit-level cell M.sub.ij at a required timing determined by a clock signal, which is supplied through the clock signal supply line. Because the j-th memory unit U.sub.j stores information of byte size or word size by the sequence of bit-level cells arrayed in the j-th memory unit U.sub.j, and the (j−1)-th memory unit U.sub.j−1 stores information of byte size or word size by the sequence of bit-level cells arrayed in the (j−1)-th memory unit U.sub.j−1, a sequence of inter-unit cells arrayed in parallel with the memory units U.sub.j−1 and U.sub.j transfers the information of byte size or word size, controlled by the clock signal supplied through the clock signal supply line so that the information of byte size or word size can march along a predetermined direction, pari passu. As shown in FIGS. 11 and 13, because the input terminal of the j-th bit-level cell M.sub.ij on the i-th row is connected to the inter-unit cell B.sub.ij, the signal charge stored in the (j−1)-th bit-level cell M.sub.ij−1 is fed to the second delay element D.sub.ij2 through the inter-unit cell B.sub.ij at the required timing, and the transfer operation of the signal charge is cut off at periods other than the required timing.
(158) In FIGS. 11 and 13, although an example of the inter-unit cell B.sub.ij, which encompasses a single isolation transistor Q.sub.ij3 having a first main-electrode connected to the output terminal of the (j−1)-th bit-level cell M.sub.ij, a second main-electrode connected to the input terminal of the j-th bit-level cell M.sub.ij and a control electrode connected to the clock signal supply line, the structure of the inter-unit cell B.sub.ij is not limited to the configuration shown in FIGS. 11 and 13. For example, the inter-unit cell B.sub.ij may be implemented by a clocked-circuit having a plurality of transistors, which can transfer the signal from the (j−1)-th bit-level cell M.sub.ij−1 to the j-th bit-level cell M.sub.ij at the required timing determined by the clock signal.
(159) Similar to the configuration shown in FIG. 5, the j-th bit-level cell M.sub.ij encompasses the first nMOS transistor Q.sub.ij1 having the drain electrode connected to the clock signal supply line through the first delay element D.sub.ij1 and the gate electrode connected to the inter-unit cell B.sub.ij through the second delay element D.sub.ij2; the second nMOS transistor Q.sub.ij2 having the drain electrode connected to the source electrode of the first nMOS transistor Q.sub.ij1, the gate electrode connected to the clock signal supply line, and the source electrode connected to the ground potential; and the capacitor C.sub.ij configured to store the information of the bit-level cell M.sub.ij, connected in parallel with the second nMOS transistor Q.sub.ij2.
(160) An example of planar structure of the inter-unit cell B.sub.ij, encompassing a single isolation transistor Q.sub.ij3 of nMOS transistor is shown in FIG. 12, in addition to the configuration of the bit-level cell M.sub.ij, which are already shown in FIG. 9. In the bit-level cell M.sub.ij, the first nMOS transistor Q.sub.ij1 having the drain electrode region 93, the first meandering line 91 connected to the drain electrode region 93 via a contact plug 96a, the second meandering line 97 implementing the gate electrode of the first nMOS transistor Q.sub.ij1, and the second nMOS transistor Q.sub.ij3 having the drain electrode region implemented by the common n.sup.+ semiconductor region 94, serving as the output terminal of the bit-level cell M.sub.ij are shown.
(161) In FIG. 12, the isolation transistor Q.sub.ij3 of the inter-unit cell B.sub.ij has a first main-electrode region implemented by a left side of an n.sup.+ semiconductor region 90, a gate electrode 99 connected to the clock signal supply line, and a second main-electrode region implemented by a right side of the n.sup.+ semiconductor region 90. The second main-electrode region is connected to one end of the second meandering line 97 opposite to the other end of the second meandering line 97, which serves as the gate electrode of the first nMOS transistor Q.sub.ij1 via a contact plug 96e, and first main-electrode region is connected to the output terminal of the previous cell M.sub.ij−1 via a contact plug 96f. Although the illustration is omitted, similar to the structure shown in FIG. 10, on an interlayer dielectric film provided on the second meandering line 97, a parallel plate structure of the capacitor C.sub.ij configured to store the information of the bit-level cell M.sub.ij may be provided, being connected in parallel with the second nMOS transistor Q.sub.ij2.
(162) In FIG. 13, in addition to the configuration shown in FIG. 11, another inter-unit cell B.sub.i(j−1) is provided between the (j−2)-th bit-level cell M.sub.i(j−2) and the (j−1)-th bit-level cell M.sub.i(j−1), configured to isolate the signal-storage state of the (j−1)-th bit-level cell M.sub.i(j−1) in the (j−1)-th memory unit U.sub.j−1 from the signal-storage state of the (j−2)-th bit-level cell M.sub.i(j−2) in the (j−2)-th memory unit U.sub.j−2, and to transfer a signal from the (j−2)-th bit-level cell M.sub.i(j−2) to the (j−1)-th bit-level cell M.sub.i(j−1) at the required timing determined by the clock signal, which is supplied through the clock signal supply line. In FIG. 13, because the input terminal of the (j−1)-th bit-level cell M.sub.i(j−1) on the i-th row is connected to the inter-unit cell B.sub.i(j−1), the signal charge stored in the (j−2)-th bit-level cell M.sub.i(j−2) is fed to the second delay element D.sub.i(j−1)2 through the inter-unit cell B.sub.i(j−1) at the required timing, and the transfer operation of the signal charge is cut off thereafter.
(163) In FIG. 13, although an example of the inter-unit cell B.sub.i(j−1), which encompasses a single isolation transistor Q.sub.i(j−1)3 having a first main-electrode connected to the output terminal of the (j−2)-th bit-level cell M.sub.i(j−1), a second main-electrode connected to the input terminal of the (j−1)-th bit-level cell M.sub.i(j−1) and a control electrode connected to the clock signal supply line, the structure of the inter-unit cell B.sub.i(j−1) is not limited to the configuration shown in FIG. 13, and the inter-unit cell B.sub.i(j−1) may be implemented by a clocked-circuit having a plurality of transistors, which can transfer the signal from the (j−2)-th bit-level cell M.sub.i(j−2) to the (j−1)-th bit-level cell M.sub.i(j−1) at the required timing determined by the clock signal.
(164) Similar to the configuration of the j-th bit-level cell M.sub.ij, the (j−1)-th bit-level cell M.sub.i(j−1) encompasses a first nMOS transistor Q.sub.i(j−1)1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.i(j−1) and a gate electrode connected to the inter-unit cell B.sub.i(j−1) through a second delay element D.sub.i(j−1)2; a second nMOS transistor Q.sub.i(j−1)2 having a drain electrode connected to the source electrode of the first nMOS transistor Q.sub.i(j−1)1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.i(j−1) configured to store the information of the bit-level cell M.sub.i(j−1), connected in parallel with the second nMOS transistor Q.sub.i(j−1)2.
(165) In the circuit configuration shown in FIGS. 11 and 13, the second nMOS transistor Q.sub.ij2 of the bit-level cell M.sub.ij, serves as a reset-transistor configured to reset the signal charge stored in the capacitor C.sub.ij, when the clock signal of high-level (or a logical level of “1”) is applied to the gate electrode of the second nMOS transistor Q.sub.ij2, discharging the signal charge already stored in the capacitor C.sub.ij, and the second nMOS transistor Q.sub.i(j−1)2 of the bit-level cell M.sub.i(j−1) serves as a reset-transistor configured to reset the signal charge stored in the capacitor C.sub.i(j−1), when the clock signal of high-level (or a logical level of “1”) is applied to the gate electrode of the second nMOS transistor Q.sub.i(j−1)2, discharging the signal charge already stored in the capacitor C.sub.i(j−1). Therefore, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 may be pMOS transistors, which can operate complementary with the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2, although FIGS. 11 and 13 represent the transistor symbol of an nMOS transistor as the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3. That is, when the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2 are conductive state for discharging the signal charge stored in the capacitors C.sub.i(j−1) and C.sub.ij, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 shall be cut-off state so as to establish the isolation between the memory units, and when the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2 are cut-off state, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 shall be conductive state so as to transfer the signal charges between the memory units.
(166) Alternatively, if the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 are nMOS transistors, as the transistor symbol shows in FIGS. 11 and 13, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 shall be high-speed transistors having a shorter rise time, a shorter period of conductive state, and a shorter fall time than the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2, which have larger stray capacitances and larger stray resistances associated with gate circuits and gate structures so that, when the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2 are still in the cut-off state, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 becomes the conductive state very rapidly so as to transfer the signal charges between the memory units, and when the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2 start slowly toward the conductive state for discharging the signal charge stored in the capacitors C.sub.i(j−1) and C.sub.ij, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 proceeds to become the cut-off state very rapidly so as to establish the isolation between the memory units. As a candidate for such high-speed transistors, a normally off type MOS static induction transistor (SIT) can be used, which represents triode-like I-V characteristic. N-channel MOSFET can be considered as an extreme ultimate structure of the short channel nMOSFET. Owing to the triode-like I-V characteristic, because the on-state of the MOSSIT depends both on a gate voltage and a potential deference between the first and second main-electrodes, a very short time interval of the on-state can be achieved. Instead of the MOSSIT, any normally off type switching devices such as a tunneling SIT, which represent a very short on-state period like Dirac delta function, can be used.
(167) FIG. 14(a) shows a timing diagram of a response of the bit-level cell M.sub.i(j−1) shown in FIG. 13, and FIG. 14(b) shows a next timing diagram of a next response of the next bit-level cell M.sub.ij shown in FIG. 13, to a waveform of a clock signal. In FIGS. 14(a) and (b), the clock signal is supposed to swing periodically between the logical levels of “1” and “0” with the clock period TAU(Greek-letter) clock, and the shaded rectangular area with backward diagonals shows a regime for a reset timing of the signal charges stored in the capacitors C.sub.i(j−1) and C.sub.ij, respectively, and further, the shaded rectangular area with forward diagonals shows a regime for a charge-transfer timing of the signal charges to the capacitors C.sub.i(j−1) and C.sub.ij, respectively.
(168) As shown in FIG. 14(a), if the signal charges stored in the capacitor C.sub.i(j−1) is of the logical level of “1”, although the first nMOS transistor Q.sub.i(j−1)1 still keeps off-sate, the signal charge stored in the capacitor C.sub.i(j−1) is being driven to be discharging, in the shaded rectangular area with backward diagonals. After the capacitor C.sub.i(j−1) begins discharging, in the shaded rectangular area with forward diagonals, the first nMOS transistor Q.sub.i(j−1)1 becomes active as a transfer-transistor, delayed by a predetermined delay time t.sub.d1 determined by the first delay element D.sub.i(j−1)1 implemented by the R-C delay circuit. When the signal stored in a previous bit-level cell M.sub.i(j−2) is fed through the inter-unit cell B.sub.i(j−1) to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1, the first nMOS transistor Q.sub.i(j−1)1 transfers the signal stored in the previous bit-level cell M.sub.i(j−2), further delayed by a predetermined delay time t.sub.d2 determined by the second delay element D.sub.i(j−1)2 to the capacitor C.sub.i(j−1) in the shaded rectangular area with forward diagonals.
(169) Similarly, as shown in FIG. 14(b), if the signal charges stored in the capacitor is of the logical level of “1”, although the first nMOS transistor Q.sub.ij1 still keeps off-sate, the signal charge stored in the capacitor C.sub.ij is being driven to be discharging, in the shaded rectangular area with backward diagonals. After the capacitor C.sub.ij begins discharging, in the shaded rectangular area with forward diagonals, the first nMOS transistor Q.sub.ij1 becomes active as a transfer-transistor, delayed by a predetermined delay time t.sub.d1 determined by the first delay element D.sub.ij1 implemented by the R-C delay circuit. When the signal stored in a previous bit-level cell M.sub.i(j−1) is fed through the inter-unit cell B.sub.ij to the gate electrode of the first nMOS transistor Q.sub.ij1, the first nMOS transistor Q.sub.ij1 transfers the signal stored in the previous bit-level cell M.sub.i(j−1), further delayed by a predetermined delay time t.sub.d2 determined by the second delay element D.sub.ij2 to the capacitor C.sub.ij in the shaded rectangular area with forward diagonals
(170) FIG. 15 shows a more detailed response of the bit-level cell M.sub.i(j−1) shown in FIG. 13 to the waveform of the clock signal shown by thin solid line, for a case that both of the first delay element D.sub.i(j−1)1 and the second delay element D.sub.i(j−1)2 are implemented by R-C delay circuit, as shown in FIG. 12. The clock signal shown by thin solid line swings periodically between the logical levels of “1” and “0” with the clock period TAU.sub.clock. In FIG. 15, time interval TAU.sub.1=TAU.sub.2=TAU.sub.3=TAU.sub.4 is defined to be a quarter of the clock period TAU.sub.clock (=TAU.sub.clock/4).
(171) In a normal operation of the marching memory, the signal charge stored in the capacitor C.sub.i(j−1) is actually either of the logical level of “0” or“1”, as shown in FIGS. 16(a)-(d). If the signal charge stored in the capacitor C.sub.i(j−1) is of the logical level of “1”, as shown in FIGS. 16(c) and (d), although the first nMOS transistor Q.sub.i(j−1)1 still keeps off-sate, the capacitor C.sub.i(j−1) can begin discharging at the beginning of the time interval TAU.sub.1, because the second nMOS transistor Q.sub.i(j−1)2 becomes active when the clock signal of the high-level is applied to the gate electrode of the second nMOS transistor Q.sub.i(j−1)2, under the assumption that an ideal operation of the second nMOS transistor Q.sub.i(j−1)2 with no delay can be approximated. Therefore, if the signal charge stored in the capacitor C.sub.i(j−1) is actually of the logical level of “1”, after the clock signal of high-level has been applied to the gate electrode of the second nMOS transistor Q.sub.i(j−1)2, as shown by the thin solid line in FIG. 15, and the signal charge stored in the capacitor C.sub.i(j−1) will be discharged, and thereafter, the first nMOS transistor Q.sub.i(j−1)1 becomes active as a transfer-transistor, delayed by a predetermined delay time to determined by the first delay element D.sub.i(j−1)1 implemented by the R-C delay circuit. In FIG. 15, the change of the potential at the drain electrode of the first nMOS transistor Q.sub.i(j−1)1 is shown by dash-dotted line.
(172) As shown by a thick solid line in FIG. 15, when the signal level of “1” stored in a previous bit-level cell M.sub.i(j−2) is fed from the previous bit-level cell M.sub.i(j−2) on the i-th row through the inter-unit cell B.sub.i(j−1) to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1, the first nMOS transistor Q.sub.i(j−1)1 transfers the signal level of “1” stored in the previous bit-level cell M.sub.i(j−2), further delayed by a predetermined delay time t.sub.d2 determined by the second delay element D.sub.i(j−1)2 to the capacitor C.sub.i(j−1). Alternatively, as shown by a broken line in FIG. 15, when the signal level of “0” stored in a previous bit-level cell M.sub.i(j−2) is fed from the previous bit-level cell M.sub.i(j−2) to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1, the first nMOS transistor Q.sub.i(j−1)1 transfers the signal level of “0” stored in the previous bit-level cell M.sub.i(j−2), further delayed by the predetermined delay time t.sub.d2 to the capacitor C.sub.i(j−1). An output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.i(j−1)1 and the drain electrode of the second nMOS transistor Q.sub.i(j−1)2 serves as an output terminal of the bit-level cell M.sub.i(j−1), and the output terminal delivers the signal stored in the capacitor C.sub.i(j−1) to the next bit-level cell on the i-th row.
(173) As shown by the thin solid line in FIG. 15, when the clock signal becomes the logical level of “1”, the second nMOS transistor Q.sub.i(j−1)2 begins to discharge the signal charge, which is already stored in the capacitor C.sub.i(j−1) at a previous clock cycle. After the clock signal of the logical level of “1” is applied and the signal charge stored in the capacitor C.sub.i(j−1) is completely discharged to the potential of the logical level of “0”, the first nMOS transistor Q.sub.i(j−1)1 becomes active as the transfer-transistor, delayed by the predetermined delay time t.sub.d1 determined by the first delay element D.sub.i(j−1)1. The delay time to is set to be equal to ¼TAU.sub.clock=TAU.sub.1 in an exemplary embodiment.
(174) When the signal stored in the previous bit-level cell M.sub.i(j−2) is fed from the previous bit-level cell M.sub.i(j−2) to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1 through the inter-unit cell B.sub.i(j−1), as shown by thick solid line and broken line, the first nMOS transistor Q.sub.i(j−1)1 transfers the signal stored in the previous bit-level cell M.sub.i(j−2), further delayed by the predetermined delay time t.sub.d2 determined by the second delay element D.sub.i(j−1)2 implemented by the R-C delay circuit to the capacitor C.sub.i(j−1).
(175) For example, if the logical level of “1” stored in the previous bit-level cell M.sub.i(j−2) is fed from the previous bit-level cell M.sub.i(j−2) to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1 as shown by the thick solid line, the first nMOS transistor Q.sub.i(j−1)1 becomes conductive state at the beginning of the time intervalTAU.sub.3, and the logical level of “1” is stored in the capacitor C.sub.i(j−1). On the other hand, if the logical level of “0” stored in the previous bit-level cell M.sub.i(j−2) is fed from the previous bit-level cell M.sub.i(j−1)2 to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1 as shown by the broken line, the first nMOS transistor Q.sub.i(j−1)1 keeps the cut-off state, and the logical level of “0” is maintained in the capacitor C.sub.i(j−1). Therefore, the bit-level cell M.sub.i(j−1) can establish “a marching AND-gate” operation. The delay time t.sub.d2 is longer than the delay time to, and the delay time t.sub.d2 is set to be equal to ½TAU.sub.clock in an exemplary embodiment.
(176) Since the clock signal swings periodically between the logical levels of “1” and “0”, with the clock period TAU.sub.clock, as shown by the thin solid line, then the clock signal becomes the logical level of “0” as time proceeds by ½TAU.sub.clock, or at the beginning of the time interval TAU.sub.3, the potential at the drain electrode of the first nMOS transistor Q.sub.i(j−1)1 begins to decay as shown by the dash-dotted line. If the inter-unit cell B.sub.ij, inserted between the current bit-level cell M.sub.i(j−1) and the next bit-level cell M.sub.ij, is implemented by an nMOS transistor, the path between the output terminal of the current bit-level cell M.sub.i(j−1) and the gate electrode of the first nMOS transistor Q.sub.ij1 of the next bit-level cell M.sub.ij, becomes the cut-off state by the logical level of “0” of the clock signal being applied to the gate electrode of the nMOS transistor, and therefore, the output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.i(j−1)1 and the drain electrode of the second nMOS transistor Q.sub.i(j−1)2 cannot deliver the signal transferred from the previous bit-level cell M.sub.i(j−2) further to the next bit-level cell M.sub.ij like duckpins in the time intervalsTAU.sub.3 and TAU.sub.4, and the signal is blocked to be domino transferred to the gate electrode of the next first nMOS transistor Q.sub.ij1. Since the first nMOS transistor Q.sub.i(j−1)1 becomes the cut-off state in the time intervals TAU.sub.3 and TAU.sub.4, the potential at the output node N.sub.out is kept in a floating state, and the signal states stored in the capacitor C.sub.i(j−1) are held.
(177) When the clock signal becomes the logical level of “1” again, as shown by the thin solid line in a next column of FIG. 15, the output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.i(j−1)1 and the drain electrode of the second nMOS transistor Q.sub.i(j−1)2, which is serving as the output terminal of the bit-level cell M.sub.i(j−1), can deliver the signal stored in the capacitor C.sub.i(j−1) to the next bit-level cell M.sub.ij at the next clock cycle because the inter-unit cell B.sub.ij becomes conductive state, and the potential at the drain electrode of the first nMOS transistor Q.sub.i(j−1)1 increase as shown by the dash-dotted line.
(178) FIGS. 16(a)-(d) show four modes of signal-transferring operations, respectively, focusing to the bit-level cell M.sub.ij shown in FIGS. 11 and 13, the bit-level cell M.sub.ij is one of the bit-level cells arrayed sequentially in the j-th memory unit U.sub.j, the j-th memory unit U.sub.j stores information of byte size or word size by the sequence of bit-level cells arrayed sequentially in the j-th memory unit U.sub.j. In the exemplary computer system, the information of byte size or word size arrayed sequentially marches side by side from a previous memory unit to a next memory unit, pari passu. In FIGS. 16(a)-(d), the clock signal is supplied by the clock signal supply line CLOCK so as to swing periodically between the logical levels of “1” and “0” with the clock period TAU.sub.clock, while the clock signal supply line CLOCK serves as a power supply line.
(179) FIGS. 16(a) and (b) show when the logical level of “0” is stored by previous clock signal into the capacitor C.sub.ij, and FIGS. 16(c) and (d) show when the logical level of “1” is stored by previous clock signal into the capacitor C.sub.ij as one of the signal in the information of byte size or word size. As shown in FIG. 16(a), in a case when the signal charge previously stored in the capacitor C.sub.ij is of the logical level of “0”, if the signal of the logical level of “0”, which is stored in a previous bit-level cell M.sub.i(j−1), as one of the signal in the information of byte size or word size to be transferred in a cooperative way, is fed from the previous bit-level cell M.sub.i(j−1) through the inter-unit cell B.sub.ij (the illustration is omitted) to the gate electrode of the first nMOS transistor Q.sub.ij1, in the timing the signal charge stored in the capacitor C.sub.ij keeping the logical level of “0”, because the first nMOS transistor Q.sub.ij1 keeps off-state, the output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.ij1 and the drain electrode of the second nMOS transistor Q.sub.ij2 delivers the signal level of “0”, which is maintained in the capacitor C.sub.ij, to the next bit-level cell on the i-th row, so as to execute marching AND-gate operation of 0+1=0 with an input signal of “1” provided by the clock signal.
(180) Similarly, as shown in FIG. 16(b), in a case when the signal charge previously stored in the capacitor C.sub.ij is of the logical level of “0”, if the signal of the logical level of “1” stored in a previous bit-level cell M.sub.i(j−1) is fed from the previous bit-level cell M.sub.i(j−1) through the inter-unit cell B.sub.ij to the gate electrode of the first nMOS transistor Q.sub.ij1, in the timing the signal charge stored in the capacitor C.sub.ij keeps the logical level of “0”, the first nMOS transistor Q.sub.ij1 begins turning-on for transferring the signal of the logical level of “1” stored in the previous bit-level cell M.sub.i(j−1) to the capacitor C.sub.ij so that the logical level of “1” can be stored in the capacitor C.sub.ij, and the output node N.sub.out delivers the signal level of “1” stored in the capacitor C.sub.ij to the next bit-level cell on the i-th row, so as to execute marching AND-gate operation 1+1=1 with an input signal of “1” provided by the clock signal.
(181) On the contrary, as shown in FIG. 16(c), when the signal charge previously stored in the capacitor C.sub.ij is of the logical level of “1”, if the signal of the logical level of “0”, which is stored in a previous bit-level cell M.sub.i(j−1), is fed from the previous bit-level cell M.sub.i(j−1) through the inter-unit cell B.sub.ij to the gate electrode of the first nMOS transistor Q.sub.ij1, after the timing when the signal charge stored in the capacitor C.sub.ij is completely discharged to establish the logical level of “0”, because the first nMOS transistor Q.sub.ij1 keeps off-state, the output node N.sub.out delivers the signal level of “0” stored in the capacitor C.sub.ij to the next bit-level cell on the i-th row, so as to execute marching AND-gate operation of 0+1=0 with an input signal of “1” provided by the clock signal.
(182) Similarly, as shown in FIG. 16(d), when the signal charge previously stored in the capacitor C.sub.ij is of the logical level of “1”, if the signal of the logical level of “1” stored in a previous bit-level cell M.sub.i(j−1) is fed from the previous bit-level cell M.sub.i(j−1) through the inter-unit cell B.sub.ij to the gate electrode of the first nMOS transistor Q.sub.ij1, after the timing when the signal charge stored in the capacitor C.sub.ij is completely discharged to establish the logical level of “0”, the first nMOS transistor Q.sub.ij1 begins turning-on for transferring the signal of the logical level of “1” stored in the previous bit-level cell M.sub.i(j−1) to the capacitor C.sub.ij so that the logical level of “1” can be stored in the capacitor C.sub.ij, and the output node N.sub.out delivers the signal level of “1” stored in the capacitor C.sub.ij to the next bit-level cell on the i-th row, so as to execute marching AND-gate operation 1+1=1 with an input signal of “1” provided by the clock signal.
(183) Similar to the configuration shown in FIG. 11, although an inter-unit cell B.sub.ij is inserted between the (j−1)-th bit-level cell M.sub.ij−1 and the j-th bit-level cell M.sub.ij, and the j-th bit-level cell M.sub.ij encompasses the first nMOS transistor Q.sub.ij1 having the drain electrode connected to the clock signal supply line through the first delay element D.sub.ij1 and the gate electrode connected to the inter-unit cell B.sub.ij through the second delay element D.sub.ij2; the second nMOS transistor Q.sub.ij2 having the drain electrode connected to the source electrode of the first nMOS transistor Q.sub.ij1, the gate electrode connected to the clock signal supply line, and the source electrode connected to the ground potential; and the capacitor C.sub.ij configured to store the information of the bit-level cell M.sub.ij, connected in parallel with the second nMOS transistor Q.sub.ij2, the features such that the first delay element D.sub.ij1 is implemented by a first diode D.sub.1a, and the second delay element D.sub.ij2 is implemented by a tandem connection of a second diode D.sub.2a and a third diode D.sub.3a is distinguishable from the configuration shown in FIG. 11.
(184) Although any p-n junction diode can be represented by an equivalent circuit encompassing resistors, including the series resistance such as the diffusion resistance, the lead resistance, the ohmic contact resistance and the spreading resistance, etc., and capacitors including the diode capacitance such as the junction capacitance or the diffusion capacitance, and a single diode or a tandem connection of diodes can serve as “resistive-capacitive delay” or “R-C delay”, because the value of “R-C delay” can be made much smaller than the values achieved by the specialized and dedicated R-C elements, such as the first meandering line 91 and the second meandering line 97 shown in FIGS. 9 and 12, the operation of the j-th bit-level cell M.sub.ij with the inter-unit cell B.sub.ij shown in FIG. 17 can achieve a higher level of operation than the operation achieved by the configuration shown in FIG. 12. That is, the operation of the j-th bit-level cell M.sub.ij with the inter-unit cell B.sub.ij shown in FIG. 17 can approach an ideal delay performance shown in FIGS. 7A and 7B, in which any rise time and fall time are not shown, and wave forms of the pulses are shown by ideal rectangular shape. In addition to the performance by the configuration shown in FIGS. 11 and 12, because the tandem connection of the second diode D.sub.2a and the third diode D.sub.3a can block efficiently the flow of the reverse-directional current, the configuration implemented by a combination of the j-th bit-level cell M.sub.ij with the inter-unit cell B.sub.ij shown in FIG. 17 can achieve a better isolation between the signal-storage state of the (j−1)-th bit-level cell M.sub.i(j−1) and the signal-storage state of the j-th bit-level cell M.sub.ij, even if the signal of the lower logical level of “0” stored in the previous bit-level cell M.sub.i(j−1) is fed to the gate electrode of the first nMOS transistor Q.sub.ij1 through the inter-unit cell B.sub.ij.
(185) In FIG. 18, in addition to the configuration shown in FIG. 17, another inter-unit cell B.sub.i(j−1) is provided between the (j−2)-th bit-level cell M.sub.i(j−2) and the (j−1)-th bit-level cell M.sub.i(j−1), configured to isolate the signal-storage state of the (j−1)-th bit-level cell M.sub.i(j−1) in the (j−1)-th memory unit U.sub.j−1 from the signal-storage state of the (j−2)-th bit-level cell M.sub.i(j−2) in the (j−2)-th memory unit U.sub.j−2, and to transfer a signal from the (j−2)-th bit-level cell M.sub.i(j−2) to the (j−1)-th bit-level cell M.sub.i(j−1) at the required timing determined by the clock signal, which is supplied through the clock signal supply line. In FIG. 18, because the input terminal of the (j−1)-th bit-level cell M.sub.i(j−1) is connected to the inter-unit cell B.sub.i(j−1), the signal charge stored in the (j−2)-th bit-level cell M.sub.i(j−2) is fed to the second delay element D.sub.i(j−1)2 through the inter-unit cell B.sub.i(j−1) at the required timing, and the transfer of the signal charge is cut off thereafter.
(186) Similar to the configuration of the j-th bit-level cell M.sub.ij, the (j−1)-th bit-level cell M.sub.i(j−1) encompasses a first nMOS transistor Q.sub.i(j−1)1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.i(j−1)1 and a gate electrode connected to the inter-unit cell B.sub.i(j−1) through a second delay element D.sub.i(j−1)2; a second nMOS transistor Q.sub.i(j−1)2 having a drain electrode connected to the source electrode of the first nMOS transistor Q.sub.i(j−1)1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.i(j−1) configured to store the information of the bit-level cell M.sub.i(j−1), connected in parallel with the second nMOS transistor Q.sub.i(j−1)2. Here, the first delay element D.sub.i(i−1)1 is implemented by a first diode D.sub.1b, and the second delay element D.sub.i(i−1)2 is implemented by a tandem connection of a second diode D.sub.2b and a third diode D.sub.3b.
(187) As explained above, because a single diode or a tandem connection of diodes can serve as “resistive-capacitive delay” or “R-C delay”, the operation of the (j−1)-th bit-level cell M.sub.i(j−1) with the inter-unit cell B.sub.i(j−1) shown in FIG. 18 is substantially same as the operation shown in FIG. 13. In addition to the performance by the configuration shown in FIG. 13, because the tandem connection of the second diode D.sub.2b and the third diode D.sub.3b can block efficiently the flow of the reverse-directional current, the configuration implemented by a combination of the (j−1)-th bit-level cell M.sub.i(j−1) with the inter-unit cell B.sub.i(j−1) shown in FIG. 18 can achieve a better isolation between the signal-storage state of the (j−2)-th bit-level cell M.sub.i(j−2) and the signal-storage state of the (j−1)-th bit-level cell M.sub.i(j−1), even if the signal of the lower logical level of “0” stored in the previous bit-level cell M.sub.i(j−2) is fed to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1 through the inter-unit cell B.sub.i(j−1).
(188) In actual semiconductor devices, because many parasitic resistances (stray resistances) and many parasitic capacitances (stray capacitances) associated with wirings, gate structures, electrode structures, and junction structures are inherent, in a very high speed operation of the marching main memory, the delineation of extrinsic resistor elements and capacitor elements can be omitted, if the parasitic resistances and the parasitic capacitances can achieve the required delay times t.sub.d1, t.sub.d2 compared with operation speed of the marching main memory. Therefore, in the configuration shown in FIGS. 11-13 and 16, the first delay elements D.sub.i(j−1)1 and D.sub.ij1 can be omitted, as shown in FIGS. 19, 20 and 22.
(189) In another exemplary embodiment of the bit-level cells shown in FIG. 19, although the j-th bit-level cell M.sub.ij encompasses a first nMOS transistor Q.sub.ij1, similar to the configuration shown in FIG. 11, the first nMOS transistor Q.sub.ij1 has a drain electrode directly connected to the clock signal supply line, and the first delay element D.sub.ij1 employed in the configuration shown in FIG. 11 is omitted. The feature that the first nMOS transistor Q.sub.ij1 has a gate electrode connected to the inter-unit cell B.sub.ij through a signal-delay element D.sub.ij, which corresponds to the second delay element D.sub.ij2 shown in FIG. 11, and the second nMOS transistor Q.sub.ij2 has a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.ij1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential, and a capacitor C.sub.ij configured to store the information of the bit-level cell M.sub.ij, connected in parallel with the second nMOS transistor Q.sub.ij2 is substantially same as the configuration shown in FIG. 11.
(190) In another exemplary embodiment of the bit-level cell shown in FIG. 19, similar to the configuration shown in FIGS. 11-13 and 16, the inter-unit cell B.sub.ij is further provided so as to isolate the signal-storage state of the j-th bit-level cell M.sub.ij in the j-th memory unit U.sub.j from the signal-storage state of the (j−1)-th bit-level cell M.sub.ij−1 in the (j−1)-th memory unit U.sub.j−1. Furthermore, the inter-unit cell B.sub.ij transfers a signal from the (j−1)-th bit-level cell M.sub.ij−1 to the j-th bit-level cell M.sub.ij at a required timing determined by a clock signal, which is supplied through the clock signal supply line. Since the j-th memory unit U.sub.j stores information of byte size or word size by the sequence of bit-level cells arrayed in the j-th memory unit U.sub.j, and the (j−1)-th memory unit U.sub.j−1 stores information of byte size or word size by the sequence of bit-level cells arrayed in the (j−1)-th memory unit U.sub.j−1, a sequence of inter-unit cells arrayed in parallel with the memory units U.sub.j−1 and U.sub.j transfers the information of byte size or word size, controlled by the clock signal supplied through the clock signal supply line so that the information of byte size or word size can march along a predetermined direction, pari passu.
(191) As shown in FIG. 19, the input terminal of the j-th bit-level cell M.sub.ij on the i-th row is connected to the inter-unit cell B.sub.ij, the signal charge stored in the (j−1)-th bit-level cell M.sub.ij−1 is fed to the signal-delay element D.sub.ij through the inter-unit cell B.sub.ij at the required timing, and the transfer operation of the signal charge is cut off at periods other than the required timing.
(192) In FIG. 20, in addition to the configuration shown in FIG. 19, another inter-unit cell B.sub.i(j−1) is provided between the (j−2)-th bit-level cell M.sub.i(j−2) and the (j−1)-th bit-level cell M.sub.i(j−1), configured to isolate the signal-storage state of the (j−1)-th bit-level cell M.sub.i(j−1) in the (j−1)-th memory unit U.sub.j−1 from the signal-storage state of the (j−2)-th bit-level cell M.sub.i(j−2) in the (j−2)-th memory unit U.sub.j−2, and to transfer a signal from the (j−2)-th bit-level cell M.sub.i(j−2) to the (j−1)-th bit-level cell M.sub.i(j−1) at the required timing determined by the clock signal, which is supplied through the clock signal supply line. In FIG. 20, because the input terminal of the (j−1)-th bit-level cell M.sub.i(j−1) on the i-th row is connected to the inter-unit cell B.sub.i(j−1), the signal charge stored in the (j−2)-th bit-level cell M.sub.i(j−2) is fed to the signal-delay element D.sub.i(j−1) through the inter-unit cell B.sub.i(j−1) at the required timing, and the transfer operation of the signal charge is cut off thereafter.
(193) Similar to the configuration of the j-th bit-level cell M.sub.ij, the (j−1)-th bit-level cell M.sub.i(j−1) encompasses a first nMOS transistor Q.sub.i(j−1)1 having a drain electrode directly connected to the clock signal supply line and a gate electrode connected to the inter-unit cell B.sub.i(j−1) through a signal-delay element D.sub.i(j−1); a second nMOS transistor Q.sub.i(j−1)2 having a drain electrode connected to the source electrode of the first nMOS transistor Q.sub.i(j−1)1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.i(j−1) configured to store the information of the bit-level cell M.sub.i(j−1), connected in parallel with the second nMOS transistor Q.sub.i(j−1)2.
(194) In the circuit configuration, as one of other examples of the bit-level cells pertaining to the exemplary embodiment, shown in FIGS. 19 and 20, the second nMOS transistor Q.sub.ij2 of the bit-level cell M.sub.ij, serves as a reset-transistor configured to reset the signal charge stored in the capacitor C.sub.ij, when the clock signal of high-level (or a logical level of “1”) is applied to the gate electrode of the second nMOS transistor Q.sub.ij2, discharging the signal charge already stored in the capacitor C.sub.ij, and the second nMOS transistor Q.sub.i(j−1)2 of the bit-level cell M.sub.i(j−1) serves as a reset-transistor configured to reset the signal charge stored in the capacitor C.sub.i(j−1), when the clock signal of high-level (or a logical level of “1”) is applied to the gate electrode of the second nMOS transistor Q.sub.i(j−1)2, discharging the signal charge already stored in the capacitor C.sub.i(j−1).
(195) In FIGS. 19 and 20, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 are high-speed transistors having a shorter rise time, a shorter period of conductive state, and a shorter fall time than the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2, which have larger stray capacitances and larger stray resistances associated with gate circuits and gate structures so that, when the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2 are still in the cut-off state, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 becomes the conductive state very rapidly so as to transfer the signal charges between the memory units, and when the second nMOS transistors Q.sub.i(j−1)2 and Q.sub.ij2 start slowly toward the conductive state for discharging the signal charge stored in the capacitors C.sub.i(j−1) and C.sub.ij, the isolation transistors Q.sub.i(j−1)3 and Q.sub.ij3 proceeds to become the cut-off state very rapidly so as to establish the isolation between the memory units.
(196) FIG. 21 shows a detailed response of the bit-level cell M.sub.i(j−1) shown in FIG. 20, which is one of other examples of the bit-level cells used in the computer system pertaining to the exemplary embodiment of the present invention, to the waveform of the clock signal shown by thin solid line, for a case that the signal-delay element D.sub.i(j−1) is implemented by R-C delay circuit. The clock signal shown by thin solid line swings periodically between the logical levels of “1” and “0” with the clock period TAU.sub.clock. In FIG. 21, time intervalTAU.sub.1=TAU.sub.2=TAU.sub.3=TAU.sub.4 is defined to be a quarter of the clock period TAU.sub.clock (=TAU.sub.clock/4).
(197) In a normal operation of the marching memory, the signal charge stored in the capacitor C.sub.i(j−1) is actually either of the logical level of “0” or“1”, as shown in FIGS. 22(a)-(d). If the signal charge stored in the capacitor C.sub.i(j−1) is of the logical level of “1”, as shown in FIGS. 22(c) and (d), although the first nMOS transistor Q.sub.i(j−1)1 still keeps off-sate because the potential of the gate electrode of the first nMOS transistor Q.sub.i(j−1)1 is delayed by the signal-delay element D.sub.i(j−1), the capacitor C.sub.i(j−1) can begin discharging at the beginning of the time intervalTAU.sub.1, because the second nMOS transistor Q.sub.i(j−1)2 becomes active rapidly when the clock signal of the high-level is applied to the gate electrode of the second nMOS transistor Q.sub.i(j−1)2, under the assumption that an ideal operation of the second nMOS transistor Q.sub.i(j−1)2 with no delay can be approximated. Therefore, if the signal charge stored in the capacitor C.sub.i(j−1) is actually of the logical level of “1”, after the clock signal of high-level has been applied to the gate electrode of the second nMOS transistor Q.sub.i(j−1)2, as shown by the thin solid line in FIG. 21, and the signal charge stored in the capacitor C.sub.i(j−1) will be discharged to the logical level of “0”, and at the same time approximately, the first nMOS transistor Q.sub.i(j−1)1 is prepared to be active as a transfer-transistor, delayed by a negligibly-short delay time determined by parasitic elements implemented by stray resistance and stray capacitance. In FIG. 21, the change of the potential at the drain electrode of the first nMOS transistor Q.sub.i(j−1)1 is shown exaggeratingly by dash-dotted line.
(198) As shown by a thick solid line in FIG. 21, when the signal level of “1” stored in a previous bit-level cell M.sub.i(j−2) is fed from the previous bit-level cell M.sub.i(j−2) through the inter-unit cell B.sub.i(j−1) to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1, the first nMOS transistor Q.sub.i(j−1)1 turns on, and the first nMOS transistor Q.sub.i(j−1)1 transfers the signal level of “1” stored in the previous bit-level cell M.sub.i(j−2), delayed by a predetermined delay time t.sub.d2 determined by the signal-delay element D.sub.i(j−1) to the capacitor C.sub.i(j−1). Alternatively, as shown by a broken line in FIG. 21, when the signal level of “0” stored in a previous bit-level cell M.sub.i(j−2) is fed from the previous bit-level cell M.sub.i(j−2) to the gate electrode of the first nMOS transistor Q.sub.i(j−1)1, the first nMOS transistor Q.sub.i(j−1)1 keeps off-state. At this instant of time, since the capacitor C.sub.i(j−1) still keeps the logical level of “0”, the first nMOS transistor Q.sub.i(j−1)1 transfers equivalently the signal level of “0” stored in the previous bit-level cell M.sub.i(j−2). An output node N.sub.out serving as an output terminal of the bit-level cell M.sub.i(j−1) delivers the signal stored in the capacitor C.sub.i(j−1) to the next bit-level cell on the i-th row.
(199) Since the clock signal swings periodically between the logical levels of “1” and “0”, with the clock period TAU.sub.clock as shown by the thin solid line, the clock signal becomes the logical level of “0” as time proceeds by ½TAU.sub.clock, or at the beginning of the time intervalTAU.sub.3, the potential at the drain electrode of the first nMOS transistor Q.sub.i(j−1)1 begins to decay rapidly as shown exaggeratingly by the dash-dotted line. If the inter-unit cell B.sub.ij, inserted between the current bit-level cell M.sub.i(j−1) and the next bit-level cell M.sub.ij, is implemented by an nMOS transistor, the path between the output terminal of the current bit-level cell M.sub.i(j−1) and the gate electrode of the first nMOS transistor Q.sub.ij1 of the next bit-level cell M.sub.ij, becomes the cut-off state by the logical level of “0” of the clock signal being applied to the gate electrode of the nMOS transistor, and therefore, the output node N.sub.out cannot deliver the signal transferred from the previous bit-level cell M.sub.i(j−2) further to the next bit-level cell M.sub.ij like duckpins in the time intervalsTAU.sub.3 and TAU.sub.4, and the signal is blocked to be domino transferred to the gate electrode of the next first nMOS transistor Q.sub.ij1. Because the first nMOS transistor Q.sub.i(j−1)1 becomes the cut-off state in the time intervalsTAU.sub.3 and TAU.sub.4, the potential at the output node N.sub.out is kept in a floating state, and the signal states stored in the capacitor C.sub.i(j−1) are held.
(200) When the clock signal becomes the logical level of “1” again, as shown by the thin solid line in a next column of FIG. 21, the output node N.sub.out connecting the source electrode of the first nMOS transistor Q.sub.i(j−1)1 and the drain electrode of the second nMOS transistor Q.sub.i(j−1)2, which is serving as the output terminal of the bit-level cell M.sub.i(j−1), can deliver the signal stored in the capacitor C.sub.i(j−1) to the next bit-level cell M.sub.ij at the next clock cycle because the inter-unit cell B.sub.ij becomes conductive state, and the potential at the drain electrode of the first nMOS transistor Q.sub.i(j−1) increase as shown exaggeratingly by the dash-dotted line.
(201) FIGS. 22(a)-(d) show four modes of signal-transferring operations, respectively, focusing to the bit-level cell M.sub.ij shown in FIGS. 19 and 20, the bit-level cell M.sub.ij is one of the bit-level cells arrayed sequentially in the j-th memory unit U.sub.j, the j-th memory unit U.sub.j stores information of byte size or word size by the sequence of bit-level cells arrayed sequentially in the j-th memory unit U.sub.j. In the computer system pertaining to the exemplary embodiment of the present invention, the information of byte size or word size arrayed sequentially marches side by side from a previous memory unit to a next memory unit, pari passu. In FIGS. 22(a)-(d), the clock signal is supplied by the clock signal supply line CLOCK so as to swing periodically between the logical levels of “1” and “0” with the clock period TAU.sub.clock, while the clock signal supply line CLOCK serves as a power supply line.
(202) FIGS. 22(a) and (b) show when the logical level of “0” is stored by previous clock signal into the capacitor C.sub.ij, and FIGS. 22(c) and (d) show when the logical level of “1” is stored by previous clock signal into the capacitor C.sub.ij as one of the signal in the information of byte size or word size. As shown in FIG. 22(a), when the signal charge previously stored in the capacitor C.sub.ij is of the logical level of “0”, if the signal of the logical level of “0”, which is stored in a previous bit-level cell M.sub.i(j−1), as one of the signal in the information of byte size or word size to be transferred in a cooperative way, is fed from the previous bit-level cell M.sub.i(j−1) through the inter-unit cell B.sub.ij (the illustration is omitted) to the gate electrode of the first nMOS transistor Q.sub.ij1, the first nMOS transistor Q.sub.ij1 keeps off-state. At this instant of time, because the capacitor C.sub.ij still keep the logical level of “0”, the first nMOS transistor Q.sub.i(j−1)1 transfers equivalently the logical level of “0” to the capacitor C.sub.ij. Then, the output node N.sub.out delivers the signal level of “0”, which is maintained in the capacitor C.sub.ij, to the next bit-level cell as shown in FIG. 22(a).
(203) Similarly, as shown in FIG. 22(b), when the signal charge previously stored in the capacitor C.sub.ij is of the logical level of “0”, if the signal of the logical level of “1” stored in a previous bit-level cell M.sub.i(j−1) is fed from the previous bit-level cell M.sub.i(j−1) through the inter-unit cell B.sub.ij to the gate electrode of the first nMOS transistor Q.sub.ij1, in the timing the signal charge stored in the capacitor C.sub.ij keeps the logical level of “0”, the first nMOS transistor Q.sub.ij1 begins turning-on for transferring the signal of the logical level of “1” stored in the previous bit-level cell M.sub.i(j−1) to the capacitor C.sub.ij so that the logical level of “1” can be stored in the capacitor C.sub.ij, and the output node N.sub.out delivers the signal level of “1” stored in the capacitor C.sub.ij to the next bit-level cell as shown in FIG. 22(b).
(204) On the contrary, as shown in FIG. 22(c), when the signal charge previously stored in the capacitor C.sub.ij is of the logical level of “1”, if the signal of the logical level of “0”, which is stored in a previous bit-level cell M.sub.i(j−1), is fed from the previous bit-level cell M.sub.i(j−1) through the inter-unit cell B.sub.ij to the gate electrode of the first nMOS transistor Q.sub.ij1, after the timing when the signal charge stored in the capacitor C.sub.ij is completely discharged to establish the logical level of “0”, the first nMOS transistor Q.sub.ij1 keeps off-state. Then, the output node N.sub.out delivers the signal level of “0” stored in the capacitor C.sub.ij to the next bit-level cell as shown in FIG. 22(c).
(205) Similarly, as shown in FIG. 22(d), when the signal charge previously stored in the capacitor C.sub.ij is of the logical level of “1”, if the signal of the logical level of “1” stored in a previous bit-level cell M.sub.i(j−1) is fed from the previous bit-level cell M.sub.i(j−1) through the inter-unit cell B.sub.ij to the gate electrode of the first nMOS transistor Q.sub.ij1, after the timing when the signal charge stored in the capacitor C.sub.ij is completely discharged to establish the logical level of “0”, the first nMOS transistor Q.sub.ij1 turns on, and the first nMOS transistor Q.sub.ij1 transfers the signal of the logical level of “1” stored in the previous bit-level cell M.sub.i(j−1) to the capacitor C.sub.ij. Then, the output node N.sub.out delivers the signal level of “1” stored in the capacitor C.sub.ij to the next bit-level cell as shown in FIG. 22(d).
(206) As above-mentioned, with an input signal of “1” provided by the clock signal and another input signal of “1” or “0” provided by the previous bit-level cell M.sub.i(j−1), the bit-level cell M.sub.ij can establish “a marching AND-gate” operations of:
1+1=1
1+0=1,
and with an input signal of “0” provided by the clock signal and another input signal of “1” or “0” provided by the previous bit-level cell M.sub.i(j−1), the bit-level cell M.sub.ij can establish “the marching AND-gate” operations of:
0+1=0
0+0=0.
(207) Therefore, in a gate-level representation of the cell array corresponding to the marching main memory 31 shown in FIG. 4, as shown in FIG. 23, a first cell M.sub.11 allocated at the leftmost side on a first row and connected to an input terminal I.sub.1 encompasses a capacitor C.sub.11 configured to store the information, and a marching AND-gate G.sub.11 having one input terminal connected to the capacitor C.sub.11, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the next marching AND-gate G.sub.21 assigned to the adjacent second cell M.sub.21 on the first row. An example of the response to the waveform of the clock signal is shown in FIG. 7C. When the logical values of “1” of the clock signal is fed to the other input terminal of the marching AND-gate G.sub.11, the information stored in the capacitor C.sub.11 is transferred to a capacitor C.sub.12, assigned to the adjacent second cell M.sub.12, and the capacitor C.sub.12 stores the information. Namely, the second cell M.sub.12 on the first row of the gate-level representation of cell array implementing the marching main memory 31 encompasses the capacitor C.sub.12 and a marching AND-gate G.sub.12, which has one input terminal connected to the capacitor C.sub.12, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the next marching AND-gate G.sub.13 assigned to the adjacent third cell M.sub.13 on the first row. Similarly the third cell M.sub.13 on the first row of the gate-level representation of cell array implementing the marching main memory 31 encompasses a capacitor C.sub.13 configured to store the information, and a marching AND-gate G.sub.13 having one input terminal connected to the capacitor C.sub.13, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the next marching AND-gate assigned to the adjacent fourth cell, although the illustration of the fourth cell is omitted. Therefore, when the logical values of “1” is fed to the other input terminal of the marching AND-gate G.sub.12, the information stored in the capacitor C.sub.12 is transferred to the capacitor C.sub.13, assigned to the third cell M.sub.13, and the capacitor C.sub.13 stores the information, and when the logical values of “1” is fed to the other input terminal of the marching AND-gate G.sub.13, the information stored in the capacitor C.sub.13 is transferred to the capacitor, assigned to the fourth cell. Furthermore, a (n−1)-th cell M.sub.1, n−1 on the first row of the gate-level representation of cell array implementing the marching main memory 31 encompasses a capacitor C.sub.1, n−1 configured to store the information, and a marching AND-gate G.sub.1, n−1 having one input terminal connected to the capacitor C.sub.1, n−1, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the next marching AND-gate G.sub.1n assigned to the adjacent n-th cell M.sub.1n, which is allocated at the rightmost side on the first row and connected to an output terminal O.sub.1. Therefore, each of the cells M.sub.11, M.sub.12, M.sub.13, . . . , M.sub.1, n−1, M.sub.1n stores the information, and transfers the information synchronously with the clock signal, step by step, toward the output terminals O.sub.1, so as to provide the processor 11 with the stored information actively and sequentially so that the ALU 112 can execute the arithmetic and logic operations with the stored information.
(208) Similarly, in a gate-level representation of cell array implementing the marching main memory 31 shown in FIG. 23, a first cell M.sub.21 allocated at the leftmost side on a second row and connected to an input terminal 12 encompasses a capacitor C.sub.21, and a marching AND-gate G.sub.21 having one input terminal connected to the capacitor C.sub.21, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the next marching AND-gate G.sub.21 assigned to the adjacent second cell M.sub.21 on the second row. The second cell M.sub.22 on the second row of the gate-level representation of cell array implementing the marching main memory 31 encompasses the capacitor C.sub.22 and a marching AND-gate G.sub.22, which has one input terminal connected to the capacitor C.sub.22, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the next marching AND-gate G.sub.23 assigned to the adjacent third cell M.sub.23 on the second row. Similarly the third cell M.sub.23 on the second row of the gate-level representation of cell array implementing the marching main memory 31 encompasses a capacitor C.sub.23, and a marching AND-gate G.sub.23 having one input terminal connected to the capacitor C.sub.23, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the next marching AND-gate assigned to the adjacent fourth cell. Furthermore, a (n−1)-th cell M.sub.2, n−1 on the second row of the gate-level representation of cell array implementing the marching main memory 31 encompasses a capacitor C.sub.2, n−1, and a marching AND-gate G.sub.2, n−1 having one input terminal connected to the capacitor C.sub.2, n−1, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the next marching AND-gate G.sub.1n assigned to the adjacent n-th cell M.sub.1n, which is allocated at the rightmost side on the second row and connected to an output terminal O.sub.1. Therefore, each of the cells M.sub.21, M.sub.22, M.sub.23, . . . , M.sub.2, n−1, M.sub.2n on the second row stores the information, and transfers the information synchronously with the clock signal, step by step, toward the output terminals O.sub.1, so as to provide the processor 11 with the stored information actively and sequentially so that the ALU 112 can execute the arithmetic and logic operations with the stored information.
(209) On a third row, a first cell M.sub.31 allocated at the leftmost side and connected to an input terminal 13, a second cell M.sub.32 adjacent to the first cell M.sub.31, a third cell M.sub.33 adjacent to the second cell M.sub.32, . . . , a (n−1)-th cell M.sub.3, n−1, and an n-th cell M.sub.3n, which is allocated at the rightmost side on the third row and connected to an output terminal O.sub.3 are aligned. And, each of the cells M.sub.31, M.sub.32, M.sub.33, . . . , M.sub.3, n−1, M.sub.3n on the third row stores the information, and transfers the information synchronously with the clock signal, step by step, toward the output terminals O.sub.3, so as to provide the processor 11 with the stored information actively and sequentially so that the ALU 112 can execute the arithmetic and logic operations with the stored information.
(210) On a (m−1)-th row, a first cell M.sub.(m−1),1 allocated at the leftmost side and connected to an input terminal a second cell M.sub.(m−1),2 adjacent to the first cell M.sub.(m−1), n−1, a third cell M.sub.(m−1),3 adjacent to the second cell M.sub.(m−1),2, . . . , a (n−1)-th cell M.sub.(m−1), n−1, and an n-th cell M.sub.(m−1),n, which is allocated at the rightmost side on the (m−1)-th row and connected to an output terminal O.sub.m−1, are aligned. And, each of the cells M.sub.(m−1),1, M.sub.(m−1),2, M.sub.(m−1),3, . . . , M.sub.(m−1), n−1, M.sub.(m−1),n on the (m−1)-th row stores the information, and transfers the information synchronously with the clock signal, step by step, toward the output terminals O.sub.m−1, so as to provide the processor 11 with the stored information actively and sequentially so that the ALU 112 can execute the arithmetic and logic operations with the stored information.
(211) On a m-th row, a first cell M.sub.m1 allocated at the leftmost side and connected to an input terminal I.sub.m−1, a second cell M.sub.m2 adjacent to the first cell M.sub.m1, a third cell M.sub.m3 adjacent to the second cell M.sub.m2, . . . , a (n−1)-th cell M.sub.m(n−1), and an n-th cell M.sub.mn, which is allocated at the rightmost side on the m-th row and connected to an output terminal O.sub.m, are aligned. And, each of the cells M.sub.m1, M.sub.m2, M.sub.m3, . . . , M.sub.m(n−1), M.sub.mn on the m-th row stores the information, and transfers the information synchronously with the clock signal, step by step, toward the output terminals O.sub.m, so as to provide the processor 11 with the stored information actively and sequentially so that the ALU 112 can execute the arithmetic and logic operations with the stored information.
(212) Although one of the examples of the transistor-level configurations of the marching AND-gate G.sub.ij is shown in FIG. 6, there are various circuit configurations to implement the marching AND-gate, which can be applied to the cell array implementing the marching main memory 31. Another example of the marching AND-gate G.sub.ij, which can be applied to the cell array implementing the marching main memory 31, may be a configuration encompassing a CMOS NAND gate and a CMOS inverter connected to the output terminal of the CMOS NAND gate. Because the CMOS NAND gate requires two nMOS transistors and two pMOS transistors, and the CMOS inverter requires one nMOS transistor and one pMOS transistor, the configuration encompassing the CMOS NAND gate and the CMOS inverter requires six transistors. Furthermore, the marching AND-gate G.sub.ij can be implemented by other circuit configurations such as resistor-transistor logics, or by various semiconductor elements, magnetic elements, superconductor elements, or single quantum elements, etc. which has a function of AND logic.
(213) As shown in FIG. 23, the gate-level representation of cell array implementing the marching main memory 31 is as simple as the configuration of DRAM, where each of the bit-level cells M.sub.ij (i=1 to m; j=1 to n) is represented by one capacitor and one marching AND-gate. Each of the vertical sequence of marching AND-gates G.sub.11, G.sub.21, G.sub.31, . . . , G.sub.m−1,1, G.sub.m1 implementing the first memory unit U.sub.1 shifts the sequence of signals from input terminals I.sub.1, I.sub.2, I.sub.3, . . . , I.sub.n−1, I.sub.n to right along row-direction, or horizontal direction, based on clocks as shown in FIG. 7C. And, each of the vertical sequence of marching AND-gates G.sub.12, G.sub.22, G.sub.32, . . . , G.sub.m−1,2, G.sub.m2 implementing the second memory unit U.sub.2 shifts the sequence of signals of word size from left to right along row-direction based on clocks, each of the vertical sequence of marching AND-gates G.sub.13, G.sub.23, G.sub.33, . . . , G.sub.m−1,3, G.sub.m3 implementing the third memory unit U.sub.3 shifts the sequence of signals of word size from left to right along row-direction based on clocks, . . . , each of the vertical sequence of marching AND-gates G.sub.1,n−1, G.sub.2,n−1, G.sub.3,n−1, . . . , G.sub.m−1,n−1, G.sub.m,n−1 implementing the (n−1)-th memory unit U.sub.n−1 shifts the sequence of signals of word size from left to right along row-direction based on clocks, and each of the vertical sequence of marching AND-gates G.sub.1,n, G.sub.2,n, G.sub.3,n, . . . , G.sub.m−1,n, G.sub.m,n implementing the n-th memory unit U.sub.n shifts the sequence of signals of word size from left to right to the output terminals O.sub.1, O.sub.2, O.sub.3, . . . , O.sub.n−1, O.sub.n based on clocks as shown in FIG. 7C. Especially, the time delay t.sub.d1, t.sub.d2 in each of marching AND-gate G.sub.ij (i=1 to m; j=1 to n) is significant to correctly perform the marching-shift actions in every memory units in the marching main memory 31 successively.
Reverse-Directional Marching Main Memory
(214) Although FIGS. 3-23 show the marching main memory which stores the information in each of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n and transfers the information synchronously with the clock signal, step by step, from input terminal toward the output terminal, FIG. 24 shows another marching main memory.
(215) In FIG. 24, each of the memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n stores the information including word size of data or instructions, and transfers in the reverse direction the information synchronously with the clock signal, step by step, toward the output terminals, provided from the processor 11 with the resultant data executed in the ALU 112.
(216) FIG. 25(a) shows an array of i-th row of the m*n matrix (here, “m” is an integer determined by word size) in a cell-level representation of the another marching main memory shown in FIG. 24, which stores the information of bit level in each of cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,n−1, M.sub.i,n and transfers the information synchronously with the clock signal, step by step in the reverse direction to the marching main memory shown in FIGS. 3-23, namely from the output terminal OUT toward the input terminal IN.
(217) As shown in FIG. 25(a), in a reverse-directional marching main memory, a bit-level cell M.sub.in of the n-th column and on the i-th row, allocated at the rightmost side on the i-th row and connected to an input terminal IN encompasses a first nMOS transistor Q.sub.in1 having a drain electrode connected to a clock signal supply line through a first delay element D.sub.in1 and a gate electrode connected to the input terminal IN through a second delay element D.sub.in2; a second nMOS transistor Q.sub.in2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.in1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.in configured to store the information of the bit-level cell M.sub.in, connected in parallel with the second nMOS transistor Q.sub.in2, wherein an output node connecting the source electrode of the first nMOS transistor Q.sub.in1 and the drain electrode of the second nMOS transistor Q.sub.in2 serves as an output terminal of the bit-level cell M.sub.in, configured to transfer the signal stored in the capacitor C.sub.in to the next bit-level cell M.sub.i2.
(218) As shown in FIG. 25(b), the clock signal swings periodically between the logical levels of “1” and “0”, with a predetermined clock period TAU.sub.clock, and when the clock signal becomes the logical level of “1”, the second nMOS transistor Q.sub.in2 begins to discharge the signal charge, which is already stored in the capacitor C.sub.in at a previous clock cycle. After the clock signal of the logical level of “1” is applied and the signal charge stored in the capacitor C.sub.in is completely discharged to become the logical level of “0”, the first nMOS transistor Q.sub.in1 becomes active as the transfer transistor, delayed by the predetermined delay time to determined by the first delay element D.sub.in1. The delay time to is set to be equal to ¼TAU.sub.clock in an exemplary embodiment. Thereafter, when the signal is fed from the input terminal IN to the gate electrode of the first nMOS transistor Q.sub.in1, the first nMOS transistor Q.sub.in1 transfers the signal stored in the previous bit-level cell M.sub.i2, further delayed by the predetermined delay time t.sub.d2 determined by the second delay element D.sub.in2 to the capacitor C.sub.in. For example, if the logical level of “1” is fed from the input terminal IN to the gate electrode of the first nMOS transistor Q.sub.in1, the first nMOS transistor Q.sub.in1 becomes conductive state, and the logical level of “1” is stored in the capacitor C.sub.in. On the other hand, if the logical level of “0” is fed from the input terminal IN to the gate electrode of the first nMOS transistor Q.sub.in1, the first nMOS transistor Q.sub.in1 keeps cut-off state, and the logical level of “0” is maintained in the capacitor C.sub.in. Therefore, the bit-level cell M.sub.in can establish “a marching AND-gate” operation. The delay time t.sub.d2 shall be longer than the delay time t.sub.d1, and the delay time t.sub.d2 is set to be equal to ½TAU.sub.clock in an exemplary embodiment. When the clock signal becomes the logical level of “0” at a time when time proceeds ½TAU.sub.clock, the output node connecting the source electrodes of the first nMOS transistor Q.sub.in1 and the drain electrodes of the second nMOS transistor Q.sub.in2 cannot deliver the signals, which are entered to the gate electrodes of the first nMOS transistor Q.sub.in1, further to the next bit-level cell M.sub.i2, at a time when time proceeds ½TAU.sub.clock, as the signals is blocked to be transferred to the gate electrodes of the next first nMOS transistor Q.sub.i21 delayed by the delay time t.sub.d2=½TAU.sub.clock determined by the second delay element D.sub.i22. As shown in FIG. 25(a), in a reverse-directional marching main memory, a bit-level cell M.sub.i(n−1) of the (n−1)-th column and on the i-th row, allocated at the second right side on the i-th row, encompasses a first nMOS transistor Q.sub.i(n−1)1 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.i(n−1)1 and a gate electrode connected to the output terminal of the bit-level cell M.sub.in through a second delay element D.sub.i(n−1)2; a second nMOS transistor Q.sub.i(n−1)2 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.i(n−1)1, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.i(n−1) configured to store the information of the bit-level cell M.sub.i(n−1), connected in parallel with the second nMOS transistor Q.sub.i(n−1)2. When the clock signal becomes the logical level of “1”, the second nMOS transistor Q.sub.i(n−1)2 begins to discharge the signal charge, which is already stored in the capacitor C.sub.i(n−1) at a previous clock cycle. As shown in FIG. 25(b), and the logical values of “1” is kept from time “t” to time “t+1” in the capacitor C.sub.i(n−1). After the clock signal of the logical level of “1” is applied and the signal charge stored in the capacitor C.sub.i(n−1) is completely discharged to becomes the logical level of “0”, the first nMOS transistor Q.sub.i(n−1)1 becomes active as the transfer transistor, delayed by the delay time to determined by the first delay element D.sub.i(n−1)1. Thereafter, when the signal is fed from the output terminal of the bit-level cell M.sub.in to the gate electrode of the first nMOS transistor Q.sub.i(n−1)1, the first nMOS transistor Q.sub.i(n−1)1 transfers the signal stored in the previous bit-level cell M.sub.in, further delayed by the delay time t.sub.d2 determined by the second delay element D.sub.i(n−1)2 to the capacitor C.sub.i(n−1). When the clock signal becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrodes of the first nMOS transistor Q.sub.i(n−1)1 and the drain electrodes of the second nMOS transistor Q.sub.i(n−1)2 cannot deliver the signals, which are entered to the gate electrodes of the first nMOS transistor Q.sub.i(n−1)1, further to the next bit-level cell M.sub.i(n−2), at a time when time proceeds 1/2TAU.sub.clock, as the signals is blocked to be transferred to the gate electrodes of the next first nMOS transistor Q.sub.i(n−2)1 (illustration is omitted) delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second delay element D.sub.i(n−2)2 (illustration is omitted).
(219) Similarly the third cell M.sub.i3 from the left, on the i-th row, of the reverse-directional marching main memory encompasses a first nMOS transistor Q.sub.i31 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.i31 and a gate electrode connected to the output terminal of the bit-level cell M.sub.i4 (illustration is omitted) through a second delay element D.sub.i32; a second nMOS transistor Q.sub.i32 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.i31, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.i3 configured to store the information of the bit-level cell M.sub.i3, connected in parallel with the second nMOS transistor Q.sub.i32. When the clock signal becomes the logical level of “1”, the second nMOS transistor Q.sub.i32 begins to discharge the signal charge, which is already stored in the capacitor C.sub.i3 at a previous clock cycle. After the clock signal of the logical level of “1” is applied and the signal charge stored in the capacitor C.sub.i3 is completely discharged to becomes the logical level of “0”, the first nMOS transistor Q.sub.i31 becomes active as the transfer transistor, delayed by the delay time to determined by the first delay element D.sub.i31. Thereafter, when the signal is fed from the output terminal of the bit-level cell M.sub.i4 to the gate electrode of the first nMOS transistor Q.sub.i31, the first nMOS transistor Q.sub.i31 transfers the signal stored in the previous bit-level cell M.sub.in, further delayed by the delay time t.sub.d2 determined by the second delay element D.sub.i32 to the capacitor C.sub.i3. When the clock signal becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrodes of the first nMOS transistor Q.sub.i31 and the drain electrodes of the second nMOS transistor Q.sub.i32 cannot deliver the signals, which are entered to the gate electrodes of the first nMOS transistor Q.sub.i31, further to the next bit-level cell M.sub.i2, at a time when time proceeds 1/2TAU.sub.clock, as the signals is blocked to be transferred to the gate electrodes of the next first nMOS transistor Q.sub.i21 delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second delay element D.sub.i22
(220) As shown in FIG. 25(a), in a reverse-directional marching main memory, a bit-level cell M.sub.i2 of the second column from the left, and on the i-th row, encompasses a first nMOS transistor Q.sub.i21 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.i21 and a gate electrode connected to the output terminal of the bit-level cell M.sub.i3 through a second delay element D.sub.i22; a second nMOS transistor Q.sub.i22 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.i21, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.i2 configured to store the information of the bit-level cell M.sub.i2, connected in parallel with the second nMOS transistor Q.sub.i22. When the clock signal becomes the logical level of “1”, the second nMOS transistor Q.sub.i22 begins to discharge the signal charge, which is already stored in the capacitor C.sub.i2 at a previous clock cycle. After the clock signal of the logical level of “1” is applied and the signal charge stored in the capacitor C.sub.i2 is completely discharged to becomes the logical level of “0”, the first nMOS transistor Q.sub.i21 becomes active as the transfer transistor, delayed by the delay time t.sub.d1 determined by the first delay element D.sub.i21. Thereafter, when the signal is fed from the output terminal of the bit-level cell M.sub.i3 to the gate electrode of the first nMOS transistor Q.sub.i21, the first nMOS transistor Q.sub.i21 transfers the signal stored in the previous bit-level cell M.sub.i3, further delayed by the delay time t.sub.d2 determined by the second delay element D.sub.i22 to the capacitor C.sub.i2. When the clock signal becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first nMOS transistor Q.sub.i21 and the drain electrode of the second nMOS transistor Q.sub.i22 cannot deliver the signal, which is entered to the gate electrode of the first nMOS transistor Q.sub.i21, further to the next bit-level cell M.sub.i1, at a time when time proceeds 1/2TAU.sub.clock, as the signal is blocked to be transferred to the gate electrode of the next first nMOS transistor Q.sub.i11 delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second delay element D.sub.i12.
(221) As shown in FIG. 25(a), in a reverse-directional marching main memory, a bit-level cell M.sub.i1 of the first column and on the i-th row, which is allocated at the leftmost side on the i-th row and connected to an output terminal OUT, encompasses a first nMOS transistor Q.sub.i11 having a drain electrode connected to the clock signal supply line through a first delay element D.sub.i11 and a gate electrode connected to the output terminal of the bit-level cell M.sub.i2 through a second delay element D.sub.i12; a second nMOS transistor Q.sub.i12 having a drain electrode connected to a source electrode of the first nMOS transistor Q.sub.i11, a gate electrode connected to the clock signal supply line, and a source electrode connected to the ground potential; and a capacitor C.sub.i1 configured to store the information of the bit-level cell M.sub.i1, connected in parallel with the second nMOS transistor Q.sub.i12. When the clock signal becomes the logical level of “1”, the second nMOS transistor Q.sub.i12 begins to discharge the signal charge, which is already stored in the capacitor C.sub.i1 at a previous clock cycle. After the clock signal of the logical level of “1” is applied and the signal charge stored in the capacitor C.sub.i1 is completely discharged to becomes the logical level of “0”, the first nMOS transistor Q.sub.i11 becomes active as the transfer transistor, delayed by the delay time t.sub.d1 determined by the first delay element D.sub.i11. Thereafter, when the signal is fed from the output terminal of the bit-level cell M.sub.i2 to the gate electrode of the first nMOS transistor Q.sub.i11, the first nMOS transistor Q.sub.i11 transfers the signal stored in the previous bit-level cell M.sub.i2, further delayed by the delay time t.sub.d2 determined by the second delay element D.sub.i12 to the capacitor C.sub.i1. The output node connecting the source electrode of the first nMOS transistor Q.sub.i11 and the drain electrode of the second nMOS transistor Q.sub.i12 delivers the signal stored in the capacitor C.sub.i1 to the output terminal OUT.
(222) According to the reverse-directional one-dimensional marching main memory 31 of the exemplary embodiment shown in FIGS. 24. 25(a) and 25(b), addressing to each of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n disappears and required information is heading for its destination unit connected to the edge of the memory. The mechanism of accessing the reverse-directional one-dimensional marching main memory 31 of the exemplary embodiment is truly alternative to existing memory schemes that are starting from the addressing mode to read/write information. Therefore, according to the reverse-directional one-dimensional marching main memory 31 of the exemplary embodiment, the memory-accessing without addressing mode is quite simpler than existing memory schemes.
(223) As above mentioned, the bit-level cell M.sub.ij can establish “a marching AND-gate” operation. Therefore, as shown in FIG. 26, in a gate-level representation of the cell array corresponding to the reverse-directional marching main memory 31 shown in FIG. 25(a), the n-th bit-level cell M.sub.i,n allocated at the rightmost side on the i-th row and connected to an input terminal IN encompasses a capacitor C.sub.in configured to store the information, and a marching AND-gate G.sub.in having one input terminal connected to the capacitor C.sub.in, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the preceding marching AND-gate G.sub.in−1 assigned to the adjacent (n−1)-th bit-level cell M.sub.i,n−1 on the i-th row. When the logical values of “1” is fed to the other input terminal of the marching AND-gate G.sub.n, the information stored in the capacitor C.sub.in is transferred to a capacitor C.sub.i,n−1, assigned to the adjacent (n−1)-th bit-level cell on the i-th row, and the capacitor C.sub.i,n−1 stores the information. Namely, the (n−1)-th bit-level cell on the i-th row of the reverse-directional marching main memory encompasses the capacitor C.sub.i,n−1 and a marching AND-gate G.sub.i,n−1, which has one input terminal connected to the capacitor C.sub.i,n−1, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the preceding marching AND-gate G.sub.i,n−2 assigned to the adjacent third bit-level cell M.sub.i,n−2 (illustration is omitted).
(224) Similarly the third bit-level cell M.sub.i3 on the i-th row of the reverse-directional marching main memory encompasses a capacitor C.sub.i3 configured to store the information, and a marching AND-gate G.sub.i3 having one input terminal connected to the capacitor C.sub.i3, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the preceding marching AND-gate G.sub.i2 assigned to the adjacent second bit-level cell M.sub.i2. When the logical values of “1” is fed to the other input terminal of the marching AND-gate G.sub.i3, the information stored in the capacitor C.sub.i3 is transferred to the capacitor C.sub.i2, assigned to the second bit-level cell M.sub.i2, and the capacitor C.sub.i2 stores the information.
(225) Furthermore, the second bit-level cell M.sub.i2 on the i-th row of the reverse-directional marching main memory encompasses the capacitor C.sub.i2 configured to store the information, and the marching AND-gate G.sub.i2 having one input terminal connected to the capacitor C.sub.i2, the other input terminal configured to be supplied with the clock signal, and an output terminal connected to one input terminal of the preceding marching AND-gate G.sub.i1 assigned to the adjacent first bit-level cell M.sub.i1, which is allocated at the leftmost side on the i-th row and connected to an output terminal OUT.
(226) The concept of marching main memory 31 is shown in FIG. 27. This is different from existing computer memory, because the marching main memory 31 is purposely designed with functionality of storage and conveyance of information/data through all of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n in the marching main memory 31. Marching memory supplies information/data to the processor (CPU) 11 at the same speed of the processor 11. As shown in the time-domain relationship of FIG. 9, the memory unit streaming time T.sub.mus required for transferring information/data through one memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, in the marching main memory 31 is equal to the clock cycle T.sub.cc in the processor 11. The marching main memory 31 stores information/data in each of the memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, and transfers synchronously with the clock signal, step by step, toward the output terminals, so as to provide the processor 11 with the stored information/data so that the arithmetic logic unit 112 can execute the arithmetic and logic operations with the stored information/data.
(227) As shown in FIG. 28, marching memory structure 3 includes the marching main memory 31 of the exemplary embodiment of the present invention. The term “marching memory structure 3” means a generic concept of the memory structure including a marching-instruction register file (RF) 22a and a marching-data register file (RF) 22b connected to the ALU 112, which will be explained further in the following second embodiment, and a marching-instruction cache memory 21a and a marching-data cache memory 21b, which will be explained further in the following exemplary embodiments, in addition to the marching main memory 31.
(228) FIG. 29(a) shows a forward data-stream S.sub.f flowing from the marching memory structure 3 to the processor 11 and backward data-stream (reverse data-stream) S.sub.b flowing from the processor 11 to the marching memory structure 3, and FIG. 29(b) shows bandwidths established between the marching memory structure 3 and the processor 11 assuming that the memory unit streaming time T.sub.mus in the marching memory structure 3 is equal to the clock cycle T.sub.cc of the processor 11.
(229) The scheme of the marching main memory 31 may be considered to be analogous to a magnetic tape system shown in FIG. 30(a), which encompasses a magnetic tape 503, a take-up reel 502 for winding the magnetic tape 503, a supply reel 501 for rewinding and releasing the magnetic tape 503, a read/write header 504 for reading information/data from the magnetic tape 503 or writing information/data to the magnetic tape 503, and a processor 11 connected to the read/write header 504. As the take-up reel 502 winds the magnetic tape 503, which is released from the supply reel 501, the magnetic tape 503 moves at high speed from the supply reel 501 toward the take-up reel 502, and information/data stored on the magnetic tape 503, being transferred with the movement of the magnetic tape 503 at high speed, are read by the read/write header 504. And the processor 11 connected to the read/write header 504 can execute arithmetic and logic operations with information/data read from the magnetic tape 503. Alternatively, the results of the processing in the processor 11 are sent out to the magnetic tape 503 through the read/write header 504.
(230) If the architecture of the magnetic tape system shown in FIG. 30(a) is implemented by semiconductor technology, such that one images an extremely high-speed magnetic tape system virtually established on semiconductor silicon chip as shown in FIG. 30(b), the extremely high-speed magnetic tape system shown in FIG. 30(a) may correspond to a net marching memory structure 3, including the marching main memory 31 of the present invention. The net marching memory structure 3 shown in FIG. 30(b) stores information/data in each of the memory units on the silicon chip and transfers synchronously with the clock signal, step by step, toward the take-up reel 502, so as to provide the processor 11 with the stored information/data actively and sequentially so that the processor 11 can execute the arithmetic and logic operations with the stored information/data, and the results of the processing in the processor 11 are sent out to the net marching memory structure 3.
Bidirectional Marching Main Memory
(231) As shown in FIGS. 31(a)-(c), the exemplary embodiment of the marching main memory 31, can achieve bidirectional transferring of information/data. FIG. 31(a) shows a forward marching behavior of information/data, in which information/data marches (shifts) side by side toward right-hand direction (forward direction) in a one-dimensional marching main memory 31. FIG. 31(b) shows a staying state of the one-dimensional marching main memory 31. FIG. 31(c) shows a reverse-marching behavior of information/data (a backward marching behavior), in which information/data marches (shifts) side by side toward left-hand direction (reverse direction) in the one-dimensional marching main memory 31.
(232) FIGS. 32 and 33 show two examples of the representative arrays of i-th row of the m*n matrix (here, “m” is an integer determined by word size) in a transistor-level representation of the cell array for the bidirectional marching main memory 31, respectively, which can achieve the bidirectional behavior shown in FIGS. 31(a)-(c). The bidirectional marching main memory 31 stores the information/data of bit level in each of cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,n−1, M.sub.i,n and transfers bi-directionally the information/data synchronously with the clock signal, step by step in the forward direction and/or reverse direction (backward direction) between a first I/O selector 512 and a second I/O selector 513.
(233) In FIGS. 32 and 33, each of the cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,n−1, M.sub.i,n is assigned in memory unit U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, respectively. That is the cell M.sub.i1 is assigned as the first bit-level cell in the first memory unit U.sub.1, the first memory unit U.sub.1 stores information of byte size or word size by the sequence of bit-level cells arrayed in the first memory unit U.sub.1. Similarly, the cell M.sub.i2 is assigned as the second bit-level cell in the second memory unit U.sub.2, the cell M.sub.i3 is assigned as the third bit-level cell in the third memory unit U.sub.3, . . . , the cell M.sub.i,n−1 is assigned as the (n−1)-th bit-level cell in the (n−1)-th memory unit U.sub.n−1, and the cell M.sub.i,n is assigned as the n-th bit-level cell in the n-th memory unit U.sub.n. And the memory units U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n stores information of byte size or word size by the sequence of bit-level cells arrayed in the memory unit U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, respectively. The bidirectional marching main memory 31 stores the information/data of byte size or word size in each of cells U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n and transfers bi-directionally the information/data of byte size or word size synchronously with the clock signal, pari passu, in the forward direction and/or reverse direction (backward direction) between a first I/O selector 512 and a second I/O selector 513.
(234) A clock selector 511 selects a first clock signal supply line CL1 and a second clock signal supply line CL2. The first clock signal supply line CL1 drives the forward data-stream, and the second clock signal supply line CL2 drives the backward data-stream, and each of the first clock signal supply line CL1 and the second clock signal supply line CL2 has logical values of “1” and “0”.
(235) In the transistor-level representation of the cell array implementing the marching main memory 31 shown in FIG. 32, a first bit-level cell M.sub.i1 allocated at the leftmost side on i-th row, being connected to a first I/O selector 512, encompasses a first forward nMOS transistor Q.sub.1i11f having a drain electrode connected to a first clock signal supply line CL1 through a first forward delay element D.sub.i11f and a gate electrode connected to the first I/O selector 512 through a second forward delay element D.sub.i12f; a second forward nMOS transistor Q.sub.i12f having a drain electrode connected to a source electrode of the first forward nMOS transistor Q.sub.i11f, a gate electrode connected to the first clock signal supply line, and a source electrode connected to the ground potential; and a forward capacitor C.sub.i1f configured to store the forward information/data of the cell connected in parallel with the second forward nMOS transistor Q.sub.i12f, wherein an output node connecting the source electrode of the first forward nMOS transistor Q.sub.i11f and the drain electrode of the second forward nMOS transistor Q.sub.i12f serves as a forward output terminal of the cell configured to transfer the signal stored in the forward capacitor C.sub.i1f to the next bit-level cell M.sub.i2. The first bit-level cell M.sub.i1 further encompasses a first backward nMOS transistor Q.sub.i11g having a drain electrode connected to a second clock signal supply line through a first backward delay element D.sub.i11g and a gate electrode connected to the backward output terminal of the bit-level cell M.sub.i2 through a second backward delay element D.sub.i12g; a second backward nMOS transistor Q.sub.i12g having a drain electrode connected to a source electrode of the first backward nMOS transistor Q.sub.i11g, a gate electrode connected to the second clock signal supply line, and a source electrode connected to the ground potential; and a backward capacitor C.sub.i1g configured to store the backward information/data of the cell connected in parallel with the second backward nMOS transistor Q.sub.i12g, wherein an output node connecting the source electrode of the first backward nMOS transistor Q.sub.i11g and the drain electrode of the second backward nMOS transistor Q.sub.i12g serves as a backward output terminal of the cell M.sub.i1, configured to transfer the signal stored in the backward capacitor C.sub.i1g to the first I/O selector 512.
(236) A second bit-level cell M.sub.i2 allocated at the second from the left side on i-th row, being connected to the bit-level cell M.sub.i1, encompasses a first forward nMOS transistor Q.sub.i21f having a drain electrode connected to the first clock signal supply line CL1 through a first forward delay element D.sub.i21f and a gate electrode connected to the forward output terminal of the bit-level cell nu through a second forward delay element D.sub.i22f; a second forward nMOS transistor Q.sub.i22f having a drain electrode connected to a source electrode of the first forward nMOS transistor Q.sub.i21f, a gate electrode connected to the first clock signal supply line CL1, and a source electrode connected to the ground potential; and a forward capacitor C.sub.i2f configured to store the forward information/data of the cell M.sub.i2, connected in parallel with the second forward nMOS transistor Q.sub.i22f, wherein an output node connecting the source electrode of the first forward nMOS transistor Q.sub.i21f and the drain electrode of the second forward nMOS transistor Q.sub.i22f serves as a forward output terminal of the cell M.sub.i2, configured to transfer the signal stored in the forward capacitor C.sub.i2f to the next bit-level cell M.sub.i3. The second bit-level cell M.sub.i2 further encompasses a first backward nMOS transistor Q.sub.i21g having a drain electrode connected to the second clock signal supply line CL2 through a first backward delay element D.sub.i21g and a gate electrode connected to the backward output terminal of the bit-level cell M.sub.i3 through a second backward delay element D.sub.i22g; a second backward nMOS transistor Q.sub.i22g having a drain electrode connected to a source electrode of the first backward nMOS transistor Q.sub.i21g, a gate electrode connected to the second clock signal supply line CL2, and a source electrode connected to the ground potential; and a backward capacitor C.sub.i2g configured to store the backward information/data of the cell M.sub.i2, connected in parallel with the second backward nMOS transistor Q.sub.i22g, wherein an output node connecting the source electrode of the first backward nMOS transistor Q.sub.i21g and the drain electrode of the second backward nMOS transistor Q.sub.i22g serves as a backward output terminal of the cell M.sub.i2, configured to transfer the signal stored in the backward capacitor C.sub.i2g to the next bit-level cell M.sub.i1.
(237) A third bit-level cell M.sub.i3 allocated at the third from the left side on i-th row, being connected to the bit-level cell M.sub.i2, encompasses a first forward nMOS transistor Q.sub.i31f having a drain electrode connected to the first clock signal supply line CL1 through a first forward delay element D.sub.i31f and a gate electrode connected to the forward output terminal of the bit-level cell M.sub.i2 through a second forward delay element D.sub.i32f; a second forward nMOS transistor Q.sub.i32f having a drain electrode connected to a source electrode of the first forward nMOS transistor Q.sub.i31f, a gate electrode connected to the first clock signal supply line CL1, and a source electrode connected to the ground potential; and a forward capacitor C.sub.i3f configured to store the forward information/data of the cell M.sub.i3, connected in parallel with the second forward nMOS transistor Q.sub.i32f, wherein an output node connecting the source electrode of the first forward nMOS transistor Q.sub.i31f and the drain electrode of the second forward nMOS transistor Q.sub.i32f serves as a forward output terminal of the cell M.sub.i3, configured to transfer the signal stored in the forward capacitor C.sub.i3f to the next bit-level cell M.sub.i4 (illustration is omitted). The third bit-level cell M.sub.i3 further encompasses a first backward nMOS transistor Q.sub.i31g having a drain electrode connected to the second clock signal supply line CL2 through a first backward delay element D.sub.i31g and a gate electrode connected to the backward output terminal of the bit-level cell M.sub.i4 through a second backward delay element D.sub.i32g; a second backward nMOS transistor Q.sub.i32g having a drain electrode connected to a source electrode of the first backward nMOS transistor Q.sub.i31g, a gate electrode connected to the second clock signal supply line CL2, and a source electrode connected to the ground potential; and a backward capacitor C.sub.i3g configured to store the backward information/data of the cell M.sub.i3, connected in parallel with the second backward nMOS transistor Q.sub.i32g, wherein an output node connecting the source electrode of the first backward nMOS transistor Q.sub.i31g and the drain electrode of the second backward nMOS transistor Q.sub.i32g serves as a backward output terminal of the cell M.sub.i3, configured to transfer the signal stored in the backward capacitor C.sub.i3g to the next bit-level cell M.sub.i2.
(238) A (n−1)-th bit-level cell M.sub.i(n−1) allocated at the second (n−1)-th from the left side on i-th row, encompasses a first forward nMOS transistor Q.sub.i(n−1)1f having a drain electrode connected to the first clock signal supply line CL1 through a first forward delay element D.sub.i(n−1)1f and a gate electrode connected to the forward output terminal of the bit-level cell M.sub.i(n−2) (illustration is omitted) through a second forward delay element D.sub.i(n−1)2f; a second forward nMOS transistor Q.sub.i(n−1)2f having a drain electrode connected to a source electrode of the first forward nMOS transistor Q.sub.i(n−1)1f, a gate electrode connected to the first clock signal supply line CL1, and a source electrode connected to the ground potential; and a forward capacitor C.sub.i(n−1)f configured to store the forward information/data of the cell M.sub.i(n−1), connected in parallel with the second forward nMOS transistor Q.sub.(i(n−1)2f, wherein an output node connecting the source electrode of the first forward nMOS transistor Q.sub.i(n−1)1f and the drain electrode of the second forward nMOS transistor Q.sub.i(n−1)2f serves as a forward output terminal of the cell M.sub.i(n−1), configured to transfer the signal stored in the forward capacitor C.sub.i(n−1)f to the next bit-level cell M.sub.in. The (n−1)-th bit-level cell M.sub.i(n−1) further encompasses a first backward nMOS transistor Q.sub.i(n−1)1g having a drain electrode connected to the second clock signal supply line CL2 through a first backward delay element D.sub.i(n−1)1g and a gate electrode connected to the backward output terminal of next bit-level cell M.sub.in through a second backward delay element D.sub.i(n−1)2g; a second backward nMOS transistor Q.sub.i(n−1)2g having a drain electrode connected to a source electrode of the first backward nMOS transistor Q.sub.i(n−1)1g, a gate electrode connected to the second clock signal supply line CL2, and a source electrode connected to the ground potential; and a backward capacitor C.sub.i(n−1)g configured to store the backward information/data of the cell M.sub.i(n−1), connected in parallel with the second backward nMOS transistor Q.sub.i(n−1)2g, wherein an output node connecting the source electrode of the first backward nMOS transistor Q.sub.i(n−1)1g and the drain electrode of the second backward nMOS transistor Q.sub.i(n−1)2g serves as a backward output terminal of the cell M.sub.i(n−1), configured to transfer the signal stored in the backward capacitor C.sub.i(n−1)g to the next bit-level cell M.sub.i(n−2) (illustration is omitted).
(239) A n-th bit-level cell M.sub.in allocated at the rightmost side on i-th row, encompasses a first forward nMOS transistor Q.sub.in1f having a drain electrode connected to the first clock signal supply line CL1 through a first forward delay element D.sub.in1f and a gate electrode connected to the forward output terminal of the bit-level cell M.sub.i(n−1) through a second forward delay element D.sub.in2f; a second forward nMOS transistor Q.sub.in2f having a drain electrode connected to a source electrode of the first forward nMOS transistor Q.sub.in1f, a gate electrode connected to the first clock signal supply line CL1, and a source electrode connected to the ground potential; and a forward capacitor C.sub.inf configured to store the forward information/data of the cell M.sub.in, connected in parallel with the second forward nMOS transistor Q.sub.in2f, wherein an output node connecting the source electrode of the first forward nMOS transistor Q.sub.in1f and the drain electrode of the second forward nMOS transistor Q.sub.in2f serves as a forward output terminal of the cell M.sub.in, configured to transfer the signal stored in the forward capacitor C.sub.inf to the second I/O selector 513. The n-th bit-level cell M.sub.in further encompasses a first backward nMOS transistor Q.sub.in1g having a drain electrode connected to the second clock signal supply line CL2 through a first backward delay element D.sub.in1g and a gate electrode connected to the second I/O selector 513 through a second backward delay element D.sub.in2g; a second backward nMOS transistor Q.sub.in2g having a drain electrode connected to a source electrode of the first backward nMOS transistor Q.sub.in1g, a gate electrode connected to the second clock signal supply line CL2, and a source electrode connected to the ground potential; and a backward capacitor C.sub.ing configured to store the backward information/data of the cell M.sub.in, connected in parallel with the second backward nMOS transistor Q.sub.in2g, wherein an output node connecting the source electrode of the first backward nMOS transistor Q.sub.in1g and the drain electrode of the second backward nMOS transistor Q.sub.in2g serves as a backward output terminal of the cell M.sub.in, configured to transfer the signal stored in the backward capacitor C.sub.ing to the next bit-level cell M.sub.i(n−1).
(240) When the clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “1”, the second forward nMOS transistor Q.sub.i12f in the first memory unit U.sub.1 begins to discharge the signal charge, which is already stored in the forward capacitor C.sub.i1f in the first memory unit U.sub.1 at a previous clock cycle. After the clock signal of the logical level of “1”, supplied from the first clock signal supply line CL1, is applied to the second forward nMOS transistor Q.sub.i12f, and the signal charge stored in the forward capacitor C.sub.i1f is completely discharged to becomes the logical level of “0”, the first forward nMOS transistor Q.sub.i11f, becomes active as the transfer transistor, delayed by the delay time to determined by the first forward delay element D.sub.i11f. Thereafter, when the information/data of bit level is entered from the first I/O selector 512 to the gate electrode of the first forward nMOS transistor Q.sub.i11f, the first forward nMOS transistor Q.sub.i11f transfers the information/data to the forward capacitor C.sub.i1f, delayed by the delay time t.sub.d2 determined by the second forward delay element D.sub.i12f. When the clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first forward nMOS transistor Q.sub.i11f and the drain electrode of the second forward nMOS transistor Q.sub.i12f cannot deliver the information/data, which is entered from the first I/O selector 512 to the gate electrode of the first forward nMOS transistor Q.sub.i11f, further to the next bit-level cell M.sub.i2, at a time when time proceeds 1/2TAU.sub.clock, as the information/data is blocked to be transferred to the gate electrode of the next first forward nMOS transistor Q.sub.i21f delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second forward delay element D.sub.i22f.
(241) When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “1”, the second backward nMOS transistor Q.sub.i12b begins to discharge the signal charge, which is already stored in the backward capacitor C.sub.i1b at a previous clock cycle. After the clock signal of the logical level of “1”, supplied from the second clock signal supply line CL2, is applied and the signal charge stored in the backward capacitor C.sub.i1b is completely discharged to becomes the logical level of “0”, the first backward nMOS transistor Q.sub.i11b becomes active as the transfer transistor, delayed by the delay time to determined by the first backward delay element D.sub.i11b. Thereafter, when the information/data is fed from the backward output terminal of the bit-level cell M.sub.i2 to the gate electrode of the first backward nMOS transistor Q.sub.i11b, the first backward nMOS transistor Q.sub.i11b transfers the information/data stored in the previous bit-level cell M.sub.i2, further delayed by the delay time t.sub.d2 determined by the second backward delay element D.sub.i12b to the backward capacitor C.sub.i1b. The output node connecting the source electrode of the first backward nMOS transistor Q.sub.i11b, and the drain electrode of the second backward nMOS transistor Q.sub.i12b delivers the information/data stored in the backward capacitor C.sub.i1b to the first I/O selector 512.
(242) When the next clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “1”, the second forward nMOS transistor Q.sub.i22f in the second memory unit U.sub.2 begin to discharge the signal charge, which is already stored in the forward capacitor C.sub.i2f in the second memory unit U.sub.2 at the previous clock cycle. After the clock signal of the logical level of “1”, supplied from the first clock signal supply line CL1, is applied to the second forward nMOS transistor Q.sub.i22f, and the signal charge stored in the forward capacitor C.sub.i2f is completely discharged to becomes the logical level of “0”, the first forward nMOS transistor Q.sub.i2f1 becomes active as the transfer transistor, delayed by the delay time t.sub.d1 determined by the first forward delay element D.sub.i21f. Thereafter, when the information/data of bit level stored in the previous forward capacitor C.sub.i1f is fed to the gate electrode of the first forward nMOS transistor Q.sub.i21f, the first forward nMOS transistor Q.sub.i21f transfers the information/data, delayed by the delay time t.sub.d2 determined by the second forward delay element D.sub.i22f to the forward capacitor C.sub.i2f. When the clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first forward nMOS transistor Q.sub.i21f and the drain electrode of the second forward nMOS transistor Q.sub.i22f cannot deliver the information/data, which is entered to the gate electrode of the first forward nMOS transistor Q.sub.i21f, further to the next bit-level cell M.sub.i3, at a time when time proceeds 1/2TAU.sub.clock, as the information/data is blocked to be transferred to the gate electrode of the next first forward nMOS transistor Q.sub.i31f delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second forward delay element D.sub.i32f.
(243) When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “1”, the second backward nMOS transistor Q.sub.i22b begins to discharge the signal charge, which is already stored in the backward capacitor C.sub.i2b at a previous clock cycle. After the clock signal supplied from the second clock signal supply line CL2 of the logical level of “1” is applied and the signal charge stored in the backward capacitor C.sub.i2b is completely discharged to becomes the logical level of “0”, the first backward nMOS transistor Q.sub.i21b becomes active as the transfer transistor, delayed by the delay time t.sub.d1 determined by the first backward delay element D.sub.i21b. Thereafter, when the information/data is fed from the backward output terminal of the bit-level cell M.sub.i3 to the gate electrode of the first backward nMOS transistor Q.sub.i21b, the first backward nMOS transistor Q.sub.i21b transfers the information/data stored in the previous bit-level cell M.sub.i3, further delayed by the delay time t.sub.d2 determined by the second backward delay element D.sub.i22b to the backward capacitor C.sub.i2b. When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first backward nMOS transistor Q.sub.i21b and the drain electrode of the second backward nMOS transistor Q.sub.i22b cannot deliver the information/data, which is entered to the gate electrode of the first backward nMOS transistor Q.sub.i21b, further to the next bit-level cell M.sub.i1, at a time when time proceeds 1/2TAU.sub.clock, as the information/data is blocked to be transferred to the gate electrode of the next first backward nMOS transistor Q.sub.i11b delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second backward delay element D.sub.i12b.
(244) When the next clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “1”, the second forward nMOS transistor Q.sub.i32f in the third memory unit U.sub.3 begin to discharge the signal charge, which is already stored in the forward capacitor C.sub.i3f in the third memory unit U.sub.3 at the previous clock cycle. After the clock signal of the logical level of “1”, supplied from the first clock signal supply line CL1, is applied to the second forward nMOS transistor Q.sub.i32f, and the signal charge stored in the forward capacitor C.sub.i3f is completely discharged to becomes the logical level of “0”, the first forward nMOS transistor Q.sub.i31f becomes active as the transfer transistor, delayed by the delay time t.sub.d1 determined by the first forward delay element D.sub.i31f. When the information/data stored in the previous forward capacitor C.sub.i2f is fed to the gate electrode of the first forward nMOS transistor Q.sub.i31f, the first forward nMOS transistor Q.sub.i31f transfers the information/data, delayed by the delay time t.sub.d2 determined by the second forward delay element D.sub.i32f to the forward capacitor C.sub.i3f. When the clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first forward nMOS transistor Q.sub.i31f and the drain electrode of the second forward nMOS transistor Q.sub.i32f cannot deliver the information/data, which is entered to the gate electrode of the first forward nMOS transistor Q.sub.i31f, further to the next bit-level cell M.sub.i4 (illustration is omitted), at a time when time proceeds 1/2TAU.sub.clock, as the information/data is blocked to be transferred to the gate electrode of the next first forward nMOS transistor Q.sub.i41f (illustration is omitted) delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second forward delay element D.sub.i42f (illustration is omitted).
(245) When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “1”, the second backward nMOS transistor Q.sub.i32b begins to discharge the signal charge, which is already stored in the backward capacitor C.sub.i3b at a previous clock cycle. After the clock signal supplied from the second clock signal supply line CL2 of the logical level of “1” is applied and the signal charge stored in the backward capacitor C.sub.i3b is completely discharged to becomes the logical level of “0”, the first backward nMOS transistor Q.sub.i31b becomes active as the transfer transistor, delayed by the delay time to determined by the first backward delay element D.sub.i31b. When the information/data is fed from the backward output terminal of the bit-level cell M.sub.i3 to the gate electrode of the first backward nMOS transistor Q.sub.i31b, the first backward nMOS transistor Q.sub.i31b transfers the information/data stored in the previous bit-level cell M.sub.i3, further delayed by the delay time t.sub.d2 determined by the second backward delay element D.sub.i32b on to the backward capacitor C.sub.i3b. When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first backward nMOS transistor Q.sub.i31b and the drain electrode of the second backward nMOS transistor Q.sub.i32b cannot deliver the information/data, which is entered to the gate electrode of the first backward nMOS transistor Q.sub.i31b, further to the next bit-level cell M.sub.i2, at a time when time proceeds 1/2TAU.sub.clock, as the information/data is blocked to be transferred to the gate electrode of the next first backward nMOS transistor Q.sub.i21b delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second backward delay element D.sub.i22b.
(246) When the next clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “1”, the second forward nMOS transistor Q.sub.i(n−1)2f in (n−1)-th memory unit U.sub.(n−1) begin to discharge the signal charge, which is already stored in the forward capacitor C.sub.i(n−1)f in (n−1)-th memory unit U.sub.(n−1) at the previous clock cycle. And, after the clock signal of the logical level of “1”, supplied from the first clock signal supply line CL1, is applied to the second forward nMOS transistor Q.sub.i(n−1)2f, and the signal charge stored in the forward capacitor C.sub.i(n−1)f is completely discharged to becomes the logical level of “0”, the first forward nMOS transistor Q.sub.i(n−1)1f becomes active as the transfer transistor, delayed by the delay time to determined by the first forward delay element D.sub.i(n−1)1f. When the information/data stored in the previous forward capacitor C.sub.i2f is fed to the gate electrode of the first forward nMOS transistor Q.sub.i(n−1)1f, the first forward nMOS transistor Q.sub.i(n−1)1f transfers the information/data, delayed by the delay time to determined by the second forward delay element D.sub.i(n−1)2f to the forward capacitor C.sub.i(n−1)f. When the clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first forward nMOS transistor Q.sub.i(n−1)1f and the drain electrode of the second forward nMOS transistor Q.sub.i(n−1)2f cannot deliver the information/data, which is entered to the gate electrode of the first forward nMOS transistor Q.sub.i(n−1)1f, further to the next bit-level cell M.sub.in, at a time when time proceeds 1/2TAU.sub.clock, as the information/data is blocked to be transferred to the gate electrode of the next first forward nMOS transistor Q.sub.in1f delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second forward delay element D.sub.in2f.
(247) When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “1”, the second backward nMOS transistor Q.sub.i(n−1)2b begins to discharge the signal charge, which is already stored in the backward capacitor C.sub.i(n−1)b at a previous clock cycle. After the clock signal supplied from the second clock signal supply line CL2 of the logical level of “1” is applied and the signal charge stored in the backward capacitor C.sub.i(n−1)b is completely discharged to becomes the logical level of “0”, the first backward nMOS transistor Q.sub.i(n−1)1b becomes active as the transfer transistor, delayed by the delay time to determined by the first backward delay element D.sub.i(n−1)1b. Thereafter, when the information/data is fed from the backward output terminal of the bit-level cell M.sub.i(n−1) to the gate electrode of the first backward nMOS transistor Q.sub.i(n−1)1b, the first backward nMOS transistor Q.sub.i(n−1)1b transfers the information/data stored in the previous bit-level cell M.sub.i(n−1), further delayed by the delay time t.sub.d2 determined by the second backward delay element D.sub.i(n−1)2b to the backward capacitor C.sub.i(n−1)b. When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first backward nMOS transistor Q.sub.i(n−1)1b and the drain electrode of the second backward nMOS transistor Q.sub.i(n−1)2b cannot deliver the information/data, which is entered to the gate electrode of the first backward nMOS transistor Q.sub.i(n−1)1b, further to the next bit-level cell M.sub.i(n−2) (illustration is omitted), at a time when time proceeds 1/2TAU.sub.clock, as the information/data is blocked to be transferred to the gate electrode of the next first backward nMOS transistor Q.sub.i(n−2)1b (illustration is omitted)delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second backward delay element D.sub.i(n−2)2b (illustration is omitted).
(248) When the next clock signal supplied from the first clock signal supply line CL1 becomes the logical level of “1”, the second forward nMOS transistor Q.sub.in2f in n-th memory unit U.sub.n begin to discharge the signal charge, which is already stored in the forward capacitor C.sub.inf in n-th memory unit U.sub.n at the previous clock cycle. After the clock signal of the logical level of “1”, supplied from the first clock signal supply line CL1, is applied to the second forward nMOS transistor Q.sub.in2f, and the signal charge stored in the forward capacitor C.sub.inf is completely discharged to becomes the logical level of “0”, the first forward nMOS transistor Q.sub.in1f becomes active as the transfer transistor, delayed by the delay time to determined by the first forward delay element D.sub.in1f. When the information/data stored in the previous forward capacitor C.sub.i2f is fed to the gate electrode of the first forward nMOS transistor Q.sub.in1f, the first forward nMOS transistor Q.sub.in1f transfers the information/data, delayed by the delay time t.sub.d2 determined by the second forward delay element D.sub.in2f to the forward capacitor C.sub.inf. The output node connecting the source electrode of the first forward nMOS transistor Q.sub.in1f and the drain electrode of the second forward nMOS transistor Q.sub.in2f delivers the information/data, which is entered to the gate electrode of the first forward nMOS transistor Q.sub.in1f to the second I/O selector 513.
(249) When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “1”, the second backward nMOS transistor Q.sub.in2b begins to discharge the signal charge, which is already stored in the backward capacitor C.sub.inb at a previous clock cycle. After the clock signal supplied from the second clock signal supply line CL2 of the logical level of “1” is applied and the signal charge stored in the backward capacitor C.sub.inb is completely discharged to becomes the logical level of “0”, the first backward nMOS transistor Q.sub.in1b becomes active as the transfer transistor, delayed by the delay time to determined by the first backward delay element D.sub.in1b. Thereafter, when the information/data is fed from the second I/O selector 513 to the gate electrode of the first backward nMOS transistor Q.sub.in1b, the first backward nMOS transistor Q.sub.in1b transfers the information/data received from the second I/O selector 513, further delayed by the delay time t.sub.d2 determined by the second backward delay element D.sub.in2b to the backward capacitor C.sub.inb. When the clock signal supplied from the second clock signal supply line CL2 becomes the logical level of “0” at a time when time proceeds 1/2TAU.sub.clock, the output node connecting the source electrode of the first backward nMOS transistor Q.sub.in1b and the drain electrode of the second backward nMOS transistor Q.sub.in2b cannot deliver the information/data, which is entered to the gate electrode of the first backward nMOS transistor Q.sub.in1b, further to the next bit-level cell M.sub.i(n−2) (illustration is omitted), at a time when time proceeds 1/2TAU.sub.clock, as the information/data is blocked to be transferred to the gate electrode of the next first backward nMOS transistor Q.sub.i(n−2)1b (illustration is omitted)delayed by the delay time t.sub.d2=1/2TAU.sub.clock determined by the second backward delay element D.sub.i(n−2)2b (illustration is omitted).
(250) In the bidirectional marching main memory shown in FIG. 32, each of the cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,(n−1), M.sub.i,n on the i-th row of the bidirectional marching main memory stores the information/data, and transfers bi-directionally the information/data, synchronously with the clock signals supplied respectively from the first clock signal supply line CL1 and the second clock signal supply line CL2, step by step, between the first I/O selector 512 and the second I/O selector 513. As explained about, since each of the cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,n−1, M.sub.i,n assigned in memory unit U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, respectively, and the memory units U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n stores information of byte size or word size by the sequence of bit-level cells arrayed in the memory unit U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, respectively, the bidirectional marching main memory 31 shown in FIG. 32 stores the information/data of byte size or word size in each of cells U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n and transfers bi-directionally the information/data of byte size or word size synchronously with the clock signal, pari passu, in the forward direction and/or reverse direction (backward direction) between a first I/O selector 512 and a second I/O selector 513, so as to provide the processor 11 with the stored information/data of byte size or word size actively and sequentially so that the ALU 112 can execute the arithmetic and logic operations with the stored information/data.
(251) As shown in FIG. 33, a forward isolation transistor Q.sub.i23f is provided so as to isolate the signal-storage state of the second bit-level cell M.sub.i2 in the second memory unit U.sub.2 from the signal-storage state of the first bit-level cell M.sub.i1 in the first memory unit U.sub.1, the forward isolation transistor Q.sub.i23f transfers forward a signal from the first bit-level cell M.sub.i1 to the second bit-level cell M.sub.i2 at a required timing determined by a clock signal, which is supplied through the first clock signal supply line CL1. A backward isolation transistor Q.sub.i13b is provided so as to isolate the signal-storage state of the first bit-level cell M.sub.i1 in the first memory unit U.sub.1 from the signal-storage state of the second bit-level cell M.sub.i2 in the second memory unit U.sub.2, the backward isolation transistor Q.sub.i13b transfers backward a signal from the second bit-level cell M.sub.i2 to the first bit-level cell M.sub.i1 at a required timing determined by a clock signal, which is supplied through the second clock signal supply line CL2. A sequence of the forward isolation transistors Q.sub.i23f (i=1 to m; “m” is integer corresponding the byte size or the word size) arrayed in parallel with the memory units U.sub.1 and U.sub.2 transfers forward the information of byte size or word size, controlled by the clock signal supplied through the clock signal supply line CL1 so that the information of byte size or word size can march along the forward direction, pari passu. A sequence of the backward isolation transistors Q.sub.i13b (i=1 to m) arrayed in parallel with the memory units U.sub.1 and U.sub.2 transfers backward the information of byte size or word size, controlled by the clock signal supplied through the clock signal supply line CL2 so that the information of byte size or word size can march along the backward direction, pari passu.
(252) Similarly, a backward isolation transistor Q.sub.i23b is provided to isolate the signal-storage state of the signal-storage state of the second bit-level cell M.sub.i2 in the second memory unit U.sub.2 from the third bit-level cell M.sub.i3 (the illustration is omitted) in the third memory unit U.sub.3, the backward isolation transistor Q.sub.i23b transfers backward a signal from the third bit-level cell M.sub.i3 to the second bit-level cell M.sub.i2 at a required timing determined by a clock signal, which is supplied through the second clock signal supply line CL2. A sequence of the backward isolation transistors Q.sub.i23b (i=1 to m) arrayed in parallel with the memory units U.sub.2 and U.sub.3 transfers backward the information of byte size or word size, controlled by the clock signal supplied through the clock signal supply line CL2 so that the information of byte size or word size can march along the backward direction, pari passu.
(253) As shown in FIG. 33, a forward isolation transistor Q.sub.i(n−1)3f is provided so as to isolate the signal-storage state of the (n−1)-th bit-level cell M.sub.i(n−1) in the (n−1)-th memory unit U.sub.n−1 from the signal-storage state of the (n−2)-th bit-level cell M.sub.i(n−2) (the illustration is omitted) in the (n−2)-th memory unit U.sub.n−2 (the illustration is omitted), the forward isolation transistor Q.sub.i(n−1)3f transfers forward a signal from the (n−2)-th bit-level cell M.sub.i(n−2) to the (n−1)-th bit-level cell M.sub.i(n−1) at a required timing determined by a clock signal, which is supplied through the first clock signal supply line CL1. A sequence of the forward isolation transistors Q.sub.i(n−1)3f (i=1 to m) arrayed in parallel with the memory units U.sub.n−2 and U.sub.n−1 transfers the information of byte size or word size, controlled by the clock signal supplied through the clock signal supply line CL1 so that the information of byte size or word size can march along the forward direction, pari passu.
(254) A forward isolation transistor Q.sub.in3f is provided so as to isolate the signal-storage state of the n-th bit-level cell M.sub.in in the n-th memory unit U.sub.n from the signal-storage state of the (n−1)-th bit-level cell M.sub.in−1 in the (n−1)-th memory unit U.sub.n−1, the forward isolation transistor Q.sub.in3f transfers forward a signal from the (n−1)-th bit-level cell M.sub.in−1 to the n-th bit-level cell M.sub.in at a required timing determined by a clock signal, which is supplied through the first clock signal supply line CL1. A backward isolation transistor Q.sub.in3b is provided so as to isolate the signal-storage state of the (n−1)-th bit-level cell M.sub.in−1 in the (n−1)-th memory unit U.sub.n−1 from the signal-storage state of n-th bit-level cell M.sub.in in the n-th memory unit U.sub.n, the backward isolation transistor Q.sub.in3b transfers backward a signal from the n-th bit-level cell M.sub.in to the (n−1)-th bit-level cell M.sub.in−1 at a required timing determined by a clock signal, which is supplied through the second clock signal supply line CL2. A sequence of the forward isolation transistors Q.sub.in3f (i=1 to m) arrayed in parallel with the memory units U.sub.n−1 and U.sub.n transfers the information of byte size or word size, controlled by the clock signal supplied through the clock signal supply line CL1 so that the information of byte size or word size can march along the forward direction, pari passu. A sequence of the backward isolation transistors Q.sub.in3b (i=1 to m) arrayed in parallel with the memory units U.sub.n−1 and U.sub.n transfers the information of byte size or word size, controlled by the clock signal supplied through the clock signal supply line CL2 so that the information of byte size or word size can march along the backward direction, pari passu.
(255) In the bidirectional marching main memory shown in FIGS. 32 and 33, the forward capacitor C.sub.ijf and the backward capacitor C.sub.ijb are merged into a single common capacitor so as to implement random access mode with high locality. FIG. 34 shows an array of i-th row of the m*n matrix (here, “m” is an integer determined by word size) in a gate-level representation of the bidirectional marching main memory 31, which can achieve the random access mode in the bidirectional behavior shown in FIGS. 31(a)-(c).
(256) As shown in FIG. 34, two kinds of marching AND-gates are assigned to each of the cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,(n−1), M.sub.i,n on the i-th row so as to establish a bidirectional transfer of information/data with random access mode. The bidirectional marching main memory 31 stores the information/data of bit level in each of cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,n−1, M.sub.i,n and transfers bi-directionally the information/data synchronously with the clock signal, step by step in the forward direction and/or reverse direction (backward direction) between a first I/O selector 512 and a second I/O selector 513.
(257) In the gate-level representation of cell array implementing the marching main memory 31 shown in FIG. 34, a first bit-level cell M.sub.i1 allocated at the leftmost side on i-th row and connected to first I/O selector 512 encompasses a common capacitor C.sub.i1 configured to store the information/data, and a forward marching AND-gate G.sub.i1f having one input terminal connected to the common capacitor C.sub.i1, the other input supplied with the first clock signal supply line CL1, and an output terminal connected to one input terminal of the next forward marching AND-gate G.sub.(i+1)1f assigned to the adjacent second bit-level cell M.sub.(i+1)1 on the i-th row, and a backward marching AND-gate G.sub.i1b having one input terminal connected to the common capacitor C.sub.i1, the other input supplied with the second clock signal supply line CL2, and an output terminal connected to the first I/O selector 512.
(258) The first clock signal supply line CL1, configured to drive the forward data-stream, and the second clock signal supply line CL2, configured to drive the backward data-stream, are respectively selected by a clock selector 511, and each of the first clock signal supply line CL1 and the second clock signal supply line CL2 has logical values of “1” and “0”. When the logical values of “1” of the first clock signal supply line CL1 is fed to the other input terminal of the forward marching AND-gate G.sub.i1, the information/data stored in the common capacitor C.sub.i1 is transferred to a common capacitor C.sub.i2, assigned to the adjacent second bit-level cell M.sub.i2, and the common capacitor C.sub.i2 stores the information/data.
(259) The second bit-level cell M.sub.i2 on the i-th row of the bidirectional marching main memory 31 encompasses the common capacitor C.sub.i2 configured to store the information/data, a forward marching AND-gate G.sub.i2f, which has one input terminal connected to the common capacitor C.sub.i2, the other input supplied with the first clock signal supply line CL1, and an output terminal connected to one input terminal of the next forward marching AND-gate G.sub.13f assigned to the adjacent third bit-level cell M.sub.i3 on the i-th row, and the backward marching AND-gate G.sub.i2b having one input terminal connected to the common capacitor C.sub.i2, the other input supplied with the second clock signal supply line CL2, and an output terminal connected to one input terminal of the preceding backward marching AND-gate G.sub.i1b.
(260) Similarly, the third bit-level cell M.sub.i3 on the i-th row encompasses a common capacitor C.sub.i3 configured to store the information/data, a forward marching AND-gate G.sub.i3f having one input terminal connected to the common capacitor C.sub.i3, the other input supplied with the first clock signal supply line CL1, and an output terminal connected to one input terminal of the next forward marching AND-gate assigned to the adjacent fourth cell, although the illustration of the fourth cell is omitted, and an backward marching AND-gate G.sub.i3b having one input terminal connected to the common capacitor C.sub.i3, the other input supplied with the second clock signal supply line CL2, and an output terminal connected to one input terminal of the preceding backward marching AND-gate G.sub.i2b assigned to the adjacent second bit-level cell M.sub.i2. When the logical values of “1” of the first clock signal supply line CL1 is fed to the other input terminal of the forward marching AND-gate G.sub.i2f, the information/data stored in the common capacitor C.sub.i2 is transferred to the common capacitor C.sub.i3, assigned to the third bit-level cell M.sub.i3, and the common capacitor C.sub.i3 stores the information/data, and when the logical values of “1” of the first clock signal supply line CL1 is fed to the other input terminal of the forward marching AND-gate G.sub.i3f, the information/data stored in the common capacitor C.sub.i3 is transferred to the capacitor, assigned to the fourth cell.
(261) An (n−1)-th bit-level cell M.sub.i,(n−1) on the i-th row encompasses a common capacitor C.sub.i,(n−1), configured to store the information/data, and a forward marching AND-gate G.sub.i,(n−1)f having one input terminal connected to the common capacitor C.sub.i,(n−1), the other input supplied with the first clock signal supply line CL1, and an output terminal connected to one input terminal of the next forward marching AND-gate G.sub.i,nf assigned to the adjacent n-th bit-level cell M.sub.i,n, which is allocated at the rightmost side on the i-th row and connected to the second I/O selector 513, and an backward marching AND-gate G.sub.i,(n−1)b, which has one input terminal connected to the common capacitor C.sub.i,(n−1), the other input supplied with the second clock signal supply line CL2, and an output terminal connected to one input terminal of the preceding backward marching AND-gate G.sub.i,(n−2)b assigned to the adjacent third bit-level cell M.sub.i,(n−2)b (illustration is omitted).
(262) An n-th bit-level cell M.sub.i,n allocated at the rightmost side on the i-th row and connected to the second I/O selector 513 encompasses a common capacitor C.sub.i,n configured to store the information/data, a backward marching AND-gate G.sub.inb having one input terminal connected to the common capacitor C.sub.in, the other input terminal configured to be supplied with the second clock signal supply line CL2, and an output terminal connected to one input terminal of the preceding backward marching AND-gate G.sub.i(n−1)b assigned to the adjacent (n−1)-th bit-level cell on the i-th row, and a forward marching AND-gate G.sub.i,nf having one input terminal connected to the common capacitor C.sub.i,n, the other input terminal configured to be supplied with the first clock signal supply line CL1, and an output terminal connected to the second I/O selector 513.
(263) When the logical values of “1” of the second clock signal supply line CL2 is fed to the other input terminal of the backward marching AND-gate G.sub.inb, the information/data stored in the common capacitor C.sub.in is transferred to a common capacitor C.sub.i,(n−1), assigned to the adjacent (n−1)-th bit-level cell M.sub.i,(n−1) on the i-th row, and the common capacitor C.sub.i,(n−1) stores the information/data. Then, when the logical values of “1” of the second clock signal supply line CL2 is fed to the other input terminal of the backward marching AND-gate G.sub.i3b, the information/data stored in the common capacitor C.sub.i3 is transferred to the common capacitor C.sub.i2, assigned to the second bit-level cell M.sub.i2, and the common capacitor C.sub.i2 stores the information/data. When the logical values of “1” of the second clock signal supply line CL2 is fed to the other input terminal of the backward marching AND-gate G.sub.i2b, the information/data stored in the common capacitor C.sub.i2 is transferred to the common capacitor C.sub.i1, assigned to the second bit-level cell M.sub.i1, and the common capacitor C.sub.i1 stores the information/data, and when the logical values of “1” of the second clock signal supply line CL2 is fed to the other input terminal of the backward marching AND-gate G.sub.i1b, the information/data stored in the common capacitor C.sub.i1 is transferred to the first I/O selector 512.
(264) Each of the cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,(n−1), M.sub.i,n on the i-th row of the bidirectional marching main memory stores the information/data, and transfers bi-directionally the information/data, synchronously with the clock signals supplied respectively from the first clock signal supply line CL1 and the second clock signal supply line CL2, step by step, between the first I/O selector 512 and the second I/O selector 513. Because each of the cells M.sub.i1, M.sub.i2, M.sub.i3, . . . , M.sub.i,n−1, M.sub.i,n is assigned in memory unit U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, respectively, and the memory units U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n stores information of byte size or word size by the sequence of bit-level cells arrayed in the memory unit U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n, respectively, the bidirectional marching main memory 31 shown in FIG. 34 stores the information/data of byte size or word size in each of cells U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n and transfers bi-directionally the information/data of byte size or word size synchronously with the clock signal, pari passu, in the forward direction and/or reverse direction (backward direction) between a first I/O selector 512 and a second I/O selector 513, so as to provide the processor 11 with the stored information/data of byte size or word size actively and sequentially so that the ALU 112 can execute the arithmetic and logic operations with the stored information/data.
Position Pointing Strategy
(265) FIG. 35(a) shows a bidirectional transferring mode of instructions in a one-dimensional marching main memory adjacent to a processor, where the instructions moves toward the processor, and moves from/to the next memory. FIG. 35(b) shows a bidirectional transferring mode of scalar data in a one-dimensional marching main memory adjacent to an ALU 112, the scalar data moves toward the ALU and moves from/to the next memory. FIG. 35(c) shows a uni-directional transferring mode of vector/streaming data in a one-dimensional marching main memory adjacent to a pipeline 117, which will be explained in the following exemplary embodiment, the vector/streaming data moves toward the pipeline 117, and moves from the next memory.
(266) An exemplary embodiment of the marching main memory 31 uses positioning to identify the starting point and ending point of a set of successive memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n in vector/streaming data. On the other hand, for programs and scalar data, each item must have a position index similar to conventional address. FIG. 36(a) shows a configuration of conventional main memory, in which every memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n in are labeled by addresses A.sub.1, A.sub.2, A.sub.3, . . . , A.sub.n−1, A.sub.n, FIG. 36(b) shows a configuration of one-dimensional marching main memory, in which the positioning of individual memory unit U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n is not always necessary, but the positioning of individual memory unit U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n is at least necessary to identify the starting point and ending point of a set of successive memory units in vector/streaming data.
(267) FIG. 37(a) shows an inner configuration of present one-dimensional marching main memory, in which the position indexes like existing addresses are not necessary for scalar instruction I.sub.s, but the positioning of individual memory unit is at least necessary to identify the starting point and ending point of a set of successive memory units in vector instruction I.sub.v, as indicated by hatched circle. FIG. 37(b) shows an inner configuration of present one-dimensional marching main memory, in which the position indexes are not necessary for scalar data “b” and “a”. However, as shown in FIG. 37(c), position indexes are at least necessary to identify the starting point and ending point of a set of successive memory units in vector/streaming data “o”, “p”, “q”, “r”, “s”, “t”, . . . as indicated by hatched circle.
(268) In a marching memory family, which includes a marching-instruction register file 22a and a marching-data register file 22b connected to the ALU 112, and a marching-instruction cache memory 21a and a marching-data cache memory 21b, which will both be explained in the following exemplary embodiments, in addition to the marching main memory, the relation between the main memory, the register file and cache memory is such that each has their own position pointing strategy based on the property of locality of reference.
(269) FIG. 38(a) shows schematically an example of an overall configuration of present marching main memory implemented by a plurality of pages P.sub.i−1,j−1, P.sub.i,j−1, P.sub.i+1,j−1, P.sub.i+2,j−1, P.sub.i−1,j, P.sub.i,j, P.sub.i+1,j, P.sub.i+2,j for vector/streaming data case. FIG. 38(b) shows schematically an example of a configuration of the hatched page P.sub.i,j, which is implemented by a plurality of files F.sub.1, F.sub.2, F.sub.3, F.sub.4 for vector/streaming data case, and each of the pages P.sub.i−1,j−1, P.sub.i,j−1, P.sub.i+1,j−1, P.sub.i+2,j−1, P.sub.i−1,j, P.sub.i,j, P.sub.i+1,j, P.sub.i+2,j can be used for marching cache memories 21a and 21b in the exemplary embodiment. FIG. 38(c) shows schematically an example of a configuration of the hatched file F.sub.3, each of the files F.sub.1, F.sub.2, F.sub.3, F.sub.4 is implemented by a plurality of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n−1, U.sub.n for vector/streaming data case, and each of the files F.sub.1, F.sub.2, F.sub.3, F.sub.4 can be used for marching register files 22a and 22b in the exemplary embodiment.
(270) Similarly, FIG. 39(a) shows schematically an example of an overall configuration of present marching main memory implemented by a plurality of pages P.sub.r−1,s−1, P.sub.r,s−1, P.sub.r+1,s−1, P.sub.r+2,s−1, P.sub.r−1,s, P.sub.r,s, P.sub.r+1,s, P.sub.r+2,s for programs/scalar data case, where each pages has its own position index as an address. FIG. 39(b) shows schematically an example of a configuration of the hatched page P.sub.r−1,s and the driving positions of the page P.sub.r−1,s, using digits in the binary system, each of the page P.sub.r−1,s−1, P.sub.r,s−1, P.sub.r+1,s−1, P.sub.r+2,s−1, P.sub.r−1,s, P.sub.r,s, P.sub.r+1,s, P.sub.r+1,s is implemented by a plurality of files F.sub.1, F.sub.2, F.sub.3, F.sub.4 for programs/scalar data case. Each of the page P.sub.r−1,s−1, P.sub.r,s−1, P.sub.r+1,s−1, P.sub.r+2,s−1, P.sub.r−1,s, P.sub.r,s, P.sub.r+1,s, P.sub.r+2,s can be used for marching cache memories 21a and 21b in the exemplary embodiment, where each of the files F.sub.1, F.sub.2, F.sub.3, F.sub.4 has its own position index as address. FIG. 39(c) shows schematically an example of a configuration of the hatched file F.sub.3 and the driving positions of the file F.sub.3, using digits 0, 1, 2, 3 in the binary system, each of the files F.sub.1, F.sub.2, F.sub.3, F.sub.4 is implemented by a plurality of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n, U.sub.n+1, U.sub.n+2, U.sub.n+3, U.sub.n+4, U.sub.n+5 for programs/scalar data case. Each of the files F.sub.1, F.sub.2, F.sub.3, F.sub.4 can be used for a marching register files 22a and 22b in the exemplary embodiment, where each memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.n, U.sub.n+1, U.sub.n+2, U.sub.n+3, U.sub.n+4, U.sub.n+5 has its own position index n+4, n+3, n+2, . . . , 5, 4, 3, 2, 1, 0 as address. FIG. 39(c) represents position pointing strategy for all of the cases by digits in the binary system.
(271) As shown in FIG. 39(c), the n binary digits identify a single memory unit among 2.sup.n memory units, respectively, in a memory structure having an equivalent size corresponding to the size of a marching register file. And, as shown in FIG. 39(b), the structure of one page has an equivalent size corresponding to the size of a marching cache memory, which is represented by two digits which identify four files F.sub.1, F.sub.2, F.sub.3, F.sub.4, while the structure of one marching main memory is represented by three digits which identify eight pages P.sub.r−1,s−1, P.sub.r,s−1, P.sub.r+1,s−1, P.sub.r+2,s−1, P.sub.r−1,s, P.sub.r,s, P.sub.r+1,s, P.sub.r+2,s in the marching main memory as shown in FIG. 39(a).
Speed/Capability
(272) The speed gap between memory access time and the CPU cycle time in a conventional computer system is, for example, 1:100. However, the speed of the marching memory access time is equal to the CPU cycle time in the computer system of the exemplary embodiment. FIG. 40 compares the speed/capability of the conventional computer system without cache with that of the marching main memory 31. That is, FIG. 40(b) shows schematically the speed/capability of the marching main memory 31, implemented by one hundred of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.100, and compares with the speed/capability of the existing memory shown in FIG. 40(a). We can also support 99 additional simultaneous memory units of the marching main memory 31, on the condition that necessary processing units are available to use the data from the marching main memory 31. Therefore, one memory unit time T.sub.mue in the conventional computer system is estimated to be equal to one hundred of the memory unit streaming time T.sub.mus of the marching main memory 31.
(273) FIG. 41 compares the speed/capability of the worst case of the existing memory for scalar data or program instructions with that of the marching main memory 31. The hatched portion of FIG. 41(b) shows schematically the speed/capability of the marching main memory 31, implemented by one hundred of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.100, and compares with the speed/capability of the worst case of the existing memory shown in FIG. 41(a). In a worst case, 99 memory units of the marching main memory 31 can be read, but they are not available due to a scalar program's requirement.
(274) FIG. 42 compares the speed/capability of conventional memory for scalar data or program instructions with that of the marching main memory 31. FIG. 42(b) shows schematically the speed/capability of the marching main memory 31, implemented by one hundred of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.100, and compares with the speed/capability of the typical case of the existing memory shown in FIG. 42(a). In the typical case, 99 memory units can be read but only several memory units are available, as shown by hatched memory units in the existing memory, by speculative data preparation in a scalar program.
(275) FIG. 43 compares the speed/capability of the conventional case of the existing memory for scalar data case with that of the marching main memory 31. FIG. 43(b) shows schematically the speed/capability of the marching main memory 31, implemented by one hundred of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.100, and compares with the speed/capability of the existing memory shown in FIG. 43(a). Similar to the case shown in FIGS. 34(a)-(b), in the conventional case, 99 memory units can be read but only several memory units are available, as shown by hatched memory units in the existing memory, by speculative data preparation in a scalar data or program instructions in multi-thread parallel processing.
(276) FIG. 44 compares the speed/capability of the best case of the conventional memory for streaming data, vector data or program instructions case with that of the marching main memory 31. That is, FIG. 44(b) shows schematically the speed/capability of the marching main memory 31, implemented by one hundred of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.100, and compares with the speed/capability of the best case of the conventional memory shown in FIG. 44(a). In the best case, one hundred memory units of the marching main memory 31 are usable for streaming data and data parallel.
Two-Dimensional Marching Main Memory
(277) The memory units can be arranged two-dimensionally on a chip as shown in FIGS. 45-51 so that various modes of operation can be achieved without a switch/network. According to the two-dimensional marching main memory 31 of the exemplary embodiment shown in FIGS. 45-51, the memory units U.sub.11, U.sub.12, U.sub.13, . . . , U.sub.1, v−1, U.sub.1v; U.sub.21, U.sub.22, U.sub.23, U.sub.2, v−2, U.sub.2v; . . . ; U.sub.u1, U.sub.u2, U.sub.u3, . . . , U.sub.u, v−1, U.sub.uv are not required of the refreshment, because all of the memory units U.sub.11, U.sub.12, U.sub.13, . . . , U.sub.1, v−1, U.sub.1v; U.sub.22, U.sub.22, U.sub.23, . . . , U.sub.2, v−2, U.sub.2v; . . . ; U.sub.u1, U.sub.u2, U.sub.u3, . . . , U.sub.u, v−1, U.sub.uv are usually refreshed automatically due to the information-moving scheme (information-marching scheme). And then addressing to each of memory units U.sub.11, U.sub.12, U.sub.13, . . . , U.sub.1, v−1, U.sub.1v; U.sub.22, U.sub.22, U.sub.23, . . . , U.sub.2, v−2, U.sub.2v; . . . ; U.sub.u1, U.sub.u2, U.sub.u3, . . . , U.sub.u, v−1, U.sub.uv disappears and required information is heading for its destination unit connected to the edge of the memory. The mechanism of accessing the two-dimensional marching main memory 31 of the exemplary embodiment is unique compared to existing memory schemes that are starting from the addressing mode to read/write information in the conventional computer system. Therefore, according to the two-dimensional marching main memory 31 of the exemplary embodiment, the memory-accessing process without addressing mode in the computer system of the exemplary embodiment is simpler than existing memory schemes of the conventional computer system.
Energy Consumption
(278) To clarify the improvement of architecture, design and implementation of the computer system having the above discussed embodiments, the improvement in energy consumption will be explained. FIG. 52(a) shows that the energy consumption in microprocessors can be decomposed into static power consumption and dynamic power consumption. In the dynamic power consumption shown in FIG. 52(a), net and overhead of the power consumption are shown in FIG. 52(b). As shown in FIG. 52(c), only the net energy portions are practically necessary to operate a given job in a computer system, so these pure energy parts require the lowest level of energy consumption to perform the computer system. This means the shortest processing time is achieved by the net energy consumed shown in FIG. 52(c).
(279) Even though some efforts are introduced into architecting, designing and implementing processors, there are bottlenecks in the conventional architecture as shown in FIG. 1. In the conventional architecture, there are various issues in the von Neumann computer, as follows: 1) Programs are stored like data in memory; 2) All processing is basically sequential in a uni-processor; 3) The operation of programs is the sequential execution of instructions; 4) Vector data is sequentially processed by the CPU with vector instructions; 5) Streaming data is sequentially processed with threads; 6) Programs then threads are arranged sequentially; 7) Data parallel consists of an arrangement of data as a vector: and 8) Streaming data is a flow of data
(280) From the properties of a conventional computer, the storage of programs and data follow sequential arrangements, meaning the regular arrangement of instructions exists in a program and the corresponding data.
(281) In the computer system of the present invention shown in FIG. 2, the access of instructions in the marching main memory 31 is not necessary, because instructions are actively accessed directly be the processor 11. Similarly, the access of data in the marching main memory 31 is not necessary, because data is actively accessed directly by the processor 11.
(282) FIG. 53 shows an actual energy consumption distribution over a processor including registers and caches in the conventional architecture, estimated by William J. Dally, et al., in “Efficient Embedded Computing”, Computer, vol. 41, no. 7, 2008, pp. 27-32. In FIG. 53, an estimation of the power consumption distribution on only the whole chip, except for wires between chips is disclosed. The instruction supply power consumption is estimated to be 42%, the data supply power consumption is estimated to be 28%, the clock and control logic power consumption is estimated to be 24%, and the arithmetic power consumption is estimated to be 6%. Therefore, the instruction supply and data supply power consumptions are relatively larger than of the clock/control logic power consumption and the arithmetic power consumption, which is ascribable to the inefficiency of cache/register accessing with lots of wires and some software overhead due to access ways of these caches and registers in addition to non-refreshment of all the memories, caches and registers.
(283) Since the ratio of the instruction supply power consumption to the data supply power consumption is 3:2, and the ratio of the clock and control logic power consumption to the arithmetic power consumption is 4:1, by using the computer system shown in FIG. 2, data supply power consumption can be reduced up to 20% by using the marching main memory 31 at least partly so that the instruction supply power consumption becomes 30%, while the arithmetic power consumption can be increased to 10% so that the clock and control logic power consumption become 40%, which means that the sum of the instruction supply power consumption and the data supply power consumption can be made 50%, and the sum of the clock and control logic power consumption and the arithmetic power consumption can be made 50%.
(284) If the data supply power consumption is reduced to 10%, the instruction supply power consumption becomes 15%, and if the arithmetic power consumption is increased to 15%, the clock and control logic power consumption will become 60%, which means that the sum of the instruction supply power consumption and the data supply power consumption can be made 35%, while the sum of the clock and control logic power consumption and the arithmetic power consumption can be made 75%.
(285) The conventional computer system dissipates energy, as shown in the FIG. 54(a),with a relatively large average active time for addressing and read/writing memory units, accompanied by wire delay time. The present computer system dissipates smaller energy as shown in the FIG. 54(b), because the present computer system has a shorter average active smooth time through marching memory, and the same data can be processed faster than the conventional computer system with less energy.
Additional Embodiments
(286) As shown in FIG. 55, an exemplary embodiment of a computer system includes a processor 11 and a marching main memory 31. The processor 11 includes a control unit 111 having a clock generator 113 configured to generate a clock signal, an arithmetic logic unit (ALU) 112 configured to execute arithmetic and logic operations synchronized with the clock signal, a marching-instruction register file (RF) 22a connected to the control unit 111 and a marching-data register file (RF) 22b connected to the ALU 112.
(287) Although the illustration is omitted, very similar to the marching main memory 31 shown in FIGS. 3-24, 25(a), 25(b), 26 and 45-51, the marching-instruction register file 22a has an array of instruction register units, instruction-register input terminals of the third array configured to receive the stored instruction from the marching main memory 31, and instruction-register output terminals of the third array, configured to store instruction in each of instruction register units and to transfer successively and periodically the stored instruction in each of instruction register units to an adjacent instruction register unit being synchronized with the clock signal from the instruction register units adjacent to the instruction-register input terminals toward the instruction register units adjacent to the instruction-register output terminals, so as to provide actively and sequentially instruction implemented by the stored instruction to the control unit 111 through the instruction-register output terminals so that the control unit 111 can execute operations with the instruction.
(288) Further similar to the marching main memory 31 shown in FIGS. 3-24, 25(a), 25(b), 26 and 45-51, the marching-data register file 22b has an array of data register units, data-register input terminals of the fourth array configured to receive the stored data from the marching main memory 31, and data-register output terminals of the fourth array, configured to store data in each of data register units and to transfer successively and periodically the stored data in each of data register units to an adjacent data register unit being synchronized with the clock signal from the data register units adjacent to the data-register input terminals toward the data register units adjacent to the data-register output terminals, so as to provide actively and sequentially the data to the ALU 112 through the data-register output terminals so that the ALU 112 can execute operations with the data, although the detailed illustration of, the marching-data register file 22b is omitted.
(289) As shown in FIG. 55, a portion of the marching main memory 31 and the marching-instruction register file 22a are electrically connected by a plurality of joint members 54, and remaining portion of the marching main memory 31 and the marching-data register file 22b are electrically connected by another plurality of joint members 54.
(290) The resultant data of the processing in the ALU 112 are sent out to the marching-data register file 22b. Therefore, as represented by bidirectional arrow PHI(Greek-letter).sub.24, data are transferred bi-directionally between the marching-data register file 22b and the ALU 112. Furthermore, the data stored in the marching-data register file 22b are sent out to the marching main memory 31 through the joint members 54. Therefore, as represented by bidirectional arrow PHI.sub.23, data are transferred bi-directionally between the marching main memory 31 and the marching-data register file 22b through the joint members 54.
(291) On the contrary, as represented by uni-directional arrows ETA(Greek-letter).sub.22 and ETA.sub.23, as to the instructions movement, there is only one way of instruction-flow from the marching main memory 31 to the marching-instruction register file 22a, and from the marching-instruction register file 22a to the control unit 111.
(292) In the exemplary embodiment of the computer system shown in FIG. 55, there are no buses consisting of the data bus and address bus because the whole computer system has no wires, even in any data exchange between the marching main memory 31 and the marching-instruction register file 22a, between the marching main memory 31 and the marching-data register file 22b, between the marching-instruction register file 22a and the control unit 111 and between the marching-data register file 22b and the ALU 112, while the wires or the buses implement the bottleneck in the conventional computer system. As there are no global wires, which generate time delay and stray capacitances between these wires, the computer system of the exemplary embodiment can achieve much higher processing speed and lower power consumption.
(293) Since other functions, configurations, and ways of operation of the computer system pertaining to the exemplary embodiment are substantially similar to the functions, configurations, way of operation already explained in the exemplary embodiment, overlapping or redundant description may be omitted.
(294) As shown in FIG. 56, another exemplary embodiment of a computer system a processor 11, a marching-cache memory (21a, 21b) and a marching main memory 31. Similar to the above exemplary embodiments, the processor 11 includes a control unit 111 having a clock generator 113 configured to generate a clock signal, an arithmetic logic unit (ALU) 112 configured to execute arithmetic and logic operations synchronized with the clock signal, a marching-instruction register file (RF) 22a connected to the control unit 111 and a marching-data register file (RF) 22b connected to the ALU 112.
(295) The marching-cache memory (21a, 21b) embraces a marching-instruction cache memory 21a and a marching-data cache memory 21b. Although the illustration is omitted, very similar to the marching main memory 31 shown in FIGS. 3-24, 25(a), 25(b), 26 and 45-51, each of the marching-instruction cache memory 21a and the marching-data cache memory 21b has an array of cache memory units at locations corresponding to a unit of information, cache input terminals of the array configured to receive the stored information from the marching main memory 31, and cache output terminals of the array, configured to store information in each of cache memory units and to transfer, synchronously with the clock signal, step by step, the information each to an adjacent cache memory unit, so as to provide actively and sequentially the stored information to the processor 11 so that the ALU 112 can execute the arithmetic and logic operations with the stored information.
(296) As shown in FIG. 56, a portion of the marching main memory 31 and the marching-instruction cache memory 21a are electrically connected by a plurality of joint members 52, and remaining portion of the marching main memory 31 and the marching-data cache memory 21b are electrically connected by another plurality of joint members 52. Furthermore, the marching-instruction cache memory 21a and the marching-instruction register file 22a are electrically connected by a plurality of joint members 51, and the marching-data cache memory 21b and the marching-data register file 22b are electrically connected by another plurality of joint members 51.
(297) The resultant data of the processing in the ALU 112 are sent out to the marching-data register file 22b, and, as represented by bidirectional arrow PHI(Greek-letter).sub.34, data are transferred bi-directionally between the marching-data register file 22b and the ALU 112. Furthermore, the data stored in the marching-data register file 22b are sent out to the marching-data cache memory 21b through the joint members 51, and, as represented by bidirectional arrow PHI.sub.33, data are transferred bi-directionally between the marching-data cache memory 21b and the marching-data register file 22b through the joint members 51. Furthermore, the data stored in the marching-data cache memory 21b are sent out to the marching main memory 31 through the joint members 52, and, as represented by bidirectional arrow PHI.sub.32, data are transferred bi-directionally between the marching main memory 31 and the marching-data cache memory 21b through the joint members 52.
(298) On the contrary, as represented by uni-directional arrows ETA(Greek-letter).sub.31, eta.sub.32 and eta.sub.33, as to the instructions movement, there is only one way of instruction-flow from the marching main memory 31 to the marching-instruction cache memory 21a, from the marching-instruction cache memory 21a to the marching-instruction register file 22a, and from the marching-instruction register file 22a to the control unit 111.
(299) In the exemplary embodiment of the computer system shown in FIG. 56, there are no buses consisting of the data bus and address bus because the whole computer system has no global wires even in any data exchange between the marching main memory 31 and the marching-instruction cache memory 21a, between the marching-instruction cache memory 21a and the marching-instruction register file 22a, between the marching main memory 31 and the marching-data cache memory 21b, between the marching-data cache memory 21b and the marching-data register file 22b, between the marching-instruction register file 22a and the control unit 111 and between the marching-data register file 22b and the ALU 112, while the wires or the buses implement the bottleneck in the conventional computer system. As there are no global wires, which generate time delay and stray capacitances between these wires, this exemplary embodiment of the computer system can achieve much higher processing speed and lower power consumption.
(300) Since other functions, configurations, way of operation of the computer system pertaining to the exemplary embodiment are substantially similar to the functions, configurations, way of operation already explained in the first and second embodiments, overlapping or redundant description may be omitted.
(301) As shown in FIG. 57(a), the ALU 112 in the exemplary embodiment of the computer system may includes a plurality of arithmetic pipelines P.sub.1, P.sub.2, P.sub.3, . . . , P.sub.n configured to receive the stored information through marching register units R.sub.11, R.sub.12, R.sub.13, . . . , R.sub.1n; R.sub.21, R.sub.22, R.sub.23, . . . , R.sub.2n, in which data move in parallel with the alignment direction of the arithmetic pipelines P.sub.1, P.sub.2, P.sub.3, . . . , P.sub.n. In case that vector data are stored, marching-vector register units R.sub.11, R.sub.12, R.sub.13, . . . , R.sub.1n; R.sub.21, R.sub.22, R.sub.23, . . . , R.sub.2n can be used.
(302) Furthermore, as shown in FIG. 57(b), a plurality of marching cache units C.sub.11, C.sub.12, C.sub.13, . . . , C.sub.1n; C.sub.21, C.sub.22, C.sub.23, . . . , C.sub.2n; C.sub.31, C.sub.32, C.sub.33, . . . , C.sub.3n can be aligned in parallel.
(303) As shown in FIG. 58, the ALU 112 in the exemplary embodiment of the computer system may include a single processor core 116, and as represented by cross-directional arrows, the information can moves from the marching-cache memory 21 to the marching-register file 22, and from the marching-register file 22 to the processor core 116. The resultant data of the processing in the processor core 116 are sent out to the marching-register file 22 so that data are transferred bi-directionally between the marching-register file 22 and the processor core 116. Furthermore, the data stored in the marching-register file 22 are sent out to the marching-cache memory 21 so that data are transferred bi-directionally between the marching-cache memory 21 and the marching-register file 22. In case of instructions movement, there is no flow along the opposite direction of the information to be processed.
(304) As shown in FIG. 59, the ALU 112 in the exemplary embodiment of the computer system may include a single arithmetic pipeline 117, and as represented by cross-directional arrows, the information can moves from the marching-cache memory 21 to the marching-vector register file 22v, and from the marching-vector register file 22v to the arithmetic pipeline 117. The resultant data of the processing in the arithmetic pipeline 117 are sent out to the marching-vector register file 22v so that data are transferred bi-directionally between the marching-vector register file 22v and the arithmetic pipeline 117. Furthermore, the data stored in the marching-vector register file 22v are sent out to the marching-cache memory 21 so that data are transferred bi-directionally between the marching-cache memory 21 and the marching-vector register file 22v. In case of instructions movement, there is no flow along the opposite direction of the information to be processed.
(305) As shown in FIG. 60, the ALU 112 in the exemplary embodiment of the computer system may include a plurality of processor cores 116.sub.−1, 116.sub.−2, 116.sub.−3, 116.sub.−4, . . . , 116.sub.−m, and as represented by cross-directional arrows, the information can moves from the marching-cache memory 21 to the marching-register file 22, and from the marching-register file 22 to the processor cores 116.sub.−1, 116.sub.−2, 116.sub.−3, 116.sub.−4, . . . , 116.sub.−m. The resultant data of the processing in the processor cores 116.sub.−1, 116.sub.−2, 116.sub.−3, 116.sub.−4, . . . , 116.sub.−m are sent out to the marching-register file 22 so that data are transferred bi-directionally between the marching-register file 22 and the processor cores 116.sub.−1, 116.sub.−2, 116.sub.−3, 116.sub.−4, . . . , 116.sub.−m. Furthermore, the data stored in the marching-register file 22 are sent out to the marching-cache memory 21 so that data are transferred bi-directionally between the marching-cache memory 21 and the marching-register file 22. In case of instructions movement, there is no flow along the opposite direction of the information to be processed.
(306) As shown in FIG. 61, the ALU 112 in the exemplary embodiment of the computer system may include a plurality of arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m, and as represented by cross-directional arrows, the information can moves from the marching-cache memory 21 to the marching-vector register file 22v, and from the marching-vector register file 22v to the arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m. The resultant data of the processing in the arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m are sent out to the marching-vector register file 22v so that data are transferred bi-directionally between the marching-vector register file 22v and the arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m. Furthermore, the data stored in the marching-vector register file 22v are sent out to the marching-cache memory 21 so that data are transferred bi-directionally between the marching-cache memory 21 and the marching-vector register file 22v. In case of instructions movement, there is no flow along the opposite direction of the information to be processed.
(307) As shown in FIG. 62(b), the ALU 112 in the exemplary embodiment of the computer system may include a plurality of arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m, and a plurality of marching cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, 21.sub.−4, . . . , 21.sub.−m are electrically connected to the marching main memory 31. Here, a first marching-vector register file 22v.sub.−1 is connected to the first marching-cache memory 214, and a first arithmetic pipeline 117.sub.−1 is connected to the first marching-vector register file 22v.sub.−1. A second marching-vector register file 22v.sub.−2 is connected to the second marching-cache memory 21.sub.−2, and a second arithmetic pipelines 117.sub.−2 is connected to the second marching-vector register file 22v.sub.−2; a third marching-vector register file 22v.sub.−3 is connected to the third marching-cache memory 21.sub.−3, and a third arithmetic pipelines 117.sub.−3 is connected to the third marching-vector register file 22v.sub.−3; . . . ; and a m-th marching-vector register file 22v.sub.−m is connected to the m-th marching-cache memory 21.sub.−m, and a m-th arithmetic pipelines 117.sub.−m is connected to the m-th marching-vector register file 22v.sub.−m.
(308) The information moves from the marching main memory 31 to the marching cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, 21.sub.−4, . . . , 21.sub.−m in parallel, from marching cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, 21.sub.−4, . . . , 21.sub.−m to the marching-vector register files 22v.sub.−1, 22v.sub.−2, 22v.sub.−3, 22v.sub.−4, . . . , 22v.sub.−m in parallel, and from the marching-vector register files 22v.sub.−1, 22v.sub.−2, 22v.sub.−3, 22v.sub.−4, . . . , 22v.sub.−m to the arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m in parallel. The resultant data of the processing in the arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m are sent out to the marching-vector register files 22v.sub.−1, 22v.sub.−2, 22v.sub.−3, 22v.sub.−4, . . . , 22v.sub.−m so that data are transferred bi-directionally between the marching-vector register files 22v.sub.−1, 22v.sub.−2, 22v.sub.−3, 22v.sub.−4, . . . , 22v.sub.−m and the arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m. Furthermore, the data stored in the marching-vector register files 22v.sub.−1, 22v.sub.−2, 22v.sub.−3, 22v.sub.−4, . . . , 22v.sub.−m are sent out to the marching cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, 21.sub.−4, . . . , 21.sub.−m so that data are transferred bi-directionally between the marching cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, 21.sub.−4, . . . , 21.sub.−m and the marching-vector register files 22v.sub.−1, 22v.sub.−2, 22v.sub.−3, 22v.sub.−4, . . . , 22v.sub.−m, and the data stored in the marching cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, 21.sub.−4, . . . , 21.sub.−m are sent out to the marching main memory 31 so that data are transferred bi-directionally between the marching main memory 31 and the marching cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, 21.sub.−4, . . . , 21.sub.−m. In case of instructions movement, there is no flow along the opposite direction of the information to be processed.
(309) On the contrary, as shown FIG. 62(a), in the ALU 112 of the conventional computer system including a plurality of arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m, a plurality of conventional cache memories 321.sub.−1, 321.sub.−2, 321.sub.−3, 321.sub.−4, . . . , 321.sub.−m are electrically connected to the conventional main memory 331 through wires and/or buses which implement von Neumann bottleneck 325. Information moves from the conventional main memory 331 to the conventional cache memories 321.sub.−1, 321.sub.−2, 321.sub.−3, 321.sub.−4, . . . , 321.sub.−m in parallel through von Neumann bottleneck 325, from conventional cache memories 321.sub.−1, 321.sub.−2, 321.sub.−3, 321.sub.−4, . . . , 321.sub.−m to the conventional-vector register files (RFs) 322v.sub.−1, 322v.sub.−2, 322v.sub.−3, 322v.sub.−4, . . . , 322v.sub.−m in parallel, and from the conventional-vector register files 322v.sub.−1, 322v.sub.−2, 322v.sub.−3, 322v.sub.−4, . . . , 322v.sub.−m to the arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m in parallel.
(310) In the exemplary embodiment of the computer system shown in FIG. 62(b), there are no buses consisting of the data bus and address bus because the whole system has no global wires even in any data exchange between the arithmetic pipelines 117.sub.−1, 117.sub.−2, 117.sub.−3, 117.sub.−4, . . . , 117.sub.−m and the marching main memory 31, while the wires or the buses implement the bottleneck in the conventional computer system as shown in FIG. 62(a). As there are no global wires, which generate time delay and stray capacitances between these wires, the computer system shown in FIG. 62(b) can achieve much higher processing speed and lower power consumption.
(311) As shown in FIG. 63, another exemplary embodiment of the computer system includes a conventional main memory 31s, a mother marching main memory 31.sub.−0 connected to the conventional main memory 31s, and a plurality of processing units 12.sub.−1, 12.sub.−2, 12.sub.−3, . . . , configured to communicate with mother marching main memory 31.sub.−0 so as to implement a high performance computing (HPC) system, which can be used for graphics processing unit (GPU)-based general-purpose computing. Although the illustration is omitted, the HPC system of the exemplary embodiment further includes a control unit 111 having a clock generator 113 configured to generate a clock signal, and a field programmable gate array (FPGA) configured to switch-control operations of the plurality of processing units 12.sub.−1, 12.sub.−2, 12.sub.−3, . . . , optimizing the flow of crunching calculations by running parallel, constructing to help manage and organize bandwidth consumption. FPGA is, in essence, a computer chip that can rewire itself for a given task. FPGA can be programmed with hardware description languages such as VHDL or Verilog.
(312) The first processing unit 12.sub.−1 encompasses a first branched-marching main memory 31.sub.−1, a plurality of first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p electrically connected respectively to the first branched-marching main memory 31.sub.−1, a plurality of first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p electrically connected respectively to the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p, a plurality of first arithmetic pipelines 117.sub.−11, 117.sub.−12, . . . , 117.sub.−1p electrically connected respectively to the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p.
(313) Similar to the configurations shown in FIGS. 3-24, 25(a), 25(b), 26 and 45-51 etc., each of the mother marching main memory 31.sub.−0, the first branched-marching main memory 31.sub.−1, the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p, and the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p encompasses an array of memory units, input terminals of the array and output terminals of the array, configured to store information in each of memory units and to transfer synchronously with the clock signal, step by step, from a side of input terminals toward the output terminals.
(314) Because the operations of the mother marching main memory 31.sub.−0, the first branched-marching main memory 31.sub.−1, the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p, and the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p are controlled by FPGA, the information moves from the mother marching main memory 31.sub.−0 to the first branched-marching main memory 31.sub.−1, from the first branched-marching main memory 31.sub.−1 to the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p in parallel, from first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p to the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p in parallel, and from the first marching-vector register files 22v.sub.−1, 22v.sub.−12, . . . , 22v.sub.−1p to the first arithmetic pipelines 117.sub.−11, 117.sub.−12, . . . , 117.sub.−1p in parallel. The resultant data of the processing in the first arithmetic pipelines 117.sub.−11, 117.sub.−12, . . . , 117.sub.−1p are sent out to the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p so that data are transferred bi-directionally between the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p and the first arithmetic pipelines 117.sub.−11, 117.sub.−12, . . . , 117.sub.−1p. Furthermore, the data stored in the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p are sent out to the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p so that data are transferred bi-directionally between the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p and the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p, and the data stored in the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p are sent out to the first branched-marching main memory 31.sub.−1 so that data are transferred bi-directionally between the first branched-marching main memory 31.sub.−1 and the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p. However, the FPGA controls the movement of instructions such that there is no flow along the opposite direction of the information to be processed in the first processing unit 12.sub.−1.
(315) The second processing unit 12.sub.−2 encompasses a second branched-marching main memory 31.sub.−2, a plurality of second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2p electrically connected respectively to the second branched-marching main memory 31.sub.−2, a plurality of second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2q electrically connected respectively to the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2p, a plurality of second arithmetic pipelines 117.sub.−21, 117.sub.−22, . . . , 117.sub.−2p electrically connected respectively to the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2q. Similar to the first processing unit 124, each of the mother marching main memory 31.sub.−0, the second branched-marching main memory 31.sub.−2, the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2p, and the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2p encompasses an array of memory units, input terminals of the array and output terminals of the array, configured to store information in each of memory units and to transfer synchronously with the clock signal, step by step, from a side of input terminals toward the output terminals. Because the operations of the mother marching main memory 31.sub.−0, the second branched-marching main memory 31.sub.−2, the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2p, and the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2p are controlled by the FPGA, the information moves from the mother marching main memory 31.sub.−0 to the second branched-marching main memory 31.sub.−2, from the second branched-marching main memory 31.sub.−2 to the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2q in parallel, from second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2q to the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2q in parallel, and from the second marching-vector register files 22v.sub.−21, 22v.sub.−2, . . . , 22v.sub.−2q to the second arithmetic pipelines 117.sub.−21, 117.sub.−22, . . . , 117.sub.−2q in parallel. The resultant data of the processing in the second arithmetic pipelines 117.sub.−21, 117.sub.−22, . . . , 117.sub.−2q are sent out to the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2q so that data are transferred bi-directionally between the second marching-vector register files 22v.sub.−21, 22v.sub.−2, . . . , 22v.sub.−2q and the second arithmetic pipelines 117.sub.−21, 117.sub.−22, . . . , 117.sub.−2q. Furthermore, the data stored in the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2q are sent out to the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2q so that data are transferred bi-directionally between the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2q and the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2q, and the data stored in the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2q are sent out to the second branched-marching main memory 31.sub.−2 so that data are transferred bi-directionally between the second branched-marching main memory 31.sub.−2 and the second marching cache memories 21.sub.−21, 21.sub.−2, . . . , 21.sub.−2q. However, the FPGA controls the movement of instructions such that there is no flow along the opposite direction of the information to be processed in the second processing unit 12.sub.−2.
(316) For example, vector instructions generated from loops in a source program are transferred from the mother marching main memory 31.sub.−0 to the first processing unit 12.sub.−1, the second processing unit 12.sub.−2, the third processing unit 12.sub.−3, in parallel, so that parallel processing of these vector instructions can be executed by arithmetic pipelines 117.sub.−11, 117.sub.−12, . . . , 117.sub.−1p, 117.sub.−21, 117.sub.−22, . . . , 117.sub.−2q, in each of the first processing unit 12.sub.−1, the second processing unit 12.sub.−2, the third processing unit 12.sub.−3, . . . .
(317) Although the current FPGA-controlled HPC system requires a large amount of wiring resources, which generate time delay and stray capacitances between these wires and contributing to the bottleneck, in the HPC system of the exemplary embodiment shown in FIG. 63, because there are no buses such as data bus and address bus for any data exchange between the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p and the first arithmetic pipelines 117.sub.−11, 117.sub.−12, . . . , 117.sub.−1p, between the first marching cache memories 21.sub.−11, 21.sub.−12, . . . , 21.sub.−1p and the first marching-vector register files 22v.sub.−11, 22v.sub.−12, . . . , 22v.sub.−1p, between the first branched-marching main memory 31.sub.−1 and the first marching cache memories 214.sub.−11, 21.sub.−12, . . . , 21.sub.−1p, between the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2q and the second arithmetic pipelines 117.sub.−21, 117.sub.−22, . . . , 117.sub.−2q, between the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2q and the second marching-vector register files 22v.sub.−21, 22v.sub.−22, . . . , 22v.sub.−2q, between the second branched-marching main memory 31.sub.−2 and the second marching cache memories 21.sub.−21, 21.sub.−22, . . . , 21.sub.−2q, between the mother marching main memory 31.sub.−0 and the first branched-marching main memory 31.sub.−1, and between the mother marching main memory 31.sub.−0 and the second branched-marching main memory 31.sub.−2, the FPGA-controlled HPC system shown in FIG. 63 can achieve much higher processing speed and lower power consumption than the current FPGA-controlled HPC system. By increasing the number of processing units 12.sub.−1, 12.sub.−2, 12.sub.−3, . . . , the FPGA-controlled HPC system pertaining to the exemplary embodiment can execute, for example, thousands of threads or more simultaneously at very high speed, enabling high computational throughput across large amounts of data.
(318) As shown in FIG. 64, yet another exemplary embodiment of the computer system includes a processor 11, a stack of marching-register files 22.sub.−1, 22.sub.−2, 22.sub.−3, . . . , implementing a three-dimensional marching-register file connected to the processor 11, a stack of marching-cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, . . . , implementing a three-dimensional marching-cache memory connected to the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ), and a stack of marching main memories 31.sub.−1, 31.sub.−2, 31.sub.−3, . . . , implementing a three-dimensional marching main memory connected to the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ). The processor 11 includes a control unit 111 having a clock generator 113 configured to generate a clock signal, an arithmetic logic unit (ALU) 112 configured to execute arithmetic and logic operations synchronized with the clock signal.
(319) In the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ), a first marching-register file 22.sub.−1 includes a first marching-instruction register file 22a.sub.−1 connected to the control unit 111 and a first marching-data register file 22b.sub.−1 connected to the ALU 112, a second marching-register file 22.sub.−2 includes a second marching-instruction register file connected to the control unit 111 and a second marching-data register file connected to the ALU 112, a third marching-register file 22.sub.−3 includes a third marching-instruction register file connected to the control unit 111 and a third marching-data register file connected to the ALU 112, and, In the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ), the first marching-cache memory 21.sub.−1 includes a first marching-instruction cache memory 21a.sub.−1 and a first marching-data cache memory 21b.sub.−1, the second marching-cache memory 21.sub.−2 includes a second marching-instruction cache memory and a second marching-data cache memory, the third marching-cache memory 21.sub.−3 includes a third marching-instruction cache memory and a third marching-data cache memory, and . . . . .
(320) Although the illustration is omitted, very similar to the marching main memory 31 shown in FIGS. 45-51, each of the marching main memories 31.sub.−1, 31.sub.−2, 31.sub.−3, . . . , has a two-dimensional array of memory units each having a unit of information, input terminals of the main memory array and output terminals of the main memory array, each of the marching main memories 31.sub.−1, 31.sub.−2, 31.sub.−3, . . . , stores the information in each of memory units and to transfer synchronously with the clock signal, step by step, toward the output terminals of the main memory array, so as to provide the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) with the stored information actively and sequentially, each of the marching-cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, . . . , has a two-dimensional array of cache memory units, cache input terminals of the marching-cache array configured to receive the stored information from the three-dimensional marching main memory (31.sub.−1, 31.sub.−2, 31.sub.−3, . . . ), and cache output terminals of the marching-cache array, each of the marching-cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, . . . , stores the information in each of cache memory units and to transfer, synchronously with the clock signal, step by step, the information to an adjacent cache memory unit, so as to provide actively and sequentially the stored information to the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ), and each of the marching-register files 22.sub.−1, 22.sub.−2, 22.sub.−3, . . . , has a two-dimensional array of register units each having a unit of information, input terminals of the register array configured to receive the stored information from the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ), and output terminals of the register array, each of the marching-register files 22.sub.−1, 22.sub.−2, 22.sub.−3, . . . , stores the information in each of register units and to transfer synchronously with the clock signal, step by step, toward the output terminals of the register array, so as to provide the processor 11 with the stored information actively and sequentially so that the processor 11 can execute the arithmetic and logic operations with the stored information.
(321) Each of the marching main memories 31.sub.−1, 31.sub.−2, 31.sub.−3, . . . , is implemented by the two-dimensional array of memory units delineated at a surface of a semiconductor chip, and a plurality of the semiconductor chips are stacked vertically as shown in 27A, sandwiching heat dissipating plates 58m.sub.−1, 58m.sub.−2, 58m.sub.−3, . . . between the plurality of the semiconductor chips so as to implement the three-dimensional marching main memory (31.sub.−1, 31.sub.−2, 31.sub.−3, . . . ). IN an exemplary embodiment, the heat dissipating plates 58m.sub.−1, 58m.sub.−2, 58m.sub.−3, . . . , are made of materials having high thermal conductivity such as diamond. Similarly, each of the marching-cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, . . . , is implemented by the two-dimensional array of memory units delineated at a surface of a semiconductor chip, and a plurality of the semiconductor chips are stacked vertically as shown in 27B, sandwiching heat dissipating plates 58c.sub.−1, 58c.sub.−2, 58c.sub.−3, . . . , between the plurality of the semiconductor chips so as to implement the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ), and each of the marching-register files 22.sub.−1, 22.sub.−2, 22.sub.−3, . . . , is implemented by the two-dimensional array of memory units delineated at a surface of a semiconductor chip, and a plurality of the semiconductor chips are stacked vertically as shown in 27C, sandwiching heat dissipating plates 58r.sub.−1, 58r.sub.−2, 58r.sub.−3, . . . , between the plurality of the semiconductor chips so as to implement the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ). In an exemplary embodiment, the heat dissipating plates 58c.sub.−1, 58c.sub.−2, 58c.sub.−3, . . . , 58r.sub.−1, 58r.sub.−2, 58r.sub.−3, . . . , are made of materials having high thermal conductivity such as diamond. Because there are no interconnects inside the surfaces of the semiconductor chips in the three-dimensional configuration shown in FIGS. 65(a)-(c) and 66, it is easy to insert the heat dissipating plates 58c.sub.−1, 58c.sub.−2, 58c.sub.−3, . . . , 58r.sub.−1, 58r.sub.−2, 58r.sub.−3, . . . , between the semiconductor chips, the configuration shown in FIGS. 65(a)-(c) and 66 is expandable to stacking structures with any number of the semiconductor chips. In the conventional architecture, basically there is a limit of the number of stacked semiconductor chips in terms of thermal issues when the conventional semiconductor chips are directly stacked. In the computer system of the exemplary embodiment, the sandwich structure shown in FIGS. 65(a)-(c) and 66 is suitable for establishing the thermal flow from active computing semiconductor chips through the heat dissipating plates 58c.sub.−1, 58c.sub.−2, 58c.sub.−3, . . . , 58r.sub.−1, 58r.sub.−2, 58r.sub.−3, . . . , to outside the system more effectively. Therefore, in the computer system of the exemplary embodiment, these semiconductor chips can be stacked proportionally to the scale of the system, and as shown in FIGS. 65(a)-(c) and 66, because a plurality of the semiconductor chips merging the marching main memories 31.sub.−1, 31.sub.−2, 31.sub.−3, . . . , the marching-cache memories 21.sub.−1, 21.sub.−2, 21.sub.−3, . . . , and the marching-register files 22.sub.−1, 22.sub.−2, 22.sub.−3, . . . , could easily be stacked to implement the three-dimensional configuration, a scalable computer systems can be easily organized, thereby keeping the temperature of the system cooler.
(322) Although the illustration is omitted, the three-dimensional marching main memory (31.sub.−1, 31.sub.−2, 31.sub.−3, . . . ) and the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) are electrically connected by a plurality of joint members, the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) and the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ) are electrically connected by a plurality of joint members, and the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ) and processor 11 are electrically connected by another plurality of joint members.
(323) The resultant data of the processing in the ALU 112 are sent out to the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ) through the joint members so that data are transferred bi-directionally between the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ) and the ALU 112. Furthermore, the data stored in the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ) are sent out to the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) through the joint members so that data are transferred bi-directionally between the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) and the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ). Furthermore, the data stored in the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) are sent out to the three-dimensional marching main memory (31.sub.−, 31.sub.−2, 31.sub.−3, . . . ) through the joint members so that data are transferred bi-directionally between the three-dimensional marching main memory (31.sub.−1, 31.sub.−2, 31.sub.−3, . . . ) and the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ).
(324) There is only one way of instruction-flow from the three-dimensional marching main memory (31.sub.−1, 31.sub.−2, 31.sub.−3, . . . ) to the three-dimensional marching-cache (21.sub.−, 21.sub.−2, 21.sub.−3, . . . ), from the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) to the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ), and from the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ) to the control unit 111. For example, vector instructions generated from loops in a source program are transferred from the three-dimensional marching main memory (31.sub.−1, 31.sub.−2, 31.sub.−3, . . . ) to the control unit 111 through the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) and the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ) so that each of these vector instructions can be executed by arithmetic pipelines in the control unit 111.
(325) In the exemplary embodiment of the computer system shown in FIG. 64, there are no buses such as the data bus and address bus in any data exchange between the three-dimensional marching main memory (31.sub.−1, 31.sub.−2, 31.sub.−3, . . . ) and the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ), between the three-dimensional marching-cache (21.sub.−1, 21.sub.−2, 21.sub.−3, . . . ) and the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ), and between the three-dimensional marching-register file (22.sub.−1, 22.sub.−2, 22.sub.−3, . . . ) and the processor 11. This is in contrast to the wires or the buses contributing to the bottleneck in the conventional computer system. As there are no global wires, which generate time delay and stray capacitances between these wires, the exemplary embodiment of the computer system can achieve much higher processing speed and lower power consumption than the conventional computer system, keeping the temperature of the computer system at lower temperature than the conventional computer system so as to establish “a cool computer”, by employing the heat dissipating plates 58c.sub.−1, 58c.sub.−2, 58c.sub.−3, . . . , 58r.sub.−1, 58r.sub.−2, 58r.sub.−3, . . . , which are made of materials having high thermal conductivity such as diamond and disposed between the semiconductor chips. The cool computer pertaining to the exemplary embodiment is different from existing computers because the cool computer is purposely architected and designed with an average of 30% less energy consumption and 10000% less size to obtain 100 times higher speed, for example.
(326) Since other functions, configurations, way of operation of the computer system pertaining to the exemplary embodiment are substantially similar to the functions, configurations, way of operation already explained in the first to third embodiments, overlapping or redundant description may be omitted.
Three-Dimensional Configurations
(327) The three-dimensional configurations shown in FIGS. 64, 65(a), 65(b) and 65(c) are exemplary embodiments, and there are various ways and combinations of how to implement three-dimensional configurations so as to facilitate the organization of a scalable computer system.
(328) For example, as shown in FIG. 66, a first chip (top chip) merging a plurality of arithmetic pipelines 117 and a plurality of marching-register files 22, a second chip (middle chip) merging a marching-cache memory 21 and a third chip (bottom chip) merging a marching main memory 31 can be stacked vertically. Each of the arithmetic pipelines 117 may include a vector-processing unit, and each of the marching-register files 22 may include marching-vector registers. Between the first and second chips, a plurality of joint members 55a are inserted, and between the second and third chips, a plurality of joint members 55b are inserted. For example, each of joint members 55a and 55b may be implemented by an electrical conductive bump such as a solder ball, a gold (Au) bump, a silver (Ag) bump, a copper (Cu) bump, a nickel-gold (Ni—Au) alloy bump or a nickel-gold-indium (Ni—Au—In) alloy bump. Although the illustration is omitted, heat-dissipating plates can be inserted between the first and second chips and between the second and third chips so as to achieve “cool chips”, similar to the configuration shown in FIGS. 65(a)-(c) and 66.
(329) Alternatively, as shown in FIGS. 67 and 68, a first three-dimensional (3D)-stack embracing a first top chip, a first middle chip and first bottom chip and a second 3D-stack embracing a second top chip, a second middle chip and second bottom chip may be disposed two dimensionally on a same substrate or a same circuit board so as to implement a parallel computing with multiple processors, in which the first 3D-stack and the second 3D-stack are connected by bridges 59a and 59b.
(330) In the first 3D-stack, a first top chip merging a plurality of first arithmetic pipelines 117.sub.−1 and a plurality of first marching-register files 22.sub.−1, a first middle chip merging a first marching-cache memory 21.sub.−1 and a first bottom chip merging a first marching main memory 31.sub.−1 are 3D-stacked vertically. Each of the first arithmetic pipelines 117.sub.−1 may include a vector-processing unit, and each of the first marching-cache files 22.sub.−1 may include marching-vector registers. Between the first top and first middle chips, a plurality of joint members 55a.sub.−1 are inserted, and between the first middle and first bottom chips, a plurality of joint members 55b.sub.−1 are inserted. For example, each of joint members 55a.sub.−1 and 55b.sub.−1 may be implemented by an electrical conductive bump such as a solder ball, a gold (Au) bump, a silver (Ag) bump, a copper (Cu) bump, a nickel-gold (Ni—Au) alloy bump or a nickel-gold-indium (Ni—Au—In) alloy bump. Similarly, in the second 3D-stack, a second top chip merging a plurality of second arithmetic pipelines 117.sub.−2 and a plurality of second marching-register files 22.sub.−2, a second middle chip merging a second marching-cache memory 21.sub.−2 and a second bottom chip merging a second marching main memory 31.sub.−2 are 3D-stacked vertically. Each of the second arithmetic pipelines 117.sub.−2 may include a vector-processing unit, and each of the second marching-cache files 22.sub.−2 may include marching-vector registers. Between the second top and second middle chips, a plurality of joint members 55a.sub.−2 are inserted, and between the second middle and second bottom chips, a plurality of members 55b.sub.−2 are inserted. For example, each ofjoint members 55a.sub.−2 and 55b.sub.−2 may be implemented by an electrical conductive bump such as a solder ball, a gold (Au) bump, a silver (Ag) bump, a copper (Cu) bump, a nickel-gold (Ni—Au) alloy bump or a nickel-gold-indium (Ni—Au—In) alloy bump. Although the illustration is omitted, heat-dissipating plates can be inserted between the first top and first middle chips, between the first middle and first bottom chips, between the second top and second middle chips and between the second middle and second bottom chips similar to the configuration shown in FIGS. 65(a)-(c) and 66 so as to achieve “cool chips”.
(331) Similar to the exemplary embodiments of the computer system a field programmable gate array (FPGA) may switch-control the operations of the first and second 3D-stacks, by traveling a thread or chaining of vector processing on the first arithmetic pipelines 117.sub.−1 and the second arithmetic pipelines 117.sub.−2, implementing a HPC system, which can be used for GPU-based general-purpose computing.
(332) As shown in FIG. 69, a further exemplary embodiment includes a first chip (top chip) merging a plurality of arithmetic pipelines 117, a second chip merging a plurality of marching-register files 22, a third chip merging a marching-cache memory 21, a fourth chip merging a first marching main memory 31.sub.−1, a fifth chip merging a marching main memory 31.sub.−2 and a sixth chip (bottom chip) merging a third marching main memory 31.sub.−3 can be stacked vertically. Each of the arithmetic pipelines 117 may include a vector-processing unit, and each of the marching-register files 22 may include marching-vector registers so that vector instructions generated from loops in a source program can be executed in the vector-processing unit. A first heat dissipating plate 58.sub.−1 is inserted between the first and second chips, a second heat dissipating plate 58.sub.−2 is between the second and third chips, a third heat dissipating plate 58.sub.−3 is between the third and fourth chips, a fourth heat dissipating plate 58.sub.−4 is between the fourth and fifth chips, and a fifth heat dissipating plate 58.sub.−5 is between the fifth and sixth chips so as to achieve “cool chips”. Since there are no interconnects inside the surfaces of these cool chips in the three-dimensional configuration shown in FIG. 69, it is easy to insert the heat dissipating plates 58.sub.−1, 58.sub.−2, 58.sub.−3, 58.sub.−4, 58.sub.−5 such as diamond chips between these six chips alternately.
(333) The cool-chip configuration shown in FIG. 69 is not limited to embodiments of six chips, but is also expandable to embodiments of three-dimensional stacking structures with any number of chips, because the sandwich structure shown in FIG. 69 is suitable for establishing the thermal flow from active computing chips through the heat dissipating plates 58.sub.−1, 58.sub.−2, 58.sub.−3, 58.sub.−4, 58.sub.−5 to outside of the cool computer system more effectively. Therefore, the number of cool chips in the exemplary embodiment of the computer system can be increased in proportion to the scale of the computer system.
(334) FIGS. 70-72 show various exemplary embodiments of the three-dimensional (3D) stack, implementing a part of fundamental cores of the exemplary embodiment of the computer systems, each of the 3D-stacks includes cooling technology with heat dissipating plate 58 such as diamond plate inserted between the semiconductor memory chips 3a and 3b, in which at least one of the marching memory classified in the marching memory family is merged. The term of “the marching memory family” includes the marching-instruction register file 22a and the marching-data register file 22b connected to the ALU 112, the marching-instruction cache memory 21a and the marching-data cache memory 21b, and the marching main memory 31 explained above in the exemplary embodiments of the present invention.
(335) As shown in FIG. 70, a 3D-stack, implementing a part of the fundamental core of the exemplary embodiments of the computer system, includes a first semiconductor memory chip 3a merging at least one of the marching memory in the marching memory family, a heat dissipating plate 58 disposed under the first semiconductor memory chip 3a, a second semiconductor memory chip 3b disposed under the heat dissipating plate 58, which merges at least one of the marching memory in the marching memory family, and a processor 11 disposed at a side of the heat dissipating plate 58. In FIG. 70, because the location of the processor 11 is shown as one of the examples, the processor 11 can be disposed at any required or appropriate site in the configuration of the 3D-stack or external of the 3D-stack, depending on the design choice of the 3D-stack. For example, the processor 11 can be allocated at the same horizontal level of the first semiconductor memory chip 3a or at the level of the second semiconductor memory chip 3b. The marching memory merged on the first semiconductor memory chip 3a and the marching memory merged on the second semiconductor memory chip 3b stores program instruction, respectively. In the 3D configuration shown in FIG. 70, in which the first semiconductor memory chip 3a, the heat dissipating plate 58 and the second semiconductor memory chip 3b are stacked vertically, a first control path is provided between the first semiconductor memory chip 3a and the processor 11, and a second control path is provided between the second semiconductor memory chip 3b and the processor 11 so as to facilitate the execution of the control processing with the processor 11. A further data-path may be provided between the first semiconductor memory chip 3a and the second semiconductor memory chip 3b so as to facilitate direct communication of the program instruction between the first semiconductor memory chip 3a and the second semiconductor memory chip 3b.
(336) As shown in FIG. 71, another 3D-stack, implementing a part of the fundamental core of the exemplary embodiments of the computer system, embraces a first semiconductor memory chip 3a merging at least one of the marching memory in the marching memory family, a heat dissipating plate 58 disposed under the first semiconductor memory chip 3a, a second semiconductor memory chip 3b disposed under the heat dissipating plate 58, which merges at least one of the marching memory in the marching memory family, and a ALU 112 disposed at a side of the heat dissipating plate 58. The location of the ALU 112 is not limited to the site shown in FIG. 71, and the ALU 112 can be disposed at any required or appropriate site in the configuration of the 3D-stack or external of the 3D-stack, such as a site allocated at the same horizontal level of the first semiconductor memory chip 3a or at the level of the second semiconductor memory chip 3b, depending on the design choice of the 3D-stack. The marching memory merged on the first semiconductor memory chip 3a and the marching memory merged on the second semiconductor memory chip 3b read/write scalar data, respectively. In the 3D configuration shown in FIG. 71, in which the first semiconductor memory chip 3a, the heat dissipating plate 58 and the second semiconductor memory chip 3b are stacked vertically, a first data-path is provided between the first semiconductor memory chip 3a and the ALU 112, and a second data-path is provided between the second semiconductor memory chip 3b and the ALU 112 so as to facilitate the execution of the scalar data processing with the ALU 112. A further data-path may be provided between the first semiconductor memory chip 3a and the second semiconductor memory chip 3b so as to facilitate direct communication of the scalar data between the first semiconductor memory chip 3a and the second semiconductor memory chip 3b.
(337) As shown in FIG. 72, a still another 3D-stack, implementing a part of the fundamental core of the exemplary embodiments of the computer system, includes a first semiconductor memory chip 3a merging at least one of the marching memory in the marching memory family, a heat dissipating plate 58 disposed under the first semiconductor memory chip 3a, a second semiconductor memory chip 3b disposed under the heat dissipating plate 58, which merges at least one of the marching memory in the marching memory family, and an arithmetic pipelines 117 disposed at a side of the heat dissipating plate 58. Similar to the topologies shown in FIGS. 62 and 63, the location of the arithmetic pipelines 117 is not limited to the site shown in FIG. 72, and the arithmetic pipelines 117 can be disposed at any required or appropriate site. The marching memory merged on the first semiconductor memory chip 3a and the marching memory merged on the second semiconductor memory chip 3b read/write vector/streaming data, respectively. In the 3D configuration shown in FIG. 72, in which the first semiconductor memory chip 3a, the heat dissipating plate 58 and the second semiconductor memory chip 3b are stacked vertically, a first data-path is provided between the first semiconductor memory chip 3a and the arithmetic pipelines 117, and a second data-path is provided between the second semiconductor memory chip 3b and the arithmetic pipelines 117 so as to facilitate the execution of the vector/streaming data processing with the arithmetic pipelines 117. A further data-path may be provided between the first semiconductor memory chip 3a and the second semiconductor memory chip 3b so as to facilitate direct communication of the vector/streaming data between the first semiconductor memory chip 3a and the second semiconductor memory chip 3b.
(338) As shown in FIG. 73, the 3D hybrid exemplary embodiment of the computer system includes a first left chip (top left chip) 3p.sub.−1 merging at least one of the marching memory in the marching memory family, a second left chip 3p.sub.−2 merging at least one of the marching memory in the marching memory family, a third left chip 3p.sub.−3 merging at least one of the marching memory in the marching memory family, a fourth left chip 3p.sub.−4 merging at least one of the marching memory in the marching memory family, a fifth left chip 3p.sub.−5 merging at least one of the marching memory in the marching memory family and a sixth left chip (bottom left chip) 3p.sub.−6 merging at least one of the marching memory in the marching memory family, which are stacked vertically. A first left heat dissipating plate 58a.sub.−1 is inserted between the first left chip 3p.sub.−1 and second left chip 3p.sub.−2, a second left heat dissipating plate 58a.sub.−2 is inserted between the second left chip 3p.sub.−2 and third left chip 3p.sub.−3, a third left heat dissipating plate 58a.sub.−3 is inserted between the third left chip 3p.sub.−3 and fourth left chip 3p.sub.−4, a fourth left heat dissipating plate 58a.sub.−4 is inserted between the fourth left chip 3p.sub.−4 and fifth left chip 3p.sub.−5, and a fifth left heat dissipating plate 58a.sub.−5 is inserted between the fifth left chip 3p.sub.−5 and sixth left chip 3p.sub.−6 so as to achieve “cool left chips”.
(339) A first right chip (top right chip) 3q.sub.−1 merging at least one of the marching memory in the marching memory family, a second right chip 3q.sub.−2 merging at least one of the marching memory in the marching memory family, a third right chip 3q.sub.−3 merging at least one of the marching memory in the marching memory family, a fourth right chip 3q.sub.−4 merging at least one of the marching memory in the marching memory family, a fifth right chip 3q.sub.−5 merging at least one of the marching memory in the marching memory family and a sixth right chip (bottom right chip) 3q.sub.−6 merging at least one of the marching memory in the marching memory family are stacked vertically. A first right heat dissipating plate 58b.sub.−1 is inserted between the first right chip 3q.sub.−1 and second right chip 3q.sub.−2, a second right heat dissipating plate 58b.sub.−2 is inserted between the second right chip 3q.sub.−2 and third right chip 3q.sub.−3, a third right heat dissipating plate 58b.sub.−1 is inserted between the third right chip 3q.sub.−3 and fourth right chip 3q.sub.−4, a fourth right heat dissipating plate 58b.sub.−4 is inserted between the fourth right chip 3q.sub.−4 and fifth right chip 3q.sub.−5, and a fifth right heat dissipating plate 58b.sub.−5 is inserted between the fifth right chip 3q.sub.−5 and sixth right chip 3q.sub.−6 so as to achieve “cool right chips”.
(340) A first processing unit 11a is provided between the first left heat dissipating plate 58a.sub.−1 and the first right heat dissipating plate 58b.sub.−1, a second processing unit llb is provided between the third left heat dissipating plate 58a.sub.−3 and the third right heat dissipating plate 58b.sub.−3, and a third processing unit 11c is provided between the fifth left heat dissipating plate 58a.sub.−5 and the fifth right heat dissipating plate 58b.sub.−5, and pipelined ALUs are respectively included in the processing units 11a, 11b, 11c.
(341) The scalar data-path and control path are established between the first left chip 3p.sub.−1 and second left chip 3p.sub.−2, the scalar data-path and control path are established between the second left chip 3p.sub.−2 and third left chip 3p.sub.−3, the scalar data-path and control path are established between the third left chip 3p.sub.−3 and fourth left chip 3p.sub.−4, the scalar data-path and control path are established between the fourth left chip 3p.sub.−4 and fifth left chip 3p.sub.−5, and the scalar data-path and control path are established between the fifth left chip 3p.sub.−5 and sixth left chip 3p.sub.−6, the scalar data-path and control path are established between the first right chip 3q.sub.−1 and second right chip 3q.sub.−2, the scalar data-path and control path are established between the second right chip 3q.sub.−2 and third right chip 3q.sub.−3, the scalar data-path and control path are established between the third right chip 3q.sub.−3 and fourth right chip 3q.sub.−4, the scalar data-path and control path are established between the fourth right chip 3q.sub.−4 and fifth right chip 3q.sub.−5, and the scalar data-path and control path are established between the fifth right chip 3q.sub.−5 and sixth right chip 3q.sub.−6. The 3D computer system shown in FIG. 73 can execute not only scalar data but also vector/streaming data through the combination of scalar data-path and control path for the computer system.
(342) Because there are no interconnects inside the surfaces of these cool chips in the 3D configuration shown in FIG. 73, it is easy to insert the heat dissipating plates 58a.sub.−1, 58a.sub.−2, 58a.sub.−3, 58a.sub.−4, 58a.sub.−5 such as diamond left chips between these six left chips alternately, and to insert the heat dissipating plates 58b.sub.−1, 58b.sub.−2, 58b.sub.−3, 58b.sub.−4, 58b.sub.−5 such as diamond right chips between these six right chips alternately.
Other Embodiments
(343) Various modifications will become possible for those skilled in the art after receiving the teaching of the present disclosure without departing from the scope thereof.
(344) In FIGS. 4, 5, 6, 8, 11, 13, 16-20, 22, 25 and 32, although nMOS transistors are assigned respectively as the transfer-transistors and the reset-transistors in the transistor-level representations of the bit-level cells, because the illustration in FIGS. 4, 5, 6, 8, 11, 13, 16-20, 22, 25 and 32 are mere schematic examples, pMOS transistors can be used as the transfer-transistors and the reset-transistors, if the opposite polarity of the clock signal is employed. Furthermore, MIS transistors, or insulated-gate transistors having gate-insulation films made of silicon nitride film, ONO film, SrO film, Al.sub.2O.sub.3 film, MgO film, Y.sub.2O.sub.3 film, HfO.sub.2 film, ZrO.sub.2 film, Ta.sub.2O.sub.5 film, Bi.sub.2O.sub.3 film, HfAlO film, and others can be used for the transfer-transistors and the reset-transistors.
(345) There are several different forms of parallel computing such as bit-level, instruction level, data, and task parallelism, and as well known as “Flynn's taxonomy”, programs and computers are classified as to whether they were operating using a single set or multiple sets of instructions, whether or not those instructions were using a single or multiple sets of data.
(346) For example, as shown in FIG. 74, a marching memory, which may include the marching-register file, the marching-cache memory, and the marching main memory already discussed in the exemplary embodiments can implement a bit-level parallel processing of scalar/vector data in a multiple-instruction-single-data (MISD) architecture, by which many independent instruction streams provided vertically to a first processor 11.sub.−1, a second processor 11.sub.−2, a third processor 11.sub.−3, a fourth processor 11.sub.−4, . . . , in parallel operate on a single horizontal stream of data at a time with a systolic array of processors 11.sub.−1, 11.sub.−2, 11.sub.−3, 11.sub.−4.
(347) Alternatively, as shown in FIG. 75,arithmetic-level parallelism can be established by a marching memory, which may include the marching-register file, the marching-cache memory, and the marching main memory already discussed in the exemplary embodiments, with a single-instruction-multiple-data (SIMD) architecture, by which a single instruction stream is provided to a first processor 11.sub.−1, a second processor 11.sub.−2, a third processor 11.sub.−3, and a fourth processor 11.sub.−4, so that the single instruction stream can operate on multiple vertical streams of data ata time with the array of processors 11.sub.−1, 11.sub.−2, 11.sub.−3, 11.sub.−4.
(348) Still alternatively, as shown in FIG. 76, a marching memory, which may include the marching-register file, the marching-cache memory, and the marching main memory already discussed in the exemplary embodiments, can implement a typical chaining in vector processing with a first processor 11.sub.−1, a second processor 11.sub.−2, a third processor 11.sub.−3, and a fourth processor 11.sub.−4 to which a first instruction I.sub.1, a second instruction I.sub.2, a third instruction I.sub.3, and a fourth instruction I.sub.4 are provided respectively.
(349) Furthermore, as shown in FIG. 77, a marching memory, which may include the marching-register file, the marching-cache memory, and the marching main memory already discussed in the exemplary embodiments, can implement a parallel processing of a single horizontal stream of scalar/vector data in a MISD architecture with a first processor 11.sub.−1, a second processor 11.sub.−2, a third processor 11.sub.−3, and a fourth processor 11.sub.−4.
(350) Furthermore, as shown in FIG. 78, a marching memory, which may include the marching-register file, the marching-cache memory, and the marching main memory already discussed in the exemplary embodiments, can implement a parallel processing of a single horizontal stream of scalar/vector data in a MISD architecture with a first processor 11.sub.−1 configured execute multiplication, a second processor 11.sub.−2 configured execute addition, a third processor 11.sub.−3 configured execute multiplication, and a fourth processor 11.sub.−4 configured execute addition.
(351) Furthermore, as to process-level parallelism, a single-thread-stream and single-data-stream architecture, a single-thread-stream and multiple-data-streams architecture, a multiple-thread-streams and single-data-stream architecture, and a multiple-thread-streams and multiple-data-streams architecture can be achieved with a marching memory, which may include the marching-register file, the marching-cache memory, and the marching main memory already discussed in the exemplary embodiments.
(352) Referring to FIG. 41, the hatched portion of FIG. 41(b) has shown schematically the speed/capability of the marching main memory 31, implemented by one hundred of memory units U.sub.1, U.sub.2, U.sub.3, . . . , U.sub.100, and compared with the speed/capability of the worst case of the existing memory shown in FIG. 41(a). With “a complex marching memory” scheme shown in FIG. 79(b), the speed/capability of the marching memory is improved for scalar data or program instructions, in which a plurality of marching memory blocks MM.sub.11, MM.sub.12, MM.sub.13, . . . , MM.sub.16; MM.sub.21, MM.sub.22, MM.sub.23, . . . , MM.sub.26; MM.sub.31, MM.sub.32, MM.sub.33, . . . , MM.sub.36; . . . ; MM.sub.51, MM.sub.52, MM.sub.53, . . . , MM.sub.56 are deployed two dimensionally and merged on a single semiconductor chip 66, and a specified marching memory block MM.sub.ij (i=1 to 5; j=1 to 6) can be randomly accessed from the plurality of marching memory blocks MM.sub.11, MM.sub.12, MM.sub.13, . . . , MM.sub.16; MM.sub.21, MM.sub.22, MM.sub.23, . . . , MM.sub.26; MM.sub.31, MM.sub.32, MM.sub.33, . . . , MM.sub.36; . . . ; MM.sub.51, MM.sub.52, MM.sub.53, . . . , MM.sub.56, similar to the random-access methodology employed in a dynamic random access memory (DRAM) architecture.
(353) As shown in FIG. 79(a), a conventional DRAM has a memory array area 661, peripheral circuitry for a row decoder 662, peripheral circuitry for sense amplifiers 663, and peripheral circuitry for a column decoder 664 merged on a single semiconductor chip 66. A plurality of memory cells are arranged in an array of rows and columns in the memory array area 661 so that each row of memory cells share a common ‘word’ line, while each column of cells share a common ‘bit’ line, and the location of a memory cell in the array is determined as the intersection of its ‘word’ and ‘bit’ lines. During a ‘write’ operation, the data to be written (‘1’ or ‘0’) is provided at the ‘bit’ line from the column decoder 664, while the ‘word line’ is asserted from the row decoder 662, so as to turn on the access transistor of the memory cell and allows the capacitor to charge up or discharge, depending on the state of the bit line. During a ‘read’ operation, the ‘word’ line is also asserted from the row decoder 662, which turns on the access transistor. The enabled transistor allows the voltage on the capacitor to be read by a sense amplifier 663 through the ‘bit’ line. The sense amplifier 663 can determine whether a ‘1’ or ‘0’ is stored in the memory cell by comparing the sensed capacitor voltage against a threshold.
(354) Although 6*5=30 marching memory blocks MM.sub.11, MM.sub.12, MM.sub.13, . . . , MM.sub.16; MM.sub.21, MM.sub.22, MM.sub.23, . . . , MM.sub.26; MM.sub.31, MM.sub.32, MM.sub.33, . . . , MM.sub.36; . . . ; MM.sub.51, MM.sub.52, MM.sub.53, . . . , MM.sub.56 are deployed on the semiconductor chip 66 for avoiding cluttering up the drawings, the illustration is schematic, and actually one thousand marching memory blocks MM.sub.ij (i=1 to s; j=1 to t; and s*t=1000) with 256 kbits capacity can be deployed on the same semiconductor chip 66, if unidirectional marching memories are arrayed, and if 512 Mbits DRAM chip technology is assumed as the manufacturing technology of the complex marching memory scheme shown in FIG. 79(b). As an area for monolithically integrating each of the marching memory blocks MM.sub.ij having 256 kbits capacity on a semiconductor chip 66, an equivalent area for 512 kbits DRAM block is required, because, as shown in FIGS. 4-6, each of unidirectional marching memory blocks is implemented by a bit-level cell consisting of two transistors and one capacitor, while the DRAM memory cell consists of only a single transistor that is paired with a capacitor. Alternatively, as to an array of bidirectional marching memories, one thousand marching memory blocks MM.sub.ij with 128 kbits capacity can be deployed on the same semiconductor chip 66 for the 512 Mbits DRAM chip. As an area for monolithically integrating each of the marching memory blocks MM.sub.ij having 128 kbits capacity, an equivalent area for the 512 kbits DRAM block is required, because, as shown in FIG. 32, a bidirectional marching memory block is implemented by a bit-level cell consisting of four transistors and two capacitors, while the DRAM memory cell consists of only a single transistor and a single capacitor. If one Gbit DRAM chip technology is assumed, one thousand bidirectional marching memory blocks MM.sub.ij with 256 kbits capacity can be deployed on the same DRAM chip 66 so as to implement a 256 Mbits marching memory chip.
(355) Therefore, one thousand of marching memory blocks MM.sub.ij, or one thousand of marching memory cores can be monolithically integrated on the semiconductor chip 66, as shown in FIG. 79(b). A single marching memory block MM.sub.ij, or “a single marching memory core” may encompass, for example, one thousand of marching memory columns, or one thousand of marching memory units U.sub.k (k=1 to 1000), which have 1000*32 byte-based addresses, where one memory unit U.sub.k has 256 bit-level cells. With a complex marching memory chip having one thousand of marching memory blocks MM.sub.ij, one thousand of marching memory units U.sub.k (k=1 to 1000) of 32 bytes (or 256 bits) are allowable to access within one cycle of the conventional DRAM access.
(356) FIGS. 80(a) and (b) show an example of a single 256 kbits marching memory blocks MM.sub.ij, which has one thousand of marching memory units U.sub.k (k=1 to n; n=1000) of 32 bytes (or 256 bits). In the complex marching memory schemes, as shown in FIG. 80(b), position indexes T.sub.k (k=1 to 1000) or position tags are labeled, respectively, on each of the marching memory units U.sub.k as the token of each of the columns U.sub.k that means the first address of the column bytes. In FIG. 80(b), the clock period (the clock cycle time) TAU(Greek-letter).sub.clock, shown in FIG. 7C, is recited as “the marching memory's memory cycle t.sub.M”.
(357) In the light of above discussions stated in the exemplary embodiments, since the large speed difference between the conventional DRAM and the marching memory, as shown in FIG. 80(c), can be used with the conventional DRAM's memory cycle t.sub.C for writing in or reading out the content of the conventional DRAM's one memory element, t.sub.C can be estimated as:
t.sub.C=1000t.sub.M (1).
(358) Therefore, with the complex marching memory scheme shown in FIG. 79(b), the speed/capability of the marching memory can be improved for scalar data or program instructions, by which a specified marching memory block MM.sub.ij (i=1 to s; j=1 to t; and s*t=1000) can be randomly accessed from one thousand of marching memory blocks, similar to the random-access methodology employed in the DRAM architecture.
(359) Although the illustration is omitted in FIG. 79(b), the plurality of 256 kbits marching memory blocks MM.sub.ij may be arranged in the two dimensional matrix form on the semiconductor chip 66 so that each horizontal array of the marching memory blocks MM.sub.ij share a common horizontal-core line, while each vertical array of marching memory blocks MM.sub.ij share a common vertical-core line, and a location of a specified marching memory block MM.sub.ij in the two dimensional matrix is accessed as the intersection of its horizontal-core line and vertical-core line, with double-level hierarchy. In the double-level hierarchy, every column of a subject marching memory block MM.sub.ij is accessed with an address at the lower level, and every marching memory block MM.sub.ij are directly accessed with its own address for each marching memory block MM.sub.ij at the higher level.
(360) Alternatively, a virtual storage mechanism can be used for the access methodology of the complex marching memory. In the virtual storage mechanism, the marching memory blocks MM.sub.ij (i=1 to s; j=1 to t), or the marching memory cores to be used are scheduled just like pages in a virtual memory. The scheduling is decided at compilation run if any. For example, in the multi-level caches architecture, the multi-level caches generally operate by checking the smallest Level 1 (L1) cache first, and if the L1 cache hits, the processor proceeds at high speed. If the smaller L1 cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked. For the access methodology of the complex marching memory, the L2 cache-like memory can support the virtual indexing mechanism, because the size of L2 cache corresponds to the size of the complex marching memory, and the size of a marching memory block MM.sub.ij corresponds to the size of smallest L1 cache.
(361) Since the achievement of the complex marching memory encompassing one thousand of marching memory blocks, or one thousand of cores is relatively easy as stated above, and in the complex marching memory, the access of any column is basically available at the CPU's clock rate, even at the worst case, the speed of the complex marching memory keeps the speed of the conventional DRAM.
(362) Furthermore, a plurality of complex marching memory chips, or a plurality of macro complex marching memory blocks MMM.sub.1, MMM.sub.2, . . . , MMM.sub.k, can be mounted on a first circuit board having external-connection pins P.sub.1, P.sub.2, . . . , P.sub.s−1, P.sub.s (“s” may be any integer determined by unit of byte, or word size) so as to implement a multichip module of the complex marching memory, or “a complex marching memory module” as shown in FIG. 81, although the illustration of the circuit board is omitted. In the hybrid assembly of macro complex marching memory blocks MMM.sub.1, MMM.sub.2, . . . , MMM.sub.k, the first macro complex marching memory block MMM.sub.1 may monolithically integrate one thousand of marching memory blocks MM.sub.111, MM.sub.121, MM.sub.131, . . . , MM.sub.1(t−1)1, MM.sub.1t1; MM.sub.211, . . . , ; MM.sub.(s−1)11 . . . ; MM.sub.s11, MM.sub.s21, . . . , MM.sub.s(t−1)1, MM.sub.st1 on a first semiconductor chip, the second macro complex marching memory block MMM.sub.2 may monolithically integrate one thousand of marching memory blocks MM.sub.112, MM.sub.122, MM.sub.132, . . . , MM.sub.1(t−1)2, MM.sub.1t2; MM.sub.212, . . . ; MM.sub.(s−1)12 . . . ; MM.sub.s12, MM.sub.s22, . . . , MM.sub.s(t−1)2, MM.sub.st2 on a second semiconductor chip, . . . , and the k-th macro complex marching memory block MMM.sub.k may monolithically integrate one thousand of marching memory blocks MM.sub.11k, MM.sub.12k, MM.sub.13k, . . . , MM.sub.1(t−1)k, MM.sub.1tk; MM.sub.21k, . . . , ; MM.sub.(s−1)1k . . . ; MM.sub.s1k, MM.sub.s2k, . . . , MM.sub.s(t−1)k, MM.sub.stk on a k-th semiconductor chip, for example. And the first complex marching memory module hybridly assembling the macro complex marching memory blocks MMM.sub.1, MMM.sub.2, . . . , MMM.sub.k can be connected to a second complex marching memory module hybridly assembling the macro complex marching memory block MMM.sub.k+1 and others on a second circuit board through the external-connection pins P.sub.1, P.sub.2, . . . , P.sub.s−1, P.sub.s. Here, the macro complex marching memory block MMM.sub.k+1 may monolithically integrate one thousand of marching memory blocks MM.sub.11(k+1), MM.sub.12(k+1), MM.sub.13(k+1), . . . , MM.sub.1(t−1)(k+1), MM.sub.1t(k+1); MM.sub.21(k+1); . . . , MM.sub.(s−1)1(k+1) . . . ; MM.sub.s1(k+1), MM.sub.s2(k+1), . . . , MM.sub.s(t−1)(k+1), MM.sub.st(k+1) on a semiconductor chip, for example. In addition, if dual lines of the hybrid assembly of macro complex marching memory blocks are implemented, a dual in-line module of complex marching memory can be established.
(363) In the configuration of the complex marching memory modules shown in FIG. 81, by using triple-level hierarchy, every column of a subject marching memory block MM.sub.iju (u=1 to k; “k” is any integer greater than or equal to two) is accessed with an address at the lowest level, every marching memory block MM.sub.iju are accessed with its own address for each marching memory block MM.sub.iju at the middle level, and every macro marching memory block MMM.sub.u (u=1 to k) may be directly accessed with its own address at the highest level, which facilitate accessing to a remote column of the marching memory for scalar data or program instructions.
(364) Alternatively, very similar to DRAM rank architecture encompassing a set of DRAM chips that operate in lockstep fashion to command in a memory, in which the DRAM chips inside the same rank are accessed simultaneously, the plurality of macro complex marching memory blocks MMM.sub.1, MMM.sub.2, . . . , MMM.sub.k, can be random accessed simultaneously, and with the above-mentioned double-level hierarchy methodology, every column of a subject marching memory block MM.sub.iju (u=1 to k) is accessed with an address at the lower level, and every marching memory block MM.sub.iju are directly accessed with its own address for each marching memory block MM.sub.iju at the higher level.
(365) Still alternatively, a virtual storage mechanism can be used for the access methodology of the complex marching memory, in which the marching memory cores to be used are scheduled just like pages in the virtual memory. The scheduling can be decided at compilation run if any.
(366) Since the data transfer between the marching main memory 31 and the processor 11 is achieved at a very high speed, the cache memory employed in the conventional computer system is not required, and the cache memory can be omitted. However, similar to the organization shown in FIG. 56, a marching-data cache memory 21b implemented by the complex marching memory scheme can be used with more smaller size of marching memory blocks, or more smaller size of marching memory cores. For example, a plurality of marching memory cores with 1 kbits, 512 bits, or 256 bits capacity can be deployed on a semiconductor chip so as to implement the marching-data cache memory 21b, while a plurality of marching memory cores MM.sub.ij (i=1 to s; j=1 to t; and s*t=1000) with 256 kbits capacity are deployed on the semiconductor chip 66 so as to implement marching main memory 31. For example, with the virtual storage mechanism, each of the marching memory cores can be randomly accessed.
(367) Alternatively, one-dimensional array of marching memory blocks, or marching memory cores, being deployed vertically on a semiconductor chip, can implement a marching cache memory. Each of the marching memory cores includes a single horizontal array of memory units, and the number of memory units deployed horizontally is smaller than the number of memory units employed in the marching memory cores for the marching main memory 31. For example, with the virtual storage mechanism, each of the marching memory cores can be randomly accessed.
(368) Furthermore, a plurality of marching memory blocks, or a plurality of marching memory cores can be deployed vertically on a semiconductor chip, each of the marching memory blocks consist of a single memory units, each of the memory units having a sequence of bit-level cells configured to store information of byte size or word size so as to implement a marching register file by the complex marching memory scheme.
(369) In the further case of scaling the marching memory core, a plurality of marching memory cores with minimized size, or one bit capacity can be deployed on a semiconductor chip by the complex marching memory scheme, which may correspond to the structure of conventional SRAM. Therefore, marching-data register file 22b implemented by one-bit marching memory cores can be connected to the ALU 112, similar to the organizations shown in FIGS. 55 and 56. Similar to the operation of SRAM, each of the one-bit marching memory cores can be randomly accessed.
(370) The present invention includes various exemplary embodiments and modifications and the like, which are not detailed above. Therefore, the scope of the present invention will be defined in the following claims.
