Field-effect transistor arrangement and method for setting a drain current of a field-effect transistor

Abstract

A field-effect transistor system is provided that comprises a field-effect transistor having a back-gate terminal that can be adjusted by a back-gate voltage, a gate-source voltage and a drain-source voltage additionally being present at the field-effect transistor, and a drain current flowing through the field-effect transistor. In addition, the field-effect transistor system includes a control unit connected to the back-gate terminal, which unit is set up to set the drain current flowing through the field-effect transistor to a setpoint current via a controlling of the back-gate voltage at the back-gate terminal, the controlling of the back-gate voltage taking place as a function of at least the gate-source voltage. In addition, a method is provided for setting a drain current of a field-effect transistor.

Claims

1. A field-effect transistor system, comprising: a field-effect transistor having a back-gate terminal that can be adjusted by a back-gate voltage, a gate-source voltage and a drain-source voltage being present at the field-effect transistor, and a drain current flowing through the field-effect transistor; and a control unit connected to the back-gate terminal, the control unit configured to set the drain current flowing through the field-effect transistor to a setpoint current by controlling the back-gate voltage at the back-gate terminal, the controlling of the back-gate voltage taking place as a function of at least the gate-source voltage, wherein the control unit includes a memory to store data describing an electrical behavior of the field-effect transistor, and is configured to control the back-gate voltage of the field-effect transistor using the data.

2. The field-effect transistor system as recited in claim 1, wherein the control unit is configured to control the back-gate voltage as a function of the drain-source voltage at the field-effect transistor.

3. The field-effect transistor system as recited in claim 1, wherein the setpoint current is independent of the drain-source voltage in a saturation region of the field-effect transistor.

4. The field-effect transistor system as recited in claim 1, wherein the control unit is configured to control the back-gate voltage as a function of the drain current through the field-effect transistor.

5. The field-effect transistor system as recited in claim 1, wherein the data describing the electrical behavior of the field-effect transistor includes a set of characteristic curves of the drain current as a function of the drain-source voltage for a plurality of different values of the gate-source voltage.

6. A field-effect transistor system, comprising: a field-effect transistor having a back-gate terminal that can be adjusted by a back-gate voltage, a gate-source voltage and a drain-source voltage being present at the field-effect transistor, and a drain current flowing through the field-effect transistor; a control unit connected to the back-gate terminal, the control unit configured to set the drain current flowing through the field-effect transistor to a setpoint current by controlling the back-gate voltage at the back-gate terminal, the controlling of the back-gate voltage taking place as a function of at least the gate-source voltage, wherein the control unit is configured to control the back-gate voltage as a function of the drain current through the field-effect transistor; and a reference field-effect transistor at which a gate-source voltage is present that is the same as the gate-source voltage of the field-effect transistor, and a constant drain-source voltage and a constant back-gate voltage being present at the reference field-effect transistor.

7. The field-effect transistor system as recited in claim 6, wherein the control unit is configured to control the back-gate voltage of the field-effect transistor from a known electrical behavior of the field-effect transistor.

8. The field-effect transistor system as recited in claim 6, wherein the control unit is configured to control the back-gate voltage at the field-effect transistor in such a way that a drain current through the reference field-effect transistor is identical to the drain current through the field-effect transistor.

9. The field-effect transistor system as recited in claim 6, wherein the control unit includes a memory to store data describing an electrical behavior of the field-effect transistor, and is configured to control the back-gate voltage of the field-effect transistor using the data.

10. An electrical circuit, comprising: an amplifier circuit including one or more field-effect transistor systems, each of the one or more of the field-effect transistor systems including: a field-effect transistor having a back-gate terminal that can be adjusted by a back-gate voltage, a gate-source voltage and a drain-source voltage being present at the field-effect transistor, and a drain current flowing through the field-effect transistor; and a control unit connected to the back-gate terminal, the control unit configured to set the drain current flowing through the field-effect transistor to a setpoint current by controlling the back-gate voltage at the back-gate terminal, the controlling of the back-gate voltage taking place as a function of at least the gate-source voltage, wherein the control unit includes a memory to store data describing an electrical behavior of the field-effect transistor, and is configured to control the back-gate voltage of the field-effect transistor using the data.

11. A method for setting a drain current of a field-effect transistor, comprising the following steps: providing a field-effect transistor having a back-gate terminal that can be adjusted by a back-gate voltage, a gate-source voltage and a drain-source voltage being present at the field-effect transistor, and a drain current flowing through the field-effect transistor; setting the drain current flowing through the field-effect transistor to a setpoint current via a controlling of the back-gate voltage at the back-gate terminal by a control unit connected to the back-gate terminal, the controlling of the back-gate voltage taking place as a function of at least the gate-source voltage, wherein the control unit includes a memory to store data describing an electrical behavior of the field-effect transistor, and controls the back-gate voltage of the field-effect transistor using the data.

12. The method as recited in claim 11, wherein the controlling of the back-gate voltage takes place as a function of the drain-source voltage.

13. The method as recited in claim 11, wherein the setpoint current in a saturation region of the field-effect transistor is independent of the drain-source voltage.

14. The method as recited in claim 11, wherein the controlling of the back-gate voltage takes place as a function of the drain current flowing through the field-effect transistor.

15. The method as recited in claim 14, further comprising the following step: providing a reference field-effect transistor at which a gate-source voltage is applied that is the same as the gate-source voltage of the field-effect transistor, a constant drain-source voltage and a constant back-gate voltage being applied at the reference field-effect transistor.

16. The method as recited in claim 15, wherein the controlling of the back-gate voltage by the control unit takes place in such a way that a drain current through the reference field-effect transistor is identical to the drain current through the field-effect transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments of the present invention are explained in more detail on the basis of the figures and the description below.

(2) FIG. 1 shows an output characteristic curve field of a field-effect transistor from the related art.

(3) FIG. 2 shows a field-effect transistor system according to the present invention according to a first specific embodiment of the present invention.

(4) FIG. 3 shows a field-effect transistor system according to a second specific embodiment of the present invention.

(5) FIG. 4 shows an example of an output characteristic curve field of a field-effect transistor system according to the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(6) FIG. 1 shows an output characteristic curve field of a field-effect transistor from the related art, in which a drain current I.sub.D flowing through a field-effect transistor is plotted as a function of drain-source voltage V.sub.DS for a multiplicity of different gate-source voltages V.sub.GS. At the field-effect transistor according to the related art, here an adjustable but constant back-gate voltage is set at its back-gate terminal, which is not explicitly shown here. The functional curve of drain current I.sub.D for each associated gate-source voltage V.sub.GS shows, as a function of drain-source voltage V.sub.DS, a linear region 40 for sufficiently small drain-source voltages V.sub.DS and a saturation region 50 for sufficiently large drain-source voltages V.sub.DS; the regions are separated from one another by a separating line for clarity. The curve shown in FIG. 1 of drain current I.sub.D as a function of drain-source voltage V.sub.DS shows that in saturation region 50, also called the pinch-off region, the drain current continues to climb as a function of the drain-source voltage, which is undesirable and is attributable to parasitic effects. The effect disadvantageously results in a lower small signal drain-source resistance, and thus a lower intrinsic gain.

(7) FIG. 2 shows a field-effect transistor system 1 according to a first specific embodiment of the present invention. Here, field-effect transistor system 1 is advantageously integrated in an electrical circuit, in this specific case an amplifier circuit 100.

(8) Field-effect transistor system 1 here includes a field-effect transistor T having a back-gate terminal BG that can be adjusted by a back-gate voltage V.sub.BG. In addition, a gate-source voltage V.sub.GS and a drain-source voltage V.sub.DS are present at field-effect transistor T, and a drain current I.sub.D also flows through field-effect transistor T. Purely as an example, in the present embodiment a source terminal S of field-effect transistor T is grounded, so that the voltage at a gate terminal G of field-effect transistor T corresponds to gate-source voltage V.sub.GS. However, the present invention is not limited to a grounding of source terminal S.

(9) In addition, field-effect transistor system 1 includes a control unit 10 that is connected to back-gate terminal BG of field-effect transistor T. Control unit 10 is set up to set drain current I.sub.D flowing through field-effect transistor T to a setpoint current via a controlling of back-gate voltage V.sub.BG at back-gate terminal BG. The controlling of back-gate voltage V.sub.BG is done as a function of at least the gate-source voltage V.sub.GS.

(10) Field-effect transistor system 1 has the advantage that undesirable parasitic effects can be compensated via the controlling of back-gate voltage V.sub.BG. For example, the setpoint current can be selected such that the small signal drain-source resistance is correspondingly increased, thus improving the intrinsic gain of field-effect transistor T.

(11) The present invention provides a feedback control system, or a control loop, in which at least gate-source voltage V.sub.GS acts as input variable in order to control back-gate voltage V.sub.BG as manipulated variable, and in this way to set the drain current to a setpoint current.

(12) In addition, control unit 10 can also control back-gate voltage V.sub.BG as a function of drain-source voltage V.sub.DS at field-effect transistor T. For example, using drain-source voltage V.sub.DS, for a given gate-source voltage V.sub.GS the region in which field-effect transistor T is operating can be determined, for example whether field-effect transistor T is in saturation region 50 or in linear region 40.

(13) Control unit 10 can for example be set up to directly detect, or acquire, the drain-source voltage V.sub.DS and gate-source voltage V.sub.GS at field-effect transistor T. Alternatively, these can also be acquired by a corresponding measuring unit (not explicitly shown) and provided to control unit 10.

(14) In particular, the setpoint current in saturation region 50 of field-effect transistor T can be independent of drain-source voltage V.sub.DS. In this way, back-gate voltage V.sub.BG is controlled as a function of the input variable in such a way that drain current I.sub.D correspondingly agrees with this constant setpoint current. In this way, the intrinsic gain can be maximized.

(15) In this particular specific embodiment, the controlling of back-gate voltage V.sub.BG takes place only as a function of gate-source voltage V.sub.GS and back-gate voltage V.sub.BG; the present invention is not limited thereto.

(16) In this specific embodiment shown as an example, control unit 10 is in addition set up to control back-gate voltage V.sub.BG of field-effect transistor T from a known electrical behavior of field-effect transistor T. For this purpose, for example data sets from field-effect transistor T that describe the electrical behavior of field-effect transistor T can be stored in a memory 15. Control unit 10 can then access this memory 15. For example, control unit 10 can include an internal memory 15 in which corresponding data are stored concerning the electrical behavior of field-effect transistor T. For example, the data can indicate the output characteristic curves in the form of an I.sub.D(V.sub.DS) functional relationship for various values of gate-source voltages V.sub.GS, similar to FIG. 1.

(17) Control unit 10 can then determine a suitable correction variable for back-gate voltage V.sub.BG by acquiring gate-source voltage V.sub.GS and, optionally, drain-source voltage V.sub.DS, through comparison with the known behavior. In this way, a desired setpoint current, which is for example constant in saturation region 50, can then correspondingly be set by field-effect transistor 1 via back-gate voltage V.sub.BG. In this specific embodiment, it is advantageous that drain-current I.sub.D does not explicitly have to be ascertained as input variable. However, compared to the embodiment shown in FIG. 3, an increased design outlay and a complicated control design for control unit 10 are required.

(18) An example of an output characteristic curve field of such a field-effect transistor system 1 is shown for example in FIG. 4.

(19) Such a field-effect transistor system 1 can be integrated in an electrical circuit, as is shown as an example in FIG. 2. In the present example, the electrical circuit is realized as an amplifier circuit 100. This amplifier circuit 100 is designed in the form of a typical source circuit, the present invention not being limited to a particular circuit. In this embodiment, amplifier circuit 100 includes an operating voltage V.sub.DS that is connected via a load resistor R1 to drain terminal D of field-effect transistor T. A part of operating voltage V.sub.DS is thus always dropped at load resistor R1. Here, load resistor R1 also limits drain current I.sub.D. The input voltage of this amplifier circuit 100 is applied at gate terminal G of field-effect transistor T in this embodiment. An amplified output voltage V.sub.out of amplifier circuit 100 can then be picked off at drain terminal D. Field-effect transistor system 1 can thus be used in the place of a standard field-effect transistor from the related art, the electrical circuit, in this case the amplifier circuit, having no, or reduced, parasitic behavior in comparison with a circuit from the related art.

(20) FIG. 3 shows a field-effect transistor system 1 according to a second specific embodiment of the present invention. In the following, the differences from the specific embodiment described in FIG. 2 are described in more detail. For the features in common, reference is made to the description relating to FIG. 2.

(21) As in the specific embodiment of FIG. 2, field-effect transistor system 1 includes a control unit 10 that is connected to back-gate terminal BG of field-effect transistor T. Control unit 10 is set up to set drain current I.sub.D flowing through field-effect transistor T to a setpoint current via a controlling of back-gate voltage V.sub.BG at back-gate terminal BG. In this specific embodiment, the controlling of back-gate voltage V.sub.BG is done as a function of gate-source voltage V.sub.GS and, in addition, as a function of drain current I.sub.D through field-effect transistor T. Optionally, in this specific embodiment the controlling can also be done as a function of drain-source voltage V.sub.DS. Drain current I.sub.D can be acquired for example by control unit 10, or can be measured by another measuring unit and supplied to control unit 10. In this way, control unit 10 is provided with all electrical information, namely concerning gate-source voltage V.sub.GS and drain-source voltage V.sub.DS and drain current I.sub.D, for the realization of a control loop having a reference element.

(22) In this preferred specific embodiment, a reference field-effect transistor T1 is used as reference element. In this specific embodiment, a gate-source voltage V.sub.GS1, which is identical to gate-source voltage V.sub.GS of field-effect transistor T, is present at reference field-effect transistor T1.

(23) In the present specific embodiment, this agreement is realized by a source terminal S1 of reference field-effect transistor T1 that is grounded, as is source terminal S, and in addition is at a potential due to an electrical connection of gate terminal G of field-effect transistor T to a gate terminal G1 of reference field-effect transistor T1. Due to the coupling of gates G, G1, their electrical potentials are thus always identical. Because source terminals S, S1 are also at the same potential, because they are both grounded, the same gate-source voltage V.sub.GS=V.sub.GS1 is always present at reference field-effect transistor T1 and at field-effect transistor T.

(24) In this specific embodiment, in addition a constant drain-source voltage V.sub.DS1 and a constant back-gate voltage V.sub.BG1 are always applied at reference field-effect transistor T1. As a result, a drain current I.sub.D1 that is a function only of gate-source voltage V.sub.Gs flows through reference field-effect transistor T1 to source terminal S1. Thus, this drain current I.sub.D1 is independent of drain-source voltage V.sub.DS.

(25) Control unit 10 can then control back-gate voltage V.sub.BG at field-effect transistor T in such a way that drain current I.sub.D through reference field-effect transistor T1 is identical to drain current I.sub.D1 through field-effect transistor T. As a result, in addition drain current I.sub.D is also independent of drain-source voltage V.sub.DS. Drain current I.sub.D1 thus corresponds to the setpoint current of the control loop.

(26) Through this realization, the output characteristic curves can thus be held constant in saturation region 50 of field-effect transistor 1; see also for example FIG. 4.

(27) Field-effect transistor system 1 can be integrated in an electrical circuit, for example an amplifier circuit 100; see the embodiment in the description relating to FIG. 2.

(28) FIG. 4 shows an example of an output characteristic curve field of a field-effect transistor system 1 according to the present invention. Here, a drain current I.sub.D is plotted as a function of drain-source voltage V.sub.DS for a multiplicity of different gate-source voltages V.sub.GS.

(29) The functional curve of drain current I.sub.D for each gate-source voltage V.sub.GS shows, as in FIG. 1 of the related art, a linear region 40 for sufficiently small drain-source voltages V.sub.DS, and a saturation region 50 for sufficiently large drain-source voltages V.sub.DS, the respective regions being separated by a separating line for clarity.

(30) In contrast to the output characteristic curves shown in FIG. 1, the output characteristic curves in the region of saturation region 50 show an almost constant curve as a function of drain-source voltage V.sub.DS, or an at least significantly reduced rise. In other words, drain current I.sub.D is independent of drain-source voltage V.sub.DS. Advantageously, this results in a correspondingly increased small signal drain-source resistance r.sub.DS and thus also an improved intrinsic gain A.sub.i.

(31) Although the present invention has been illustrated and described in detail in relation to preferred exemplary embodiments, the present invention is not limited by the disclosed examples, and other variations can be derived therefrom by a person skilled in the art without departing from the scope of the present invention.