CHIP RESISTOR AND METHOD OF PRODUCING THEREOF

Abstract

A chip resistor 10 comprises: a insulating substrate 1; a pair of upper surface electrodes 2; a resistor 3; a pair of lower surface electrodes 5; a pair of resin electrode layers 6 made of synthetic resin materials containing conductive particles and laminated on the pair of lower surface electrodes 5; a pair of end face electrodes 7; and a pair of external electrodes 8, wherein the pair of the lower surface electrodes 5 is made of metal thin film layers formed as thin films on a mounting surface of the insulating substrate 1, respectively, and includes exposed portions 5a exposed from the resin electrode layers 6, respectively, and the pair of external electrodes 8 is in contact with the exposed portions 5a of the lower surface electrodes 5 and entire surfaces of the resin electrode layers 6, respectively. [Selected drawing] FIG. 1

Claims

1. A chip resistor comprising: a rectangular parallelepiped insulating substrate that includes a component surface and a mounting surface located on mutually opposite sides in a thickness direction; a pair of upper surface electrodes that is provided at both ends, respectively, in a longitudinal direction on the component surface of the insulating substrate; a resistor that bridges between the pair of upper surface electrodes; a pair of lower surface electrodes that is provided at both ends, respectively, in the longitudinal direction on the mounting surface of the insulating substrate; a pair of resin electrode layers that is laminated on the pair of lower surface electrodes, respectively, each of the pair of resin electrode layers being made of a synthetic resin material containing conductive particles; a pair of end face electrodes that electrically connects the pair of upper surface electrodes and the pair of lower surface electrodes; and a pair of external electrodes that covers at least the pair of end face electrodes, each of the pair of external electrodes being made of a plating material, wherein the pair of lower surface electrodes is made of metal thin film layers formed as thin films on the mounting surface of the insulating substrate, respectively, and includes exposed portions exposed from the pair of resin electrode layers, respectively, and the pair of external electrodes is in contact with the exposed portions of the pair of lower surface electrodes and entire surfaces of the pair of resin electrode layers, respectively.

2. The chip resistor according to claim 1, wherein each of the exposed portions of the lower surface electrodes is formed into a channel shape so as to surround an outer periphery of each of the resin electrode layers.

3. The chip resistor according to claim 1, wherein each of the pair of resin electrode layers is provided with a cutout portion that opens toward an end face of the insulating substrate, and each of the exposed portions of the pair of lower surface electrodes is formed on an outer peripheral side of each of the resin electrode layers and in the cutout portion, respectively.

4. The chip resistor according to claim 1, wherein each of the resin electrode layers is formed at an inner position away from an end face of the insulating substrate, and each of the exposed portions of the pair of lower surface electrodes is formed into a frame shape so as to surround an entire periphery of each of the resin electrode layers.

5. The chip resistor according to claim 4, wherein each of the end face electrodes is formed of a metal thin film by sputtering metal particles toward the end face of the insulating substrate, and the metal thin film covers at least a portion of each of the exposed portions of the pair of lower surface electrodes.

6. A method of producing a chip resistor, comprising the steps of: forming, on a component surface of an insulating substrate, a resistor and upper surface electrodes connected to both ends of the resistor, respectively; forming, in a central portion of a mounting surface located on an opposite side of the component surface of the insulating substrate, a mask made of a soluble material; forming, on the mounting surface exposed from the mask, lower surface electrodes by sputtering metal particles, respectively; after removing the mask, forming resin electrode layers by printing synthetic resin materials containing conductive particles on the lower surface electrodes with portions of the lower surface electrodes being exposed, respectively; forming end face electrodes that electrically connect between the upper surface electrodes and the lower surface electrodes by sputtering metal particles on end faces of the insulating substrate, respectively; and forming external electrodes that cover the end face electrodes, the exposed portions of the lower surface electrodes, and entire surfaces of the resin electrode layers by electroplating after forming the end face electrodes, respectively.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a cross-sectional view of a chip resistor according to a first embodiment.

[0019] FIG. 2 is a rear view of the chip resistor according to the first embodiment.

[0020] Each of FIGS. 3A~3E is a cross-sectional view illustrating production processes of the chip resistor.

[0021] Each of FIGS. 4F~4J is a cross-sectional view illustrating the production processes of the chip resistor.

[0022] FIG. 5 illustrates a flowchart of the production processes of the chip resistor.

[0023] FIG. 6 is a cross-sectional view illustrating the chip resistor being mounted.

[0024] FIG. 7 is a cross-sectional view of a chip resistor according to a second embodiment.

[0025] FIG. 8 is a rear view of the chip resistor according to the second embodiment.

[0026] FIG. 9 is a rear view of a chip resistor according to a third embodiment.

[0027] FIG. 10 is a rear view of a chip resistor according to a fourth embodiment.

[0028] FIG. 11 is a rear view of a chip resistor according to a fifth embodiment.

DESCRIPTION OF EMBODIMENTS

[0029] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0030] FIG. 1 is a cross-sectional view of a chip resistor 10 according to a first embodiment, and FIG. 2 is a rear view of the chip resistor 10 according to the first embodiment.

[0031] As illustrated in FIG. 1 and FIG. 2, the chip resistor 10 according to the first embodiment includes a rectangular parallelepiped insulating substrate 1 having a component surface and a mounting surface, which are located on mutually opposite sides in the thickness direction, a pair of upper surface electrodes 2 formed at both ends, respectively, in the longitudinal direction on the component surface (upper surface in FIG. 1) of the insulating substrate 1, a resistor 3 that bridges between the pair of upper surface electrodes 2, a protective layer 4 that has a double layer structure and covers the resistor 3, a pair of lower surface electrodes 5 formed at both ends, respectively, in the longitudinal direction on the mounting surface (lower surface in FIG. 1) of the insulating substrate 1, a pair of resin electrode layers 6 laminated on these lower surface electrodes 5, a pair of end face electrodes 7 that electrically connects the upper surface electrodes 2 and the lower surface electrodes 5, and a pair of external electrodes 8 that covers the end face electrodes 7.

[0032] For obtaining the insulating substrate 1, a large-sized substrate, which will be described later, is divided along divisions groove extending in a grid pattern into a plurality of substrates. The large-sized substrate from which the insulating substrate 1 is obtained is made of a ceramic substrate mainly composed of alumina (Al.sub.2O.sub.3).

[0033] The pair of upper surface electrodes 2 is obtained by screen-printing Ag-Pd paste on the upper surface of the large-sized substrate and then drying and sintering the paste.

[0034] The resistor 3 is obtained by screen-printing resistor paste, such as ruthenium oxide, on the upper surface of the large-sized substrate and then drying and sintering the paste. Both ends of the resistor 3 in the longitudinal direction overlap the pair of upper surface electrodes 2, respectively. Although not illustrated, a trimming groove for adjusting a resistance value is formed in the resistor 3.

[0035] The protective layer 4 includes an undercoat layer 4a for covering the resistor 3 and an overcoat layer 4b for covering the undercoat layer 4a. The undercoat 4a is obtained by screen-printing glass paste and then drying and sintering the paste. The overcoat layer 4b is obtained by screen-printing resin paste, such as epoxy resin or phenolic resin, and then heating and curing (baking) the paste. Note that the undercoat layer 4a is provided before the trimming groove is formed in the resistor 3, and the overcoat layer 4b is provided after the trimming groove is formed in the resistor 3.

[0036] The pair of lower surface electrodes 5 is formed by sputtering Ni—Cr, Ti—Ni, Cu, or Ni—Cu on the back surface of the large-sized substrate.

[0037] The pair of resin electrode layers 6 is formed by screen-printing synthetic resin (for example, epoxy resin or phenolic resin) paste containing conductive particles such as Ag, Ni, or Cu on the lower surface electrodes 5 and then heating and curing the paste. The lower surface electrodes 5 and the resin electrode layers 6 are formed to have a laminate structure, excluding portions of the lower surface electrodes 5, and the portions of the lower surface electrodes 5 (upper and lower end portions in FIG. 2) which are in contact with the long sides of the insulating substrate 1 are exposed portions 5a exposed from the resin electrode layers 6.

[0038] The pair of end face electrodes 7 is formed by sputtering Ni—Cr or the like, and electrically connects the upper surface electrodes 2 and the lower surface electrodes 5 which are spaced apart from each other with the end faces of the insulating substrate 1 interposed therebetween. Note that the end face electrodes 7 cover the surfaces of the upper surface electrodes 2 located near the end faces of the insulating substrate 1 while making the surfaces of the upper surface electrodes 2 other than those above and the overcoat layer 4b exposed without covering them. Furthermore, the end face electrodes 7 cover the exposed portions 5a of the lower surface electrodes 5 and portions of the resin electrode layers 6, which are located near the end faces of the insulating substrate 1, while making the exposed portions 5a other than those described above and the surfaces of the resin electrode layers 6 other than those described above exposed.

[0039] Each of the pair of external electrodes 8 is formed to have a double layer structure including an inner barrier layer 8a and an outer external connection layer 8b, and the barrier layer 8a is an Ni plating layer formed by electroplating and the external connection layer 8b is an Sn plating layer formed by electroplating. The external electrodes 8 are formed so as to cover the entire surfaces of the end face electrodes 7, the surfaces of the upper surface electrodes 2 exposed from the end face electrodes 7, and the exposed portions 5a of the lower surface electrodes 5 and the resin electrode layers 6 which are exposed from the end face electrodes 7.

[0040] Next, the processes of producing the chip resistor 10 having the structure as described above will be described with reference to FIGS. 3 to FIG. 5. FIGS. 3 and FIGS. 4 are cross-sectional views illustrating the production processes of the chip resistor 10, and FIG. 5 illustrates a flowchart of the production processes of the chip resistor 10.

[0041] Firstly, as illustrated in step S1 of FIG. 3(a) and FIG. 5, a large-sized substrate 1A having the shape of a sheet, from which a plurality of insulating substrates 1 is obtained is prepared. The large-sized substrate 1A is provided with primary division grooves and secondary division grooves which extend in a grid pattern, and each of the squares partitioned by these division grooves serves as one chip-forming area. FIGS. 3 and FIGS. 4 illustrate the cross-sections of one chip-forming area, however, practically, processes described below are carried out collectively for the large-sized substrate corresponding to a plurality of chip-forming areas.

[0042] That is, in step S2 of FIG. 5, as illustrated in FIG. 3(b), for forming, on the upper surface of the large-sized substrate 1A, the upper surface electrodes 2 facing each other across the chip-forming areas, the Ag-Pd paste is screen-printed in an area sandwiched between the secondary division grooves on the upper surface of the large-sized substrate 1A so as to extend across each of the primary division grooves and then dried and sintered.

[0043] Next, in step S3 of FIG. 5, as illustrated in FIG. 3(c), for forming the resistor 3 that extends across the pair of upper surface electrodes 2, the resistor paste such as ruthenium oxide is screen-printed on the upper surface of the large-sized substrate 1A and then dried and sintered.

[0044] Next, in step S4 of FIG. 5, as illustrated in FIG. 3(d), for forming the undercoat layer 4a that covers the resistor 3, the glass paste is screen-printed and then dried and sintered. Then, a trimming groove (not illustrated) is formed in the resistor 3 from above the undercoat layer 4a to adjust the resistance value.

[0045] Next, in step S6 of FIG. 5, as illustrated in FIG. 3(e), for forming the overcoat layer 4b that covers portions of the upper surface electrodes 2 and the entire of the resistor 3, the epoxy resin paste is screen-printed from above the undercoat layer 4a and then heated and cured. These undercoat layer 4a and overcoat layer 4b form the double layered protective layer 4 for covering the resistor 3.

[0046] Next, in step S6 of FIG. 5, as illustrated in FIG. 4(f), for forming, in the central portion of each of the chip-forming areas on the back surface of the large-sized substrate 1A, a mask 9 having the shape of a band, the masking paste is screen-printed in the area sandwiched between the primary division grooves on the back surface of the large-sized substrate 1A so as to extend across each of the secondary division grooves and then dried.

[0047] Next, in step S7 of FIG. 5, as illustrated in FIG. 4(g), for forming, on each of the chip-forming areas on the back surface of the large-sized substrate 1A, the lower surface electrodes 5 facing each other with the primary division grooves interposed therebetween, metal particles such as an Ni alloy (Ni—Cr, Ti—Ni, Ni—Cu or the like) and Cu are applied by sputtering toward the back surface of the large-sized substrate 1A. Thus, forming the lower surface electrodes 5 as metal thin film layers provided on the large-sized substrate 1A by sputtering enhances the adhesion of the lower surface electrodes 5 to the large-sized substrate (insulating substrate) 1A.

[0048] Next, in step S8 of FIG. 5, the mask 9 is removed by ultrasonic cleaning. Thereafter, in step S9 of FIG. 5, as illustrated in FIG. 4(h), forming the resin electrode layers 6 overlapping the lower surface electrodes 5, the epoxy resin paste or phenolic resin paste is screen-printed from above the lower surface electrodes 5 and then heated and cured (baked). At this time, forming the resin electrode layers 6 a little smaller in size than the lower surface electrodes 5 causes the exposed portions 5a exposed from the resin electrode layers 6 to be formed at both end portions of the lower surface electrodes 5 which are closer to the secondary division grooves (see FIG. 2).

[0049] The processes described above are carried out collectively for the large-sized substrate 1A. In the next process, the large-sized substrate 1A is divided by primary breaking (primary division) along the primary division grooves to obtain a strip-shaped substrate 1B.

[0050] Thereafter, in step S10 of FIG. 5, as illustrated in FIG. 4(i), for forming, on both end faces of the strip-shaped substrate 1B, the end face electrodes 7 that electrically connect between the upper surface electrodes 2 and the lower surface electrodes 5, Ni—Cr is applied on the divided faces of the strip-shaped substrate 1B by sputtering. The end face electrodes 7 cover portions of the surfaces of the upper surface electrodes 2 which are located closer to the divided faces of the strip-shaped substrate 1B, the exposed portions 5a of the lower surface electrodes 5 and portions of the surfaces of the resin electrode layers 6 which are located closer to the divided faces of the strip-shaped substrate 1B, respectively.

[0051] Next, the strip-shaped substrate 1B is divided by secondary breaking (secondary division) along the secondary division grooves to obtain a single chip 10C having the size equivalent to that of the chip resistor 10.

[0052] Next, in step S11 of FIG. 5, the single chip 1C which has been obtained by division into each piece is electroplated to form the barrier layers 8a for covering the upper surface electrodes 2, the end face electrodes 7, the resin electrode layers 6, and the exposed portions 5a of the lower surface electrodes 5. At this time, the lower surface electrodes 5 made of metal thin film layers having the low electrical resistivity have been formed on the back surface (mounting surface of the insulating substrate 1) of the single chip 1C and also the resin electrode layers 6 having the electrical resistivity higher than that of the metal thin film layers have been formed with portions of the lower surface electrodes 5 exposed, and thus this stabilizes the current flowing through the resin electrode layers 6 in the process of forming the external electrodes 8 by electroplating and thus makes the thickness of the plating films of the barrier layers 8a uniform. Furthermore, the plating layers are formed starting from the exposed portions 5a of the lower surface electrodes 5 having the low electrical resistivity toward the resin electrode layers 6 having the high electrical resistivity, which enables the barrier layers 8a to be formed on the resin electrode layers 6 with the high peel strength being maintained.

[0053] Thereafter, the single chip 1C is electroplated with Sn to form the external connection layers 8b for covering the entire surfaces of the barrier layers 8a, whereby, as illustrated in FIG. 4(j), the external electrodes 8 each having a double layer structure of the barrier layer 8a and the external connection layer 8b are formed. At this point, the chip resistor 10 as illustrated in FIG. 1 and FIG. 2 is obtained.

[0054] The chip resistor 10 thus produced as illustrated in FIG. 5 is mounted on lands 101 of the circuit board 100 with the mounting surface of the insulating substrate 1 (back surface) facing downward, and is surface-mounted on the circuit board 100 by bounding the pair of external electrodes 8 to the corresponding lands 101 via solder 102, respectively.

[0055] Exposure of the chip resistor 10 to the thermal shock during the surface mounting described above causes the thermal stress due to the difference between the coefficient of thermal expansion of the circuit board 100 and that of the insulating substrate 1 of the chip resistor 10, and the thermal stress acting on the solder joint portions may cause cracks to form. However, in the chip resistor 10 according to the present embodiment, the resin electrode layers 6 made of synthetic resin materials are laminated on the lower surface electrodes 5 to prevent the resin electrode layers 6 from easily peeling off. This enables the resin electrode layers 6 to relax the thermal stress, and thus can prevent formation of cracks.

[0056] As described above, in the chip resistor 10 according to the first embodiment, the lower surface electrodes 5 made of metal thin film layers having the low electrical resistivity have been formed on the mounting surface of the insulating substrate 1 and also the resin electrode layers 6 having the electrical resistivity higher than that of the metal thin film layers have been formed with portions of the lower surface electrodes 5 being exposed, and this stabilizes the current flowing through the resin electrode layers 6 in the process of forming the external electrodes 8 by electroplating and thus makes the thickness of the plating films uniform. In this process, the current can flow uniformly over the entire surfaces of the resin electrode layers 6 due to the laminate structure in which the resin electrode layers 6 partially overlap the portions excluding the exposed portions 5a of the lower surface electrodes 5 instead of connecting the lower surface electrodes 5 made of metal thin film layers only to the outer peripheries of the resin electrode layers 6. Furthermore, the plating layers are formed starting from the exposed portions 5a of the lower surface electrodes 5 having the low electrical resistivity toward the resin electrode layers 6 having the high electrical resistivity, which can prevent the plating layers formed on the resin electrode layers 6 from peeling off.

[0057] Thus, even when the strength of adhesion at the interfaces between the lower surface electrodes 5 formed of the metal thin film layers and the resin electrode layer 6 formed of the synthetic resin materials is low, due to the sandwich structure of the resin electrode layers 6 sandwiched between the metal thin film layers (lower surface electrodes 5) and the plating materials (external electrodes 8), the resin electrode layers 6 can be prevented from peeling off even in the chip resistor 10 after being finished, and the thermal stress caused by the thermal shock can be reliably relaxed. Furthermore, the lower surface electrodes 5 formed of the metal thin film layers having the high thermal conductivity are directly in contact with the insulating substrate 1, which causes, in the chip resistor 10 mounted on the circuit board 100, the heat generated in the resistor 3 to be radiated from the insulating substrate 1 to the circuit board 100 side through the lower surface electrodes 5 and the solder joint portions. This can realize the chip resistor 10 excellent in heat dissipation.

[0058] Furthermore, in the processes of producing the chip resistor 10, according to the procedures of forming the lower surface electrodes 5 by sputtering with the mask 9 being formed on the mounting surface of the insulating substrate 1, and then after removing the mask 9 using ultrasonic cleaning, forming the resin electrode layers 6 on the lower surface electrodes 5, the ultrasonic cleaning in removing the mask 9 does not adversely affect the resin electrode layers 6. Thus, the chip resistor 10 having high thermal shock resistance can be easily produced.

[0059] FIG. 7 is a cross-sectional view of a chip resistor 20 according to a second embodiment, and FIG. 8 is a rear view of the chip resistor 20 according to the second embodiment. The portions corresponding to those in FIG. 1 and FIG. 2 are provided with the same reference signs, and repetitive explanation therefor will be omitted.

[0060] The chip resistor 20 according to the second embodiment is different from the chip resistor 10 according to the first embodiment in that the exposed portions 5a of the lower surface electrodes 5 are formed closer to the central portions of the insulating substrate 1 which are farthest from the short sides thereof, while the structure other than the above is basically the same. That is, each of the pair of resin electrode layers 6 is formed so as to cover the entire surface of the lower surface electrode 5 having a rectangular shape, except the one side thereof which is close to the central portion, and the pair of lower surface electrodes 5 is formed on the mounting surface of the insulating substrate 1 with the exposed portions 5a thereof facing each other.

[0061] In the chip resistor 20 having the structure described above, the positions and shapes of the exposed portions 5a of the lower surface electrodes 5 which are exposed from the resin electrode layers 6 are different from those of the first embodiment, however, the same advantageous effects as those of the first embodiment can be obtained.

[0062] FIG. 9 is a rear view of a chip resistor 30 according to a third embodiment, in which the end face electrodes 7 and external electrodes 8 are not illustrated for convenience.

[0063] In the chip resistor 30 according to the third embodiment, each of the pair of lower surface electrodes 5 is exposed from the three sides of the resin electrode layer 6, except the one side closer to the short side of the insulating substrate 1, and each of the exposed portions 5a of the lower surface electrodes 5 is formed into a channel shape (C-shape) so as to surround the outer periphery of the resin electrode layer 6. In this structure, as compared with the cases of the first embodiment and second embodiment, the exposed portions 5a of the lower surface electrodes 5 exposed from the resin electrode layers 6 increase, which results in great improvement in heat dissipation and allows the plating layers to be formed stably.

[0064] FIG. 10 is a rear view of a chip resistor 40 according to a fourth embodiment, in which the end face electrodes 7 and external electrodes 8 are not illustrated for convenience.

[0065] In the chip resistor 40 according to the fourth embodiment, each of the resin electrode layers 6 is provided with a cutout portion 6a that opens toward the end face side of the insulating substrate 1, and each of the exposed portions 5a of the lower surface electrodes 5 is formed on the outer peripheral side of the resin electrode layer 6 and in the cutout portion 6a, respectively. In this structure, as compared with the case of the third embodiment, the exposed portions 5a of the lower surface electrodes 5 exposed from the resin electrode layers 6 increase, which allows the plating layers to be formed stably. Furthermore, providing the cutout portions 6a reduces the areas of the resin electrode layers 6 which are in contact with the primary division groove, which improves the breaking in primary-dividing the large-sized substrate 1A into the strip-shaped substrates 1B along the primary division grooves.

[0066] FIG. 11 is a rear view of a chip resistor 50 according to a fifth embodiment, in which the end face electrodes 7 and external electrodes 8 are not illustrated for convenience.

[0067] In the chip resistor 50 according to the fifth embodiment, each of the resin electrode layers 6 is formed at an inner position away from the end face of the insulating substrate 1, and each of the exposed portions 5a of the lower surface electrode 5 is formed into a frame shape so as to surround the entire periphery of the resin electrode layer 6. This structure allows the plating layers to be formed stably and also can improve the breaking in primary-division. Furthermore, applying metal particles such as Ni—Cr toward the divided faces of the strip-shaped substrate 1B by sputtering to form the end face electrodes 7 causes the sputtered particles to be formed on the exposed portions 5a of the lower surface electrodes 5 extending along the divided faces, and this enables the conductivity of the lower surface electrodes 5 and end face electrodes 7 to be stabilized.

[0068] The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the concept of the present invention. The present invention covers all of the technical matters included in the technical ideas described in the claims. The embodiments described above are suitable examples, and those skilled in the art can realize various alternative examples, modifications, variations, and the like based on the contents disclosed herein, and these are included in the technical scope described in the claims.

[0069] For example, each of the exposed portions 5a of the lower surface electrodes 5 may be formed only at a position in contact with one long side of the insulating substrate 1, or each of the resin electrode layers 6 may be provided with a cutout portion which opens toward the side opposite to the end face of the insulating substrate 1 so that the pair of lower surface electrodes 5 is formed to have the shape reversed left and right with respect to the one illustrated in FIG. 10.

TABLE-US-00001 REFERENCE SIGNS LIST 1 insulating substrate 1A large-sized substrate 1B strip-shaped substrate 1C single chip 2 upper surface electrode 3 resistor 4 protective layer 4a undercoat layer 4b overcoat layer 5 lower surface electrode 5a exposed portion 6 resin electrode layer 6a cutout portion 7 end face electrode 8 external electrode 8a barrier layer 8b external connection layer 9 mask 100 circuit board 101 land 102 solder 10, 20, 30, 40, 50 chip resistor