A VOLTAGE REFERENCE CIRCUIT AND A POWER MANAGEMENT UNIT

Abstract

A voltage reference circuit comprises: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a reference voltage is output at an output node between the first transistor and the second transistor; and a regulating transistor, wherein the regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a bulk terminal of the regulating transistor is connected to the output node for compensating changes in the reference voltage at the output node to maintain a stable reference voltage level.

Claims

1. A voltage reference circuit comprising: a first transistor comprising a gate terminal, a source terminal, a drain terminal and a bulk terminal; a second transistor comprising a gate terminal, a source terminal, a drain terminal and a bulk terminal, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a reference voltage is output at an output node between the first transistor and the second transistor; a regulating transistor comprising a gate terminal, a source terminal, a drain terminal and a bulk terminal, wherein the regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein the bulk terminal of the regulating transistor is connected to the output node for compensating changes in the reference voltage at the output node to maintain a stable reference voltage level.

2. The voltage reference circuit according to claim 1, wherein the first transistor, the second transistor and the regulating transistor are n-type metal-oxide-semiconductor, nMOS, transistors, and wherein a drain terminal of the first transistor is connected to a source terminal of the second transistor and a drain terminal of the second transistor is connected to a source terminal of the regulating transistor, and wherein the output node is connected to the drain terminal of the first transistor and the source terminal of the second transistor.

3. The voltage reference circuit according to claim 1, wherein the gate terminal of the regulating transistor is connected to the source terminal of the regulating transistor.

4. The voltage reference circuit according to claim 1, wherein the gate terminal of the second transistor is connected to the source terminal of the second transistor.

5. The voltage reference circuit according to claim 1, wherein the output node is connected to the gate terminal of the second transistor.

6. The voltage reference circuit according to claim 1, wherein the gate terminal of the first transistor is connected to ground.

7. The voltage reference circuit according to claim 1, wherein the bulk terminal of the first transistor is connected to ground.

8. The voltage reference circuit according to claim 1, wherein the first transistor, the second transistor and the regulating transistor are input/output transistors.

9. The voltage reference circuit according to claim 1, wherein an aspect ratio of the regulating transistor equals an aspect ratio of the second transistor.

10. A power management unit comprising the voltage reference circuit according to claim 1, the power management unit being configured to produce a direct current, DC, voltage based on the reference voltage.

11. A neural sensing apparatus comprising the power management unit according to claim 10.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The above, as well as additional objects, features, and advantages of the present inventive concept, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

[0055] FIG. 1 is a schematic view of a voltage reference circuit according to prior art.

[0056] FIG. 2 is a schematic view of a voltage reference circuit according to a first embodiment.

[0057] FIG. 3 is a schematic view of a voltage reference circuit according to a second embodiment.

[0058] FIG. 4 is a graph illustrating a reference voltage output by the voltage reference circuits of FIG. 2 and FIG. 3, respectively, in dependence of variation of supply voltage.

[0059] FIG. 5 is an enlargement of a portion of the graph in FIG. 4, illustrating a reference voltage output by the voltage reference circuit of FIG. 2 in dependence of variation of supply voltage.

[0060] FIG. 6 is an enlargement of a portion of the graph in FIG. 4, illustrating a reference voltage output by the voltage reference circuit of FIG. 3 in dependence of variation of supply voltage.

[0061] FIG. 7 is a graph illustrating a reference voltage output by the voltage reference circuits of FIG. 2 and FIG. 3, respectively, in dependence of variation of temperature.

[0062] FIG. 8 is a graph illustrating a current consumed by the voltage reference circuits of FIG. 2 and FIG. 3, respectively, in dependence of variation in temperature.

[0063] FIG. 9 is a schematic view of a power management unit according to an embodiment.

[0064] FIG. 10 is a schematic view of a neural sensing apparatus according to an embodiment.

DETAILED DESCRIPTION

[0065] Referring now to FIG. 2, a voltage reference circuit 100 according to a first embodiment will be described. The voltage reference circuit 100 comprises a first transistor 110, a second transistor 120 and a regulating transistor 130.

[0066] Each of the first transistor 110, the second transistor 120 and the regulating transistor 130 may be a n-type metal-oxide-semiconductor (nMOS) transistor and the description below is based on the transistors being nMOS transistors. However, it should be realized that the first transistor 110 may instead be a p-type metal-oxide-semiconductor (pMOS) transistor. In such case, source and drain terminals of the transistor should switch places with each other.

[0067] Each of the first transistor 110, the second transistor 120 and the regulating transistor 130 may comprise four terminals, a source terminal 112, 122, 132, a drain terminal 114, 124, 134, a gate terminal 116, 126, 136, and a bulk terminal 118, 128, 138. Voltage levels on the gate terminal and the bulk terminal control drain current of the transistors 110, 120, 130.

[0068] The first transistor 110 and the second transistor 120 are arranged in a stacked connection with the drain terminal 114 of the first transistor 110 connected to the source terminal 122 of the second transistor 120. The source terminal 112 of the first transistor 110 may further be connected to ground and the drain terminal 124 of the second transistor 120 may be connected to a supply voltage (via the regulating transistor 130).

[0069] The second transistor 120 and the regulating transistor 130 are also arranged in a stacked connection with the drain terminal 124 of the second transistor 120 connected to the source terminal 132 of the regulating transistor 130. The source terminal 122 of the second transistor 120 may further be connected to ground (via the first transistor 110) and the drain terminal 134 of the regulating transistor 130 may be connected to the supply voltage.

[0070] The first transistor 110 and the second transistor 120 being in a stacked connection and the second transistor 120 and the regulating transistor 130 also being in a stacked connection implies that a current may flow between the supply voltage and ground through all transistors 110, 120, 130.

[0071] The first transistor 110, the second transistor 120 and the regulating transistor 130 may be implemented such that a gate leakage current of each transistor is negligible compared with a drain current. This implies that a current drawn from the supply voltage is flowing through all transistors 110, 120, 130 equally, the current corresponding to the drain currents of the transistors 110, 120, 130.

[0072] According to an embodiment, the first transistor 110, the second transistor 120 and the regulating transistor 130 may be implemented with thick gate oxide layers in order to ensure that gate leakage current is very low. Such transistors may be referred to as input/output transistors, as transistors used for communication with external devices often are implemented with a thick gate oxide layer.

[0073] Although input/output transistors may typically have a high threshold voltage, the transistors 110, 120, 130 may have relatively low threshold voltages. The second transistor 120 and the regulating transistor 130 may have lower threshold voltages than the first transistor 110.

[0074] The voltage reference circuit 100 is configured to output a reference voltage V.sub.ref at an output node 140 between the first transistor 110 and the second transistor 120. Since the first transistor 110 is arranged in a stacked connection with the second transistor 120, the drain terminal 114 of the first transistor 110 and the source terminal 122 of the second transistor 120 may be connected to the output node 140.

[0075] The output node 140 is further connected to the bulk terminal 138 of the regulating transistor 130 for feedback of the reference voltage to the regulating transistor 130. The regulating transistor 130 is configured to provide a compensation for changes in the reference voltage such that the voltage reference circuit 100 maintains a stable reference voltage level.

[0076] The second transistor 120 may be configured to generate current in the voltage reference circuit 100. The gate terminal 126 and the source terminal 122 of the second transistor 120 are connected to each other, which also implies that the gate terminal 126 is connected to the output node 140. Since the gate terminal 126 and the source terminal 122 are connected, the second transistor 120 has a zero gate-to-source voltage V.sub.GS2. The bulk terminal 128 of the second transistor 120 may be connected to ground.

[0077] The second transistor 120 may be configured to operate in saturation at a subthreshold region of the second transistor 120. If a drain-to-source voltage V.sub.DS2 of the second transistor 120 is larger than 4*V.sub.T (where V.sub.T is thermal voltage), drain current of the second transistor 120 is controlled only by the bulk-to-source voltage V.sub.BS2 of the second transistor 120. Since the bulk terminal 128 of the second transistor 120 is connected to ground, the bulk-to-source voltage V.sub.BS2 of the second transistor 120 is negative. Further, the source terminal 122 of the second transistor 120 is connected to the output node 140 providing the reference voltage V.sub.ref, such that V.sub.BS2=−V.sub.ref.

[0078] The zero gate-to-source voltage V.sub.GS2 and the negative bulk-to-source voltage V.sub.BS2 implies that an extremely low drain current I.sub.D2 may be generated by the second transistor 120. The generated current is supplied to the first transistor 110 and the regulating transistor 130.

[0079] Since the gate-to-source voltage V.sub.GS2 of the second transistor 120 is always zero and the bulk-to-source voltage V.sub.BS2 is constant (as the output reference voltage V.sub.ref is constant in the voltage reference circuit 100 and V.sub.BS2=−V.sub.ref), the drain current I.sub.D2 will be constant if drain-to-source voltage V.sub.DS2 of the second transistor 120 is constant.

[0080] As will be shown below, the regulating transistor 130 ensures that the drain-to-source voltage V.sub.DS2 of the second transistor 120 is maintained constant.

[0081] As discussed above, the drain current of the regulating transistor 130 equals the drain current of the second transistor 120. The gate terminal 136 of the regulating transistor 130 may be connected to the source terminal 132 of the regulating transistor 130. This implies that the gate-to-source voltage V.sub.GS3 of the regulating transistor 130 is zero. Hence, the drain current through the regulating transistor 130 is controlled by the bulk-to-source voltage V.sub.BS3.

[0082] An aspect ratio of the regulating transistor 130 may equal an aspect ratio of the second transistor 120. This implies that, with the regulating transistor 130 and the second transistor 120 conducting the same current, the bulk-to-source voltage V.sub.BS3 of the regulating transistor 130 equals the bulk-to-source voltage V.sub.BS2 of the second transistor 120, i.e., V.sub.BS3=V.sub.BS2=−V.sub.ref. Hence, using the same aspect ratio for the regulating transistor 130 and the second transistor 120 provides an accurate control of the reference voltage.

[0083] The bulk terminal 138 of the regulating transistor 130 is connected to the output node 140 and, hence, also connected to the source terminal 122 of the second transistor 120. The source terminal 132 of the regulating transistor 130 is connected to the drain terminal 124 of the second transistor 120. This implies that the drain-to-source voltage V.sub.DS2 of the second transistor 120 is regulated by the condition V.sub.DS2=−V.sub.BS3=V.sub.ref.

[0084] Thanks to the regulating transistor 130, a stable reference voltage level may be maintained. If a parameter, such as supply voltage or temperature, fluctuates so that the reference voltage level increases, an incremental change will be sensed by the change in the bulk-to-source voltage V.sub.BS3 of the regulating transistor 130. The regulating transistor 130 will thus reduce the drain-to-source voltage V.sub.DS2 of the second transistor 120 such that the drain current of the second transistor 120 will degenerate and bring the reference voltage back to original value. If the reference voltage level instead decreases, the voltage reference circuit 100 operates vice versa to maintain the stable reference voltage level.

[0085] According to the embodiment in FIG. 2, the bulk terminal 118 and the drain terminal 114 of the first transistor 110 are connected to each other and connected to the output node 140. Further, the gate terminal 116 and the source terminal 112 of the first transistor 110 are connected to each other and further connected to ground. This implies that the bulk-to-source voltage V.sub.BS1 of the first transistor corresponds to the reference voltage V.sub.ref (bulk connected to reference voltage and source connected to ground).

[0086] Referring now to FIG. 3, a voltage reference circuit 200 according to a second embodiment will be described.

[0087] The voltage reference circuit 200 comprises a first transistor 210, a second transistor 220 and a regulating transistor 230 corresponding to the voltage reference circuit 100 described above with reference to FIG. 2. The drain terminal 224, the source terminal 222, the gate terminal 226 and the bulk terminal 228 of the second transistor 220 are connected in the same manner as described above for the first embodiment. Similarly, the drain terminal 234, the source terminal 232, the gate terminal 236 and the bulk terminal 238 of the regulating transistor 230 are connected in the same manner as described above for the first embodiment. Thus, regulation of the reference voltage may be provided in a same manner as described above.

[0088] According to the embodiment in FIG. 3, the gate terminal 216 and the drain terminal 214 of the first transistor 210 are connected to each other and connected to the output node 240. Further, the bulk terminal 218 and the source terminal 212 of the first transistor 210 are connected to each other and further connected to ground. This implies that the gate-to-source voltage V.sub.GS1 of the first transistor corresponds to the reference voltage V.sub.ref (gate connected to reference voltage and source connected to ground).

[0089] The connection of the first transistor 110, 210 to the output node 140, 240 and ground affects the reference voltage level at the output node 140, 240. This implies that, if the same transistors are used, a higher reference voltage level may be provided in the configuration of FIG. 2 compared to the configuration of FIG. 3.

[0090] The voltage reference circuits 100, 200 have been simulated to analyze the insensitivity of the voltage reference circuits 100, 200 to parameter variations.

[0091] In the simulations, corresponding transistors in the circuits 100, 200 have identical properties. Thus, the first transistor 110 of the voltage reference circuit 100 is identical to the first transistor 210 of the voltage reference circuit 200, the second transistor 120 and the regulating transistor 130 of the voltage reference circuit 100 are identical to the second transistor 220 and the regulating transistor 230 of the voltage reference circuit 200. The simulations have been based on the following parameters of the transistors:

[0092] The circuits are simulated in 22 nm FDSOI technology.

[0093] The first transistors 110, 210 are transistors with low threshold voltage (V.sub.th˜0.5V) and having a channel width of 0.2 μm and a channel length of 0.5 μm.

[0094] The second transistors 120, 220 and the regulating transistors 130, 230 are transistors with ultra-low threshold voltage (V.sub.th˜0.4V) and having a channel width of 0.5 μm and a channel length of 0.2 μm.

[0095] Referring now to FIG. 4, an operating range of the supply voltage for the voltage reference circuits 100, 200 is illustrated. For the voltage reference circuit 200, the reference voltage assumes a value of approximately 162 mV when the supply voltage reaches approximately 0.35 V. Then, the reference voltage remains constant until the supply voltage reaches approximately 2.5 V, defining an operating range of the supply voltage between 0.35-2.5 V for which the voltage reference circuit 200 provides a constant reference voltage. Similarly, the voltage reference circuit 100 provides a constant reference voltage of approximately 560 mV in an operating range of the supply voltage of 0.8-2.5 V.

[0096] Thus, the voltage reference circuits 100, 200 provide a large operating range of the supply voltage. In addition, the voltage reference circuits 100, 200 provide a good line regulation (LR) (change in output reference voltage in dependence of change in supply voltage).

[0097] Referring now to FIG. 5, an enlargement of the graph of FIG. 4 for the voltage reference circuit 100 is shown. Here, the output reference voltage as a function of supply voltage is shown for the voltage reference circuit 100 (solid line) and also for a voltage reference circuit where the regulating transistor 130 has been removed (dashed line). The LR for the circuit without the regulating transistor 130 is 991 μV/V in the range of 0.5 V-1.5 V of the supply voltage. The LR for the voltage reference circuit 100 including the regulating transistor 130 is 161 μV/V, indicating impact of the regulating transistor 130 on performance of the voltage reference circuit 100.

[0098] Referring now to FIG. 6, an enlargement of the graph of FIG. 4 for the voltage reference circuit 200 is shown. Again, the output reference voltage as a function of supply voltage is shown for the voltage reference circuit 200 (solid line) and also for a voltage reference circuit where the regulating transistor 230 has been removed (dashed line). The LR for the circuit without the regulating transistor 230 is 774 μV/V in the range of 1.2 V-1.7 V of the supply voltage. The LR for the voltage reference circuit 200 including the regulating transistor 230 is 100 μV/V, indicating impact of the regulating transistor 230 on performance of the voltage reference circuit 200.

[0099] Referring now to FIG. 7, temperature characteristics of the reference voltage output by the voltage reference circuits 100, 200 (solid lines) is illustrated as well as temperature characteristics of corresponding circuits without the regulating transistor 130, 230. As is shown in FIG. 7, the reference voltage output by the voltage reference circuits 100, 200 is stable between −10° C. to 150° C. The regulating transistor 130, 230 negligibly affects the temperature insensitivity of the voltage reference circuits 100, 200 in this range. Within this range, a temperature coefficient (TC) of the reference voltages is 198 ppm for the voltage reference circuit 100 and 24.3 ppm for the voltage reference circuit 200. The regulating transistor 130, 230 starts to affect performance of the voltage reference circuits 100, 200 at temperatures below −10° C.

[0100] Referring now to FIG. 8, current consumption of the voltage reference circuits 100, 200 is illustrated as a function of temperature, while keeping a supply voltage constant at 1 V. As can be seen, currents consumed by the voltage reference circuits 100, 200 increases almost exponentially over the temperature. The voltage reference circuit 200 consumes approximately ten times higher current than the voltage reference circuit 100 for the entire temperature range. At 30° C., the voltage reference circuit 100 consumes 0.0126 pA and the voltage reference circuit 200 consumes 0.127 pA. Hence, the voltage reference circuits 100, 200 have ultra-low power consumption.

[0101] It should be realized that the voltage reference circuits 100, 200 may be used in any type of circuit or device where a stable voltage reference is desired. For instance, as shown in FIG. 9, a power management unit 300 may comprise any of the voltage reference circuits 100, 200 described above.

[0102] The power management unit 300 may be configured to control power functions of modules in electronic devices. Thus, the power management unit 300 may control whether modules are active or in sleep mode and may control power to modules.

[0103] The power management unit 300 may be configured to provide a DC voltage to modules of an electronic device, such as to integrated circuits. Thus, the power management unit 300 may need to ensure that a stable voltage level of the DC voltage is provided. In this regard, the power management unit 300 may be configured to produce the DC voltage based on the reference voltage output by the voltage reference circuit 100, 200.

[0104] The power management unit 300 may comprise an output interface 302 for communicating with modules of the electronic device. The power management unit 300 may thus send signals for controlling functionality of the modules and may also supply a DC voltage to the modules over the output interface 302.

[0105] Since the power management unit 300 controls whether modules are active or in a sleep mode, the power management unit 300 may be maintained active when turning off the electronic device in which the power management unit 300 is arranged. Thus, power consumption of the power management unit 300 is important, in particular, if the power management unit 300 is arranged in a battery-powered device which may be awake only for a fraction of time, which may be the case for IoT-devices.

[0106] The voltage reference circuit 100, 200 consumes very small power, as discussed above. Hence, the voltage reference circuits 100, 200 are suited for being used in the power management unit 300.

[0107] Referring now to FIG. 10, a neural sensing apparatus 400 according to an embodiment will be described.

[0108] The neural sensing apparatus 400 may be in form of a neural probe which may be at least partly inserted into a brain. The neural sensing apparatus 400 may comprise electrodes 402 for neural sensing and readout circuitry 404 for reading out signals from the electrodes 402.

[0109] The neural sensing apparatus 400 may comprise the power management unit 300 for power management of the neural sensing apparatus 400. The power management unit 300 may be configured to control whether modules, such as the readout circuitry 404, of the neural sensing apparatus 400 are active or in a sleep mode.

[0110] The power management unit 300 may further comprise any of the voltage reference circuits 100, 200. The power consumption of the power management unit 300 of the neural sensing apparatus 400 may be very low thanks to the power management unit 300 which utilizes a voltage reference circuit 100, 200 which consumes very small power, as discussed above.

[0111] In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.