ELECTRONIC DEVICE WITH REDUCED SWITCHING OSCILLATIONS

Abstract

The present disclosure is directed to an electronic device including a semiconductor body having a first electrical conductivity and provided with a front side; an active area of the semiconductor body, accommodating the source and gate regions of the electronic device and configured to accommodate, in use, a conductive channel of the electronic device; and an edge region of the electronic device, surrounding the active area. The edge region accommodates at least in part: i) an edge termination region, having a second electrical conductivity opposite to the first electrical conductivity, extending into the semiconductor body at the front side; and ii) a gate connection terminal of conductive material, electrically coupled to the gate region, extending on the front side partially superimposed on the edge termination region and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region.

Claims

1. An electronic device comprising: a semiconductor body having a first electrical conductivity and a front side; an active area of the semiconductor body, the active area including source and gate regions and, in use, a conductive channel; an edge region of the electronic device, the edge region surrounding the active area, the edge region including, at least in part: an edge termination region having a second electrical conductivity opposite to the first electrical conductivity, the edge termination region extending into the semiconductor body at the front side; and a gate connection terminal including conductive material and electrically coupled to the gate region, the gate connection terminal extending on the front side and partially superimposed on the edge termination region, the gate connection terminal configured to establish, in use, a capacitive coupling with a portion of the semiconductor body adjacent and external to the edge termination region.

2. The electronic device according to claim 1, wherein the edge termination region is in electrical contact with the source region.

3. The electronic device according to claim 1, wherein the active area includes a body region having the second electrical conductivity, the source region extending inside the body region, and wherein the edge termination region is in electrical contact with the body region and has a doping dose greater than a doping dose of the body region.

4. The electronic device according to claim 1, further comprising: a dielectric layer interposed between the front side and the gate connection terminal.

5. The electronic device according to claim 4, wherein the gate connection terminal is a first plate of a capacitor, the semiconductor body is a second plate of the capacitor, and the dielectric layer is interposed between the first and the second plates of the capacitor.

6. The electronic device according to claim 4, wherein the dielectric layer includes Silicon Oxide, Silicon Nitride, or Silicon Oxynitride.

7. The electronic device according to claim 4, wherein the dielectric layer includes a high-k material having a value of a parameter k higher than 7.

8. The electronic device according to claim 1, further comprising: a first protection ring having the second electrical conductivity and a doping value lower than a doping value of the edge termination region, the first protection ring extending into the semiconductor body at an end portion of the edge termination region.

9. The electronic device according to claim 8, further comprising: a second protection ring having the second electrical conductivity and a doping value lower than a doping value of the edge termination region, the second protection ring extending into the semiconductor body at an end portion of the gate connection terminal.

10. The electronic device according to claim 9, further comprising: one or more floating regions having the second electrical conductivity, the one or more floating regions extending into the semiconductor body between the first protection ring and the second protection ring.

11. The electronic device according to claim 1, wherein the edge region includes a current spread layer (CSL) extending into a portion of the semiconductor body at the front side, and wherein the CSL has the first electrical conductivity and doping value higher than a doping value of the portion of the semiconductor body in which the CSL extends into.

12. The electronic device according to claim 1, further comprising: a drain region extending at a rear side, opposite to the front side, of the semiconductor body.

13. The electronic device according to claim 12, wherein the portion of the semiconductor body adjacent and external to the edge termination region is in electrical contact with the drain region.

14. The electronic device according to claim 12, wherein the gate region defines, with portions of the semiconductor body extending below the gate region and having the first electrical conductivity, a first contribution of capacitance between the gate region and the drain region of the electronic device.

15. The electronic device according to claim 14, wherein the capacitive coupling defines a second contribution of the capacitance between the gate region and the drain region which is added to the first contribution.

16. The electronic device according to claim 15, wherein the second contribution is designed with a value such that it triggers a parasitic turn-ON (PTO) phenomenon, during a turn-OFF of the electronic device.

17. The electronic device according to claim 4, wherein an overlap of the edge termination region with the portion of the semiconductor body adjacent and external to the edge termination region, has a value L.sub.shield along a reference axis parallel to the front side, which meets the relationship: $\begin{array}{c}\frac{{\left(1\text{.15}.Math.{10}^5/m\right)}^{*}{{\mathrm{Th}}_{\mathrm{diel}}}_{{*}^{}}{w}_{AA}}{{\epsilon }_{\mathrm{diel}}}\le L_{\mathrm{shield}}\le \frac{{\left\{2.3.Math.{10}^5/m\right\}}^{*}{\mathrm{Th}}_{\mathrm{diel}}^{*}{w}_{\mathrm{AA}}}{{\epsilon }_{\mathrm{diel}}}\\ \frac{{\left(1.Math.{10}^{-6*}F/m^2\right)}^{*}T{h}_{{\mathrm{diel}}^{*}}{w}_{\mathrm{AA}}}{{\epsilon }_{\mathrm{diel}}{\epsilon }_0}\le L_{\mathrm{shield}}\le \frac{{\left(2.Math.{10}^{-6*}F/m^2\right)}^{*}T{h}_{{\mathrm{diel}}^{\star }}{w}_{\mathrm{AA}}}{{\epsilon }_{\mathrm{diel}}{\epsilon }_0}\end{array}$ or where: W.sub.AA is a maximum extension, along the reference axis, of the active area, the active area having a square shape; ε.sub.diel is a dielectric constant of the material of the dielectric layer; and ε.sub.0 is a dielectric constant of vacuum.

18. The electronic device according to claim 1, wherein the edge region includes a capacitive decoupling layer extending into the semiconductor body at the front side laterally to the edge termination region and interposed between the gate connection terminal and the portion of the semiconductor body adjacent and external to the edge termination region, and wherein the capacitive decoupling layer is configured to deplete majority carriers having the second electrical conductivity when the electronic device is in use, and allow establishment of the capacitive coupling.

19. The electronic device according to claim 18, wherein the capacitive decoupling layer has a doping dose of an order of 10.sup.16 ions/cm.sup.3, and extends into the semiconductor body with a thickness between 0.2 and 0.4 μm.

20. The electronic device according to claim 1, wherein the electronic device is a vertical conduction MOSFET.

21. The electronic device according to claim 1, wherein the semiconductor body includes Silicon Carbide.

22. A device comprising: a semiconductor body having a first electrical conductivity type; an active region in the semiconductor body, the active region including a source region, a gate region, a body region, and a channel region; an edge region in the semiconductor body and surrounding the active region, the channel region does not extend into the edge region and is within the active region; an edge termination region having a second electrical conductivity type, the edge termination region extending in the active region and the edge region, the edge termination region being in electrical contact with the source region and the body region; a conductive layer on the edge termination region; a dielectric layer on the conductive layer; and a gate connection terminal including a first portion on the dielectric layer and a second portion extending through dielectric layer, the gate connection terminal being in electrical contact with the conducive layer and the gate region.

23. The device according to claim 22, further comprising: an implanted region having the second electrical conductivity type, the implanted region extending in the edge region and underlying the gate connection terminal.

24. A device, comprising: a semiconductor body having a first electrical conductivity type, the semiconductor body having an active region and an edge region that encircles the active region; a source region in the active region; a body region in the active region; a gate region in the active region; an edge termination region in the active region and the edge region, the edge termination region having a second electrical conductivity type, the edge termination region electrically coupled to the source region and the body region; a conductive layer on the edge termination region; a source terminal electrically coupled to the source region, a portion of the source terminal positioned between the gate region and the conductive layer; and a gate terminal electrically coupled to the conducive layer and the gate region.

25. The device according to claim 24, wherein the edge termination region encircles the active region.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0010] For a better understanding of the present disclosure, embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:

[0011] FIG. 1 illustrates a top view of a semiconductor die, accommodating an electronic device, in particular a MOSFET;

[0012] FIGS. 2-6 illustrate, in cross-sectional view, an electronic device, in particular a MOSFET, according to respective embodiments of the present disclosure;

[0013] FIG. 7 illustrates, in top view, the semiconductor die of FIG. 1 wherein a gate connection terminal is present in the edge region, according to an aspect of the present disclosure; and FIG. 8 illustrates, in cross-sectional view, an electronic device, in particular a MOSFET, according to a further embodiment of the present disclosure.

DETAILED DESCRIPTION

[0014] The present disclosure is illustrated with reference to the accompanying drawings which show a wafer, or a part of it, in a triaxial system of X, Y, Z axes orthogonal to each other.

[0015] With reference to FIG. 1, a die or chip 1 is obtained after a dicing step of a semiconductor wafer. The die 1 is schematically illustrated in a top view, on the XY plane (this is the view at a front side 1a of the die 1). The die 1 comprises an external edge 2, which physically delimits the die 1. The die 1 accommodates at least one electronic device (not illustrated in FIG. 1), such as for example a MOSFET. Hereinafter, both the terms “electronic device” and “MOSFET” will be used, without thereby losing generality.

[0016] The die 1 includes at least two functional regions: an active area or region 4, typically extending into a central portion of the die 1, and an edge region 6, or peripheral or border region, which completely surrounds the active area 4. Stated differently, the edge region 6 encircles the active area 4. The edge region extends, in other words, between the active area 4 and the external edge 2.

[0017] The active area 4 is the portion of the die 1 that accommodates elements of the electronic device that participate in the on-state conduction or, in general, the region of the die 1 wherein the conductive channel is formed (in use). The active area 4 accommodates, for example, source regions, drain regions, and channel regions including the conductive channel of the MOSFET. The drain region extends, for example in case of a vertical conduction device, at a rear side 1b (not visible in FIG. 1 as it is parallel and opposite to the front side 1a) of the die 1. The conductive channel extends into a region of the active area 4 comprised between the front side 1a and the rear side 1b, that is between the source and the drain, in a mainly vertical direction (along Z) towards the rear side 1b.

[0018] The edge region 6, on the other hand, is a region which does not have the channel region, more specifically, in use, the conductive channel. Stated differently, the conductive channel is contained in the active area 4, and does not extend into the edge region 6. The edge region 6 may have functional elements for reducing or preventing crowding of the electric field outside the active area.

[0019] FIG. 2 is a cross-sectional view (on the XZ plane) of a portion of the die 1, for example considered along scribe line II-II of FIG. 1. FIG. 2 illustrates portions of an electronic device, in particular a vertical conduction MOSFET, formed in the die 1.

[0020] With reference to FIG. 2, the die 1 includes: a semiconductor body, for example of Silicon Carbide (SiC) or Silicon (Si), having a first electrical conductivity (e.g., of N-type). The semiconductor body comprises a substrate 8 (N+ doped) and a drift layer 10 (N− doped) on the substrate 8. A drain terminal 9, for example of metal material, extends on the rear side 1b of the semiconductor body.

[0021] Body regions 11, having a second electrical conductivity (P) of type opposite to the first conductivity, and source regions 12, having the first conductivity (and N+ doping) in the body regions 11 are present at the front side 1a of the drift layer 10. The body regions 11 and the source regions 12 are regions implanted in the drift layer 10, in a per se known manner.

[0022] Gate regions 14 extend above the front side 1a, and include a gate dielectric 14a and a gate conductive region 14b. The gate dielectric is interposed between the gate conductive region 14b and the semiconductor body (in particular the drift layer 10).

[0023] FIG. 2 illustrates, for simplicity of representation, a single body region 11 accommodating a respective source region 12, whereon a respective gate region 14 extends. In particular, these illustrated body 11, source 12 and gate 14 regions extend in proximity of the end of the active area 4, after which the edge region 6 begins, as previously described.

[0024] The electronic device further comprises a source (e.g., metal) terminal 16, which extends in contact with the front side 1a at the source region 12, and is isolated from the gate region 14 by an insulating layer 18. As shown in FIG. 2, the source terminal 16 is on the source region 12 and an edge termination region 20.

[0025] The die 1 further accommodates, inside the semiconductor body (in particular in the drift layer 10), an edge termination region 20, implanted at the front side 1a and facing the front side 1a. The edge termination region 20 has the second electrical conductivity and a doping (P+) greater than that of the body region 11. The edge termination region 20 extends from the active area 4 in electrical contact with the source 12 and body 11 regions and proceeds along the X axis inside the edge region 6. The edge termination region 20 has the function of preventing or inhibiting the generation, in the dielectric layer 22a present under the region 22b, of an electric field having a value such that it damages the dielectric layer 22a.

[0026] A dielectric layer 22a (similar to the gate dielectric 14a) and a conductive layer 22b on the dielectric layer 22a (similar to the gate conductive region 14b) extend above the edge termination region 20 (on the front side 1a). However, the layers 22a and 22b do not have, in use, the function of gate terminal (i.e., they do not contribute to the formation of a conductive channel).

[0027] The electronic device further comprises a gate connection terminal 24, of conductive material, for example metal or N-type doped polysilicon, including a first portion 24a which extends in electrical contact with the conductive layer 22b and a second portion 24b which extends above and at a distance from the conductive layer 22b, in the edge region 6. The first and the second portions 24a, 24b are a single piece (monolithic) in structural and electrical continuity with each other. The second portion 24b forms an edge field plate, also said gate shield of the electronic device.

[0028] Furthermore, the gate connection terminal 24 is (in a manner not illustrated in Figure) in electrical contact with the gate region 14. The gate connection terminal 24 also has a region for electrical contact (e.g., by wire bonding or other technique) to provide the electronic device with gate bias during use.

[0029] The dashed line in FIG. 2, which discriminates between the active area 4 and the edge region 6, is to be understood as qualitative. For the purposes of the description of the present disclosure, the second portion 24b of the gate connection terminal 24 is completely accommodated in the edge region 6 and therefore is located in the right-hand portion with respect to the dashed demarcation line between the active area 4 and the edge region 6.

[0030] A passivation layer 28 extends on the gate connection terminal 24 and on the source terminal 16, to protect and insulate the gate connection terminal 24 and the source terminal 16. Openings 28′ are provided in the passivation layer 28 for being able to electrically contact the gate connection terminal 24 and the source terminal 16 (as said, e.g. by wire bonding, to provide the respective biases during use).

[0031] The second portion 24b of the gate connection terminal 24 extends at a distance from the front side 1a, and in particular is separated from the front side 1a of the semiconductor body (in particular, from the drift layer 10) by a dielectric or insulating layer 30. The dielectric layer 30 also extends between the conductive layer 22b and the gate connection terminal 24; the physical contact between the first portion 24a of the gate connection terminal 24 and the conductive layer 22b occurs by a conductive through-via that extends through the entire thickness (along Z) of the dielectric layer 30.

[0032] The maximum extension along the Z axis (thickness) of the stack formed by the dielectric layer 30 and the underlying dielectric layer 22a is indicated hereinafter as Th.sub.diel and has a value, for example, comprised between 0.8 and 2.4 In other words, Th.sub.diel represents the total thickness of the dielectric layer 22a plus the dielectric layer 30 between the second portion 24b of the gate connection terminal 24 and the front side 1a.

[0033] According to an embodiment of the present disclosure, the dielectric layer 22a and the dielectric layer 30 are of the same material.

[0034] According to a further embodiment of the present disclosure, the dielectric layer 22a extends exclusively below the conductive layer 22b, and is not present below the dielectric layer 30; in this case, the dielectric layer 30 extends between the front side 1a and the second portion 24b of the gate connection terminal 24 and therefore Th.sub.diel represents the maximum thickness of the dielectric layer 30 between the second portion 24b of the gate connection terminal 24 and the front side 1a.

[0035] According to an aspect of the present disclosure, the extension along the X axis of the gate connection terminal 24 (in particular, of the second portion 24b) is greater than the extension, again along X, of the edge termination region 20. In other words, in the sectional view of FIG. 2 or in the top view of FIG. 7, the gate connection terminal 24 is in part superimposed on the edge termination region 20 and in part extends beyond the edge termination region 20, in such a way that it faces the semiconductor body (in particular the drift layer 10) through the dielectric layer 30 and, if present, the insulating layer 22a, in correspondence of an N-type doped portion of the front side 1a of the semiconductor body, that is wherein the edge termination region 20 does not extend (is not present).

[0036] The extension along X (similarly, as may be seen from FIG. 7, also along Y) of the portion of the gate connection terminal 24 which faces the respective N-type doped portion of the front side 1a is indicated hereinafter as L.sub.shield.

[0037] It is noted that the N-type doped portion of the front side 1a where the gate connection terminal 24 faces, is in electrical connection with the drain region 9 of the electronic device. A capacitive coupling is thus provided (schematically illustrated with the symbol of a capacitor 32 in FIG. 2) between the gate connection terminal 24 (first plate of the capacitor 32) and the drain region 9 (second plate of the capacitor 32), wherein the dielectric layer 30 and, if any, the insulating layer 22a form the dielectric interposed between the two plates of the capacitor 32. Since the gate connection terminal 24 (first plate of the capacitor 32) is in electrical connection with the gate terminal 14 of the MOSFET and the second plate of the capacitor 32 coincides, from an electrical point of view, with the drain region 9 of the MOSFET, the capacitive coupling occurs between the gate terminal 14 and the drain terminal 9 of the MOSFET.

[0038] In this manner, the total gate-drain capacitance C.sub.gd of the electronic device (the MOSFET) is given by the sum of two capacitive contributions: a first contribution C.sub.gd′ is given by the capacitance between gate and drain present in active area 4, at the overlap region between gate terminal 14 and N-doped drift layer 10; a second contribution C.sub.gd″ is given by the capacitance value symbolically identified by the capacitor 32.

[0039] The capacitance C.sub.gd is a non-linear function of the voltage and is a relevant parameter as it provides a feedback loop between the output and the input of the circuit. The capacitance C.sub.gd is also known as Miller capacitance as it makes the total dynamic input capacitance greater than the sum of the static capacitances. The turn-OFF delay of the MOSFET device is due to the time to discharge the input capacitance after removing the bias. Since the input capacitance is a function of the capacitance C.sub.gd, the increase in the capacitance C.sub.gd (by the contribution C.sub.gd″ added according to the present disclosure) entails a corresponding adjustment of the turn-OFF delay, and allows to balance the undesired behavior during the inverse recovery step of the body diode of the MOSFET, damping the recovery current oscillations. The capacitance C.sub.gd thus set or designed is such that it varies the response of the electronic device accordingly with respect to the switching oscillations during the turn-OFF step. In particular, an increase in the feedback capacitance corresponds to a damping of the switching oscillations during the turn-OFF step.

[0040] By suitably defining, during the design step, the extension (area) of capacitive coupling between the gate connection terminal 24 and the drift layer 10, a predefined and/or desired value of capacitance C.sub.gd may be generated. The effect discussed above is observed for any value of capacitance 32 introduced according to the present disclosure; however, the Applicant has verified that the values of the capacitance C.sub.gd″ of tens of picofarads, for example in the range 65-130 pF for values of drain-source voltage (Vds) equal to or higher than 100 V, are a suitable solution. The capacitance C.sub.gd″ is added, as said, to the capacitance C.sub.gd′ still present in active area 4 and typically with a value lower than 25 pF for values of drain-source voltage (Vds) equal to or higher than 100 V.

[0041] Therefore, the following relationship (1) applies:

[00001]$\begin{array}{cc}\frac{{\left(1.15.Math.{10}^5/m\right)}^{*}T{h}_{\mathrm{diel}}^{\star }{w}_{AA}}{{\epsilon }_{\mathrm{diel}}}\le L_{\mathrm{shield}}\le \frac{{\left(2.3.Math.{10}^5/m\right)}^{*}T{h}_{\mathrm{diel}}^{*}{w}_{\mathrm{AA}}}{{\epsilon }_{\mathrm{diel}}}& \left(1\right)\end{array}$

[0042] Similarly, by making the constant ε.sub.0 explicit, the relationship (1) may be expressed as:

[00002]$\begin{array}{cc}\frac{{\left(1.Math.{10}^{-6*}F/m^2\right)}^{*}T{h}_{\mathrm{diel}}^{*}{w}_{AA}}{{\epsilon }_{\mathrm{diel}}{\epsilon }_0}\le L_{\mathrm{shield}}\le \frac{{\left(2.Math.{10}^{6\star }F/m^2\right)}^{\star }T{h}_{\mathrm{diel}}^{*}{w}_{\mathrm{AA}}}{{\epsilon }_{\mathrm{diel}}{\epsilon }_0}& \left(2\right)\end{array}$

[0043] The constant ε.sub.diel is the dielectric constant of the material used for the dielectric layer 30 and, if any, for the dielectric layer 22a (assumed to be of the same material); the constant ε.sub.0 is the dielectric constant of vacuum; W.sub.AA is the length, in XY plane view of FIG. 1 or FIG. 7, of a side along X or Y of the active area 4 (assumed to have a square shape); “F” indicates the unit of measurement “Farad”; and “m” the unit of measurement “meter.”

[0044] Relationships (1) and (2) set forth above for L.sub.shield are also based on the following assumptions: [0045] i) that the die 1 has a substantially square shape (possibly with rounded corners), with a side W.sub.die (e.g., W.sub.die equal to about 2000-8000 μm, for example 4000 μm); [0046] ii) that the active area 4 has a substantially square shape (possibly with rounded edges), with a side W.sub.AA e.g. equal to about ¾ W.sub.die; and [0047] iii) that, in the active area, the value of capacity C.sub.gd′ is lower than or equal to 1.5 pF/mm.sup.2 for Vds≥100V.

[0048] Alternatively to what has been set forth above, the relationships (1) and (2) may be replaced by equivalent relationships (3) and respectively (4) illustrated hereinbelow, wherein the parameter L.sub.shield is replaced by the value of area S.sub.shield (in XY plane view) of the portion of the gate connection terminal 24 which contributes to the capacitance C.sub.gd″:

[00003]$\begin{array}{cc}\frac{\left(4.6.Math.{10}^5/m\right).Math.{\mathrm{Th}}_{\mathrm{diel}}.Math.w_{AA}^2}{{\epsilon }_{\mathrm{diel}}}\le S_{\mathrm{shield}}\le \frac{\left(9.2.Math.{10}^5/m\right).Math.{\mathrm{Th}}_{\mathrm{diel}}.Math.w_{\mathrm{AA}}^2}{{\epsilon }_{\mathrm{diel}}}& \left(3\right)\end{array}$

[0049] Similarly, by making the constant ε.sub.0 explicit, the relationship (3) may be expressed as:

[00004]$\begin{array}{cc}\frac{\left(4.Math.{10}^{-6}.Math.F/m^2\right).Math.{\mathrm{Th}}_{\mathrm{diel}}.Math.w_{AA}^2}{{\epsilon }_{\mathrm{diel}}{\epsilon }_0}\le S_{\mathrm{shield}}\le \frac{\left(8.Math.{10}^{-6}.Math.F/m^2\right).Math.{\mathrm{Th}}_{\mathrm{diel}}.Math.w_{\mathrm{AA}}^2}{{\epsilon }_{\mathrm{diel}}{\epsilon }_0}& \left(4\right)\end{array}$

[0050] Relationships (3) and (4) are approximate, as the area contributions at the edges are not considered, such contributions representing at most a value between 5% and 6% of the total area S.sub.shield, given that L.sub.shield<<W.sub.AA.

[0051] According to an aspect of the present disclosure, the capacitance contribution C.sub.gd″ is chosen in such a way that the total capacitance C.sub.gd (i.e., given by C.sub.gd+C.sub.gd″) is such that it triggers, during the turn-OFF of the MOSFET device, the per se known parasitic turn-ON (PTO) phenomenon. When the PTO phenomenon occurs, the MOSFET turns on unintentionally, causing a temporary (parasitic) current flow in the active area. The presence of this parasitic current mitigates the effect of undesired oscillations during the turn-OFF step, more particularly it reduces the total amplitude of the oscillation of the drain-source voltage by several percentage points (for example, for current pulses of 2 A/ns, there is observed a reduction of the drain bus supply voltage below 15%).

[0052] According to an embodiment, the insulating layer 22a may be omitted in the capacitive coupling region, so that the dielectric interposed between the two plates of the capacitor is formed exclusively by the dielectric layer 30. The dielectric material of the layer 30 may thus be suitably selected as needed, regardless of the material chosen for the insulating layer 22a.

[0053] The dielectric layer 30 (similarly, also the insulating layer 22a) may be one of: Silicon Oxide (SiO.sub.2), Silicon Nitride (SiN, Si.sub.3N.sub.4), Silicon Oxynitride (SiO.sub.xN.sub.y), or a high-k dielectric material, with k>7. Usable high-k materials include, for example, Aluminum Nitride (AlN), Aluminum Oxynitride (ALON, Al.sub.2O.sub.3), Tantalum Oxide (TaO, Ta.sub.2O.sub.5), Hafnium Oxide (HfO.sub.2), Zirconium Oxide (ZrO.sub.2), etc.

[0054] FIG. 3 illustrates a further embodiment of the present disclosure. Elements of FIG. 3 common to FIG. 2 are indicated with the same reference numbers and are not further described.

[0055] The die 1′ of FIG. 3 comprises, in addition to what has already been described with reference to FIG. 2, a further implanted region 40 having the second electrical conductivity (of P-type) and doping lower than the doping of the edge termination region 20. The implanted region 40 extends at an end portion of the edge termination region 20, at a distance from the body region 11. Stated differently, the body region 11 and the implanted region 40 are positioned at opposite ends of the edge termination region 20. The implanted region 40 therefore extends as an extension of the edge termination region 20. The implanted region 40 has the function of distributing or thinning the field lines of the electric potential in such a way that it avoids a thickening of the field lines on the radius of curvature of the edge termination region 20, and thus maximizes the edge breakdown voltage value.

[0056] According to this embodiment, the extension along the X axis of the gate connection terminal 24 (in particular, of the second portion 24b) is greater than the maximum height reached, along the X axis, by the implanted region 40 (which, as said, extends as an extension of the edge termination region 20). In other words, in the sectional view of FIG. 3 (or in a corresponding top view as in FIG. 1), the gate connection terminal 24 is completely superimposed on the edge termination region 20 and also extends beyond the implanted region 40. In this manner the gate connection terminal 24 faces the semiconductor body (in particular the drift layer 10) through the dielectric layer 30 (and the insulating layer 22a if any), without the implanted region 40 being present therebetween. A capacitive coupling similar to that described with reference to FIG. 2 (illustrated with the symbol of the capacitor 32) is thus provided between the gate connection terminal 24 and the N-type semiconductor body.

[0057] FIG. 4 illustrates a further embodiment of the present disclosure. Elements of FIG. 4 common to FIG. 2 and FIG. 3 are indicated with the same reference numbers and are not further described.

[0058] The die 1″ of FIG. 4 comprises, in addition to what has already been described with reference to FIG. 2 and FIG. 3, a current spread layer (CSL) 50, which extends into the semiconductor body (in particular into the drift layer 10) facing the front side 1a. The current spread layer 50 is provided by one or more implants of doping species having the first conductivity and forms an enrichment layer which extends in depth from the front side 1a. Alternatively, the current spread layer 50 is obtained by epitaxial growth. The current spread layer 50 may also be formed by combining an epitaxial growth step and subsequent implant (for example in active area 4).

[0059] In one embodiment, the depth whereto the current spread layer 50 extends is greater than the maximum depth reached by the body region 11, the implanted region 40 and the edge termination region 20. In other words, in this embodiment, all of the body region 11, the implanted region 40 and the edge termination region 20 are completely contained within the current spread layer 50.

[0060] In a further embodiment, the current spread layer 50 extends (at least, or exclusively, in the edge region 6) to a lower depth than the maximum depth reached by the body region 11, the implanted region 40 and the edge termination region 20.

[0061] Regardless of the embodiment, the doping of the current spread layer 50 is greater than the doping of the drift layer 10 accommodating it. The current spread layer 50 has, for example, doping of the order of 10.sup.17 atoms/cm.sup.3.

[0062] The current spread layer 50 extends through the entire extension of the surface 1a, or for a part of it. Regardless of the layout chosen for the current spread layer 50, in the context of the present disclosure it extends at least in part superimposed (in top view) on the gate connection terminal 24. In this manner, the gate connection terminal 24 in part faces the current spread layer 50 through the dielectric layer 30 (and the insulating layer 22a if any) without the implanted region 40 or the edge termination region 20 being present therebetween. A capacitive coupling, similar to that described with reference to FIG. 2 or FIG. 3 (illustrated with the symbol of the capacitor 32) is thus provided between the gate connection terminal 24 and the current spread layer 50 in the semiconductor body.

[0063] The use of the current spread layer 50 is known per se and is widely used in MOSFETs for high frequency applications, with advantages and function that are known and not discussed herein. In the context of the present disclosure, the presence of the current spread layer 50 has the further advantage of improving, in use, the capacitive coupling between the gate connection terminal 24 and the semiconductor body (in particular, between the gate connection terminal 24 and the drain terminal).

[0064] FIG. 5 illustrates a view of the die 1″ (similarly, of the die 1 and 1′, with the respective elements further present or missing with respect to die 1″) wherein an expanded portion of the edge region 6 is shown. In particular, the view of FIG. 5 shows the presence of a further implanted region 60 in the semiconductor body (in particular in the drift layer 10) facing the front side 1a. The implanted region 60 has the second electrical conductivity (P-type, e.g. of the order of 5.Math.10.sup.16-2.Math.10.sup.17 ions/cm.sup.3) and, for example, is formed in the same step of forming the implanted region 40. The implanted region 60 extends at a distance from the implanted region 40 and, in top view (on the XY plane) is at least in part aligned (along the Z axis direction) with a final part 24b′ of the gate connection terminal 24, in particular with a final part 24b′ of the second portion 24b of the gate connection terminal 24. The presence of the implanted region 60 does not affect the feedback capacitance previously described and represented by the capacitor 32, since this capacitive coupling is in any case provided between the gate connection terminal 24 and the semiconductor body in the region comprised between the implanted region 40 and the implanted region 60. The implanted region 60 has the function of distributing or thinning the field lines of the electrical potential in such a way as that it avoids a thickening of the field lines on the bottom corner of the final part 24b′ of the second portion 24b, thus obviating the risk of making the electric field critical at the final part 24b′.

[0065] In the embodiment of FIG. 5, the length L.sub.shield is the distance (along X and along Y) comprised between the implanted region 40 and the implanted region 60.

[0066] FIG. 6 illustrates a further embodiment of the present disclosure wherein one or more floating regions 61 of P-type, provided by implanting doping species at the front side 1a, are present between the implanted region 40 and the implanted region 60. The floating regions 61 extend at a distance from each other (i.e., an N-type portion of the semiconductor body—in particular of the drift layer 10—is present between a floating region 61 and the subsequent along the X axis direction). A similar layout may be observed along the Y direction.

[0067] In the embodiment of FIG. 6, the length L.sub.shield is the sum of the distances (along X and, similarly, along Y) between a floating region 61 and the subsequent floating region 61 (as well as the distance between the implanted region 40 and the floating region 61 immediately following, and between the implanted region 60 and the floating region 61 immediately preceding).

[0068] The embodiment of FIG. 6, relating to the presence of the floating regions 61, can be applied in a per se evident manner also to the embodiments of FIGS. 2 to 4.

[0069] FIG. 7 illustrates, in top view (on the XY plane) the die 1 of FIG. 1 wherein the extension of the gate connection terminal 24 is also schematically represented. As it is observed, the gate connection terminal 24 has, in this example, the shape of a ring and completely surrounds the active area 4. However, embodiments may be provided wherein the gate connection terminal 24 partially surrounds the active area 4, based on specific layout and design needs.

[0070] The advantages of the proposed solution are evident from what has been previously described.

[0071] In particular, according to the present technical solution, the capacitance C.sub.gd is a device-integrated distributed capacitance.

[0072] The capacitance C.sub.gd between the gate and drain terminals (feedback capacitance) is increased by a factor defined by the capacitive coupling between the gate connection terminal 24 and the underlying N-type doped region of the semiconductor body. In this manner, the increase of the feedback capacitance allows to dampen the amplitude of the oscillations of the drain voltage during the turn-OFF step of the MOSFET (recovery step, or recovery, of the body diode of the MOSFET).

[0073] Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein without thereby departing from the scope of the present disclosure.

[0074] For example, in a further embodiment of the present disclosure illustrated in FIG. 8, a capacitive decoupling layer 70 of P-type is present, at the front side 1a, extending seamlessly below the gate connection terminal 24 or, in other words, interposed between the gate connection terminal 15 24 and the underlying N-type doped region of the semiconductor body. This capacitive decoupling layer 70 has for example a thickness comprised between 0.2-0.4 μm and exemplarily a doping of the order of 10.sup.16 ions/cm.sup.3. In general, the capacitive decoupling layer 70 is designed in such a way that, when the device is in the on-state (for example for values of drain-source voltage Vds higher than 5 V or 10 V) the holes are depleted in the capacitive decoupling layer 70, and the capacitive decoupling layer 70 allows the capacitive coupling between the gate connection terminal 24 and the underlying N-type doped region of the semiconductor body, forming the capacitor 32 as previously described.

[0075] While the embodiment of FIG. 8 is based on FIG. 5, this embodiment (presence of the layer 70) applies similarly to the embodiments of FIGS. 2-4.

[0076] For example, while the present disclosure has been described with explicit reference to an N-channel device, the proposed technical solution applies, in a similar manner, to P-channel devices.

[0077] An electronic device may be summarized as including a semiconductor body (8, 10) having a first electrical conductivity (N) and provided with a front side (1a); an active area (4) of the semiconductor body, accommodating the source (12) and gate (14) regions of the electronic device and configured to accommodate, in use, a conductive channel of the electronic device; an edge region (6) of the electronic device, surrounding the active area (4) and accommodating at least in part: an edge termination region (20), having a second electrical conductivity (P) opposite to the first electrical conductivity (N), extending into the semiconductor body at the front side (1a); and a gate connection terminal (24) of conductive material, electrically coupled to the gate region (14), extending on the front side (1a) partially superimposed on the edge termination region (20), configured to establish, in use, a capacitive coupling (32, C.sub.gd″) with a portion of the semiconductor body having the first electrical conductivity (N), adjacent and external to the edge termination region (20).

[0078] The edge termination region (20) may be in electrical contact with the source region (12).

[0079] The active area (4) may further include a body region (11) having the second electrical conductivity (P), said source region extending inside the body region, and the edge termination region (20) may also be in electrical contact with the body region and has a doping dose greater than the respective doping dose of the body region.

[0080] The electronic device may further include a dielectric layer (30; 30, 22a) interposed between the front side (1a) and the gate connection terminal (24).

[0081] The gate connection terminal (24) may form a first plate of a capacitor (32), the semiconductor body may form a second plate of the capacitor (32), and the dielectric layer (30; 30, 22a) may be interposed between the first and the second plates of the capacitor (32).

[0082] The dielectric layer (30; 30, 22a) may be of Silicon Oxide, or Silicon Nitride, or Silicon Oxynitride.

[0083] The dielectric layer (30; 30, 22a) may be of a high-k material, in particular having a value of the parameter k higher than 7.

[0084] The electronic device may further include a first protection ring (40) having the second electrical conductivity (P) and a doping value lower than a doping value of the edge termination region (20), extending into the semiconductor body at a final portion of the edge termination region (20).

[0085] The electronic device may further include a second protection ring (60) having the second electrical conductivity (P) and a doping value lower than a doping value of the edge termination region (20), extending into the semiconductor body at a final portion (24b′) of the gate connection terminal (24).

[0086] The electronic device may further include one or more floating regions (61) having the second electrical conductivity (P), extending into the semiconductor body between the first protection ring (40) and the second protection ring (60).

[0087] The edge region (6) may further include a current spread layer, CSL, (50) extending into the semiconductor body (8, 10) at the front side (1a), wherein the CSL (50) may have the first electrical conductivity (N) and doping value higher than a doping value of the portion of the semiconductor body (8, 10) wherein it is contained.

[0088] The electronic device may further include a drain region (9) extending at a rear side (1b), opposite to the front side (1a), of the semiconductor body (8, 10).

[0089] The portion of the semiconductor body having the first electrical conductivity (N) adjacent and external to the edge termination region (20) may also be in electrical contact with the drain region (9).

[0090] The gate region (14) may define, with portions of the semiconductor body (8, 10) extending below the gate region (14) and having the first electrical conductivity (N), a first contribution (C.sub.gd′) of capacitance (C.sub.gd) between the gate region and the drain region of the electronic device.

[0091] The capacitive coupling (32, C.sub.gd″) may define a second contribution (C.sub.gd″) of the capacitance (C.sub.gd) between the gate region and the drain region which is added to said first contribution (C.sub.gd′).

[0092] The second contribution (C.sub.gd″) may be designed with a value such that it triggers a parasitic turn-ON, PTO, phenomenon, during a turn-OFF of the electronic device.

[0093] The overlap of the edge termination region (20) with the portion of the semiconductor body having the first electrical conductivity (N) adjacent and external to the edge termination region (20), may have a value L.sub.shield along a reference axis (X; Y) parallel to the front side (1a), which meets the relationship:

[00005]$\begin{array}{c}\frac{{\left(1\text{.15}.Math.{10}^5/m\right)}^{*}{{\mathrm{Th}}_{\mathrm{diel}}}_{{*}^{}}{w}_{AA}}{{\epsilon }_{\mathrm{diel}}}\le L_{\mathrm{shield}}\le \frac{{\left\{2.3.Math.{10}^5/m\right\}}^{*}{\mathrm{Th}}_{\mathrm{diel}}^{*}{w}_{\mathrm{AA}}}{{\epsilon }_{\mathrm{diel}}}\\ \mathrm{or},\mathrm{equivalently}:\\ \frac{{\left(1.Math.{10}^{-6*}F/m^2\right)}^{*}T{h}_{{\mathrm{diel}}^{*}}{w}_{\mathrm{AA}}}{{\epsilon }_{\mathrm{diel}}{\epsilon }_0}\le L_{\mathrm{shield}}\le \frac{{\left(2.Math.{10}^{-6*}F/m^2\right)}^{*}T{h}_{{\mathrm{diel}}^{\star }}{w}_{\mathrm{AA}}}{{\epsilon }_{\mathrm{diel}}{\epsilon }_0}\end{array}$

where: [0094] W.sub.AA is the maximum extension, along said reference axis (X; Y), of the active area (4), the active area (4) having a square shape; [0095] ε.sub.diel is the dielectric constant of the material of the dielectric layer (30; 30, 22a); and [0096] ε.sub.0 is the dielectric constant of vacuum.

[0097] The edge region (6) may further accommodate a capacitive decoupling layer (70) extending into the semiconductor body (8, 10) at the front side (1a) laterally to the edge termination region (20) and interposed between the gate connection terminal (24) and the portion of the semiconductor body having the first electrical conductivity (N) adjacent and external to the edge termination region (20),

[0098] wherein the capacitive decoupling layer (70) is configured to deplete majority carriers having the second electrical conductivity (P) when the electronic device is in use, thus allowing the establishment of said capacitive coupling.

[0099] The capacitive decoupling layer (70) may have a doping dose of the order of 10.sup.16 ions/cm.sup.3, and extends into the semiconductor body with a thickness between 0.2 and 0.4 μm.

[0100] The electronic device may be a vertical conduction MOSFET.

[0101] The semiconductor body may be of Silicon Carbide.

[0102] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.