Abstract
A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.
Claims
1. A circuit, comprising: a first input node configured to receive a first input signal; a second input node configured to receive a second input signal; wherein said first input signal and said second input signal are in phase quadrature; an edge detector circuit configured to receive said first input signal and produce a pulsed signal indicative of edges detected in said first input signal; a pulse skip and reset circuit configured to receive said pulsed signal and said second input signal, and produce a reset signal indicative of pulses detected in said pulsed signal while said second input signal is de-asserted; and a sampling circuit configured to generate an output signal that is deasserted in response to assertion of said second input signal and is asserted in response to a pulse of said reset signal.
2. The circuit of claim 1, wherein said pulsed signal produced by the edge detector circuit is maintained in a normally de-asserted state and is asserted by a signal pulse in response to rising edges and falling edges detected in said first input signal.
3. The circuit of claim 1, wherein said reset signal produced by the pulse skip and reset circuit is maintained in a normally de-asserted state and is asserted by a signal pulse in response to each signal pulse of said pulsed signal while said second input signal is de-asserted.
4. The circuit of claim 1, wherein said edge detector circuit comprises: a delay circuit configured to produce a delayed replica of said first input signal; and a logic circuit configured to apply one of exclusive-NOR signal processing or exclusive-OR signal processing to said first input signal and said delayed replica of said first input signal to produce said pulsed signal.
5. The circuit of claim 1, wherein said pulse skip and reset circuit comprises a logic circuit configured to apply one of NOR signal processing or OR signal processing to said pulsed signal and said second input signal to produce said reset signal.
6. The circuit of claim 1, wherein said sampling circuit comprises a flip-flop having a clock input terminal configured to receive said second input signal, a clear input terminal configured to receive said reset signal, a data input terminal configured to receive a data input signal having a fixed logic value, at a preset input terminal configured to receive a preset input signal having a fixed logic value, and a data output terminal configured to produce said output signal.
7. A method, comprising: receiving a first input signal; receiving a second input signal; wherein said first input signal and said second input signal are in phase quadrature; producing a pulsed signal in response to edges detected in said first input signal; producing a reset signal in response to pulses detected in said pulsed signal while said second input signal is de-asserted; and producing an output signal that is de-asserted in response to assertion of said second input signal and is asserted in response to a pulse being detected in said reset signal.
8. The method of claim 7, wherein producing said pulsed signal comprises: maintaining the pulse signal in a normally de-asserted state; and asserting said pulsed signal by a signal pulse in response to rising edges and falling edges in said first input signal.
9. The method of claim 7, wherein producing said reset signal comprises: maintaining the reset signal in a normally de-asserted state; and asserting said reset signal by a signal pulse in response to each signal pulse of said pulsed signal while said second input signal is de-asserted.
10. A circuit, including: an input node configured to receive an input signal; a timer circuit configured to start running in response to detection of an edge in said input signal and to stop running in response to expiration of a debouncing time interval having a certain duration; and an output node configured to produce an output signal; wherein said input signal is passed from said input node to said output node while said timer circuit is not running; and wherein said output signal is prevented from changing value while said timer circuit is running.
11. The circuit of claim 10, wherein said timer circuit includes a counter circuit configured to start counting in response to the detected edge in said input signal and to stop counting in response to a count number of the counter circuit reaching a threshold value.
12. The circuit of claim 11, further including an adjustment circuit configured to: receive a clock signal; measure a period of said clock signal; and set the threshold value as a function of said measured period of said clock signal.
13. The circuit of claim 12, wherein measuring a period of said clock signal comprises measuring a time elapsed between two pulses detected in said clock signal.
14. The circuit of claim 12, wherein measuring a period of said clock signal comprises measuring an average value of a plurality of periods of said clock signal.
15. The circuit of claim 12, wherein said adjustment circuit is further configured to cap said threshold value to a maximum value.
16. The circuit of claim 12, further including a decoding logic circuit configured to receive said output signal and produce said clock signal by issuing a pulse in said clock signal in response to one or more of a rising edge and a falling edge being detected in said output signal.
17. The circuit of claim 10, further including an adjustment circuit configured to: receive a clock signal; measure a period of said clock signal; and set a duration of said debouncing time interval as a function of said measured period of said clock signal.
18. The circuit of claim 17, wherein measuring a period of said clock signal comprises measuring a time elapsed between two pulses detected in said clock signal.
19. The circuit of claim 17, wherein measuring a period of said clock signal comprises measuring an average value of a plurality of periods of said clock signal.
20. The circuit of claim 17, wherein said adjustment circuit is further configured to cap said debouncing time interval to a maximum value.
21. The circuit of claim 17, further including a decoding logic circuit configured to receive said output signal and produce said clock signal by issuing a pulse in said clock signal in response to one or more of a rising edge and a falling edge being detected in said output signal.
22. The circuit of claim 17, further comprising: a further input node configured to receive a further input signal; wherein the further input signal is in phase quadrature with said input signal; a further timer circuit configured to start running in response to detection of an edge in said further input signal and to stop running in response to expiration of said debouncing time interval; and a further output node configured to produce a further output signal; wherein said further input signal is passed from said further input node to said further output node while said further timer circuit is not running; and wherein said output signal is prevented from changing value while said further timer circuit is running; and a decoding logic circuit configured to receive said further output signal and produce said clock signal by issuing a pulse in said clock signal in response to one or more of a rising edge and a falling edge being detected in said further output signal.
23. A method, comprising: receiving an input signal; start running a timer in response to a detected edge in said input signal; stop running the timer after a debouncing time interval having a certain duration; and passing said input signal to an output signal while said timer circuit is not running, and preventing a change in value of said output signal while said timer circuit is running.
24. The method of claim 23, further including: receiving a clock signal; measuring a period of said clock signal; and setting a duration of said debouncing time interval as a function of said measured period of said clock signal.
25. The method of claim 24, wherein measuring the period of said clock signal comprises measuring a time elapsed between two pulses detected in said clock signal.
26. The method of claim 24, wherein measuring the period of said clock signal comprises measuring an average value of a plurality of periods of said clock signal.
27. The method of claim 24, further comprising capping said debouncing time interval to a maximum value.
28. The method of claim 24, further comprising: receiving said output signal; and producing said clock signal by issuing a pulse in said clock signal in response to one or more of a rising edge and a falling edge being detected in said output signal.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0037] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:
[0038] FIGS. 1 to 3, previously presented, are circuit block diagrams exemplary of various rotary encoder systems;
[0039] FIG. 4 is a circuit block diagram exemplary of decoding circuitry configured to decode quadrature signals produced by a rotary encoder;
[0040] FIG. 5 is a time diagram exemplary of possible time evolution of signals in the decoding circuitry of FIG. 4;
[0041] FIG. 6 is a circuit block diagram exemplary of a debouncing circuit suitable for use in debouncing quadrature signals, according to one or more embodiments of the present description;
[0042] FIG. 7 is a time diagram exemplary of possible time evolution of signals in the debouncing circuit of FIG. 6;
[0043] FIG. 8 is a circuit block diagram exemplary of a possible detailed implementation of the debouncing circuit of FIG. 6;
[0044] FIG. 9 is a circuit block diagram exemplary of decoding circuitry configured to debounce and decode signals produced by a rotary encoder, according to one or more embodiments of the present description;
[0045] FIG. 10 is a time diagram exemplary of possible time evolution of signals in the decoding circuitry of FIG. 9;
[0046] FIG. 11 is another circuit block diagram exemplary of decoding circuitry configured to debounce and decode signals produced by a rotary encoder, according to one or more embodiments of the present description;
[0047] FIG. 12 is a time diagram exemplary of possible time evolution of signals in the decoding circuitry of FIG. 11;
[0048] FIG. 13 is a circuit block diagram exemplary of a possible detailed implementation of the decoding circuitry of FIG. 11;
[0049] FIG. 14 is a time diagram exemplary of a possible time evolution of signals in the decoding circuitry of FIG. 13; and
[0050] FIG. 15 is a circuit block diagram exemplary of a possible detailed implementation of the decoding circuitry of FIG. 11.
DETAILED DESCRIPTION
[0051] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.
[0052] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is included in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
[0053] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
[0054] Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for the sake of brevity.
[0055] By way of introduction to the detailed description of exemplary embodiments, reference may first be made to FIGS. 4 and 5. FIG. 4 is a circuit block diagram exemplary of decoding circuitry 40 configured to decode quadrature signals produced by a rotary encoder. FIG. 5 is a time diagram exemplary of possible time evolution of signals in the decoding circuit of FIG. 4.
[0056] As exemplified in FIGS. 4 and 5, decoding circuitry 40 includes a decoding logic circuit (DL) 42 and a (bidirectional) counter circuit (CC) 44. The decoding logic circuit 42 is configured to receive two quadrature signals IN1 and IN2 (e.g., corresponding to quadrature signals A and B exemplified in FIGS. 1 to 3) produced, for example, by a quadrature rotary encoder, process the two quadrature signals IN1 and IN2, and produce a first output signal CLK (e.g., a clock signal) and a second output signal DIR.
[0057] The first output signal CLK of the decoding logic circuit 42 includes a train of pulses indicative of the rising and/or falling edges detected in the first quadrature signal IN1 and/or in the second quadrature signal IN2, depending on the operation mode of the decoding circuitry 40. Therefore, one or more edge detector circuits may be included in the decoding logic circuit 42 for producing signal CLK. For instance, in a first operation mode (also referred to as x1 mode) the decoding logic circuit 42 may be configured to produce an output signal CLKx1 including a pulse (only) at each falling edge (or rising edge) of signal IN1. In a second operation mode (also referred to as x2 mode), the decoding logic circuit 42 may be configured to produce an output signal CLKx2 including a pulse at each falling edge and each rising edge of signal IN1. In a third operation mode (also referred to as x4 mode), the decoding logic circuit 42 may be configured to produce an output signal CLKx4 including a pulse at each falling edge and each rising edge of both signals IN1 and IN2. By passing to (e.g., selecting) the x1 mode to the x2 mode or even to the x4 mode, the resolution of the encoder is increased.
[0058] The second output signal DIR of the decoding logic circuit 42 is indicative of the lagging/leading relationship of the signals IN1, IN2, for example as indicating the direction of rotation (clockwise or counterclockwise) of the encoder shaft, which is determined as a function of the phase shift between signals IN1 and IN2. For instance, as exemplified in FIG. 5, signal DIR may be set to a first value (e.g., a low logic value, ‘0’) when the first quadrature signal IN1 leads in time (e.g., anticipates) the second quadrature signal IN2, and may be set to a second value (e.g., a high logic value, ‘1’) when the first quadrature signal IN1 trails in time (e.g., follows) the second quadrature signal IN2.
[0059] Signal CLK (i.e., CLKx1, CLKx2 or CLKx4) and signal DIR are received by the counter circuit 44, which is triggered at each pulse of signal CLK to increase or decrease its (internal) count number to produce an output signal CNT (e.g., CNTx1, CNTx2 or CNTx4 as exemplified in FIG. 5, depending on the operation mode) that is indicative of the (relative) angular position of the encoder shaft. For instance, as exemplified in FIG. 5, counter 44 may increase its internal count number at each pulse of signal CLK if signal DIR has the first (e.g., low) value, and may decrease its internal count number at each pulse of signal CLK if signal DIR has the second (e.g., high) value. The value of the output signal CNT of the counter 44 can therefore be correlated to the (relative) angular position of the encoder shaft, exemplified by quantity pos in FIG. 5 (where a solid thick line is exemplary of the position detected in x4 mode, a dotted line is exemplary of the position detected in x2 mode, and a solid thin line is exemplary of the position detected in x1 mode).
[0060] As previously discussed, the quadrature signals IN1 and IN2 may suffer from bouncing effects, e.g., their transitions from one logic value to the other may include a plurality of edges. In that case, signal CLK would be incorrectly determined and would thus incorrectly trigger the counter circuit 44, resulting in an erroneous decoding.
[0061] FIG. 6 is a circuit block diagram exemplary of one or more embodiments of a debouncing circuit 6 suitable for debouncing quadrature signals. FIG. 7 is a time diagram exemplary of possible time evolution of signals in the debouncing circuit of FIG. 6. Operation of a debouncing circuit as exemplified in FIGS. 6 and 7 relies on the recognition that, by their nature, one of the two quadrature signals coming from a quadrature encoder (e.g., IN1) is stable when the other of the two quadrature signals (e.g., IN2) is subject to a transition (with possible bouncing), and vice versa. In other words, such embodiments rely on the inherent self-temporization of the quadrature signals.
[0062] In particular, the debouncing circuit 6 is configured to receive quadrature signals IN1 and IN2 possibly affected by bouncing effects (e.g., from a rotary encoder). The debouncing circuit 6 includes an edge detector circuit (ED) 60 configured to receive the first quadrature signal IN1 and produce a pulsed signal E indicative of the edges of signal IN1. For instance, as exemplified in FIG. 7, the pulsed signal E may be normally set to a default value and may be shortly asserted in response to each edge detected in signal IN1 (e.g., at both the rising edges and falling edges of signal IN1). In other words, the pulsed signal E may assert a pulse in response to each edge detected in signal IN1. By way of non-limiting example, as exemplified in FIG. 7, the default value of signal E may be a high logic value (‘1’) and its pulses may have a low logic value (‘0’), but the opposite may be possible. The debouncing circuit 6 further includes a pulse skip and reset circuit (PSR) 62 configured to receive the second quadrature signal IN2 and the pulsed signal E, and to produce a reset (or clear) signal CLR indicative of a subset of the pulses of the pulsed signal E, in particular indicative of the pulses of the pulsed signal E produced (only) while the second quadrature signal IN2 is de-asserted. In other words, the pulse skip and reset circuit 62 substantially skips the pulses of the pulsed signal E produced while the second quadrature signal IN2 is asserted. By way of non-limiting example, as exemplified in FIG. 7, the reset signal CLR may be de-asserted while the second quadrature signal IN2 is asserted, and may correspond to the complement of the pulsed signal E (possibly slightly delayed) while the second quadrature signal IN2 is de-asserted. Still in other words, the reset signal CLR may be an inverted replica of the pulsed signal E, gated as a function of the second quadrature signal IN2. It is noted that, depending on the architecture of the debouncing circuit 6, the polarity of signal CLR could be inverted in one or more embodiments, depending on the surrounding logic: in other words, signal CLR may be a replica of the pulsed signal E, gated as a function of the second quadrature signal IN2. The debouncing circuit 6 further includes a sampling circuit (S) 64 configured to receive the second quadrature signal IN2 at a respective clock input and the reset signal CLR at a respective reset or clear input, and produce a debounced quadrature signal IN2′. For instance, as exemplified in FIG. 7, the debounced quadrature signal IN2′ may be de-asserted (i.e., the sampling circuit 64 may be set) when a first rising edge is detected in the second quadrature signal IN2, and the debounced quadrature signal IN2′ may be asserted (i.e., the sampling circuit 64 may be reset) when a first pulse is detected in the reset signal CLR. Again, it is noted that, depending on the architecture of the debouncing circuit 6, the polarity of signal IN2′ could be inverted in one or more embodiments. By construction, the first reset pulse in the reset signal CLR is generated when the second quadrature signal IN2 is stable in a de-asserted state, because the reset pulses are generated at the transitions of the first quadrature signal IN1. Also, by construction, de-assertion of signal IN2 takes place when signal IN1 is stable.
[0063] It is again noted that, depending on the architecture of the debouncing circuit 6, the polarity of one or more of signals E, CLR and IN2′ could be inverted in one or more embodiments. Additionally, it will be understood that the polarity of assertion and de-assertion, to which reference is made in the present description, may not be the same for all signals. For instance, the edge detector circuit 60 may generate a negative or positive assertion according to the downstream logic, e.g., depending on the designer's choice and/or on the automatic tool that optimizes the synthesized logic.
[0064] As exemplified in FIG. 6, the first quadrature signal IN1 and the debounced quadrature signal IN2′ may then be propagated to a decoding circuitry (such as the decoding circuitry 40 exemplified in FIG. 4) operating in the x1 mode (i.e., using only the rising or falling edges of the debounced quadrature signal IN2′ for generating the clock signal CLK for the counter 44).
[0065] FIG. 8 is a circuit block diagram exemplary of a possible detailed implementation of the debouncing circuit 6 exemplified in FIG. 6.
[0066] In the example of FIG. 8, the edge detector circuit 60 includes a delay circuit (e.g., an analog delay circuit or a digital delay circuit) configured to produce a slightly delayed replica IN1d of the first quadrature signal IN1. For instance, an analog delay circuit may comprise an RC filter circuit comprising a resistor R1 and a capacitor C1. By way of example, resistor R1 may have a resistance of about 100 kOhm and capacitor C1 may have a capacitance of about 200 nF. The edge detector circuit 60 further includes an exclusive logic gate 601 (e.g., an exclusive-NOR, XNOR) configured to receive the first quadrature signal IN1 and its delayed replica IN1d to produce the pulsed signal E indicative of the edges of signal IN1 as previously discussed.
[0067] In the example of FIG. 8, the pulse skip and reset circuit 62 includes a logic gate 621 (e.g., a NOR logic gate) configured to receive the second quadrature signal IN2 and the pulsed signal E to produce the reset signal CLR as previously discussed. Optionally, the reset signal CLR may be (slightly) delayed before being propagated to the sampling circuit 64, e.g., via a delay circuit (e.g., an analog delay circuit or a digital delay circuit), in order to properly clock the sampling circuit 64 when the second quadrature signal IN2 asserts before the reset signal CLR is disabled. For instance, an analog delay circuit may comprise an RC filter circuit comprising a resistor R2 and a capacitor C2. By way of example, resistor R2 may have a resistance of about 100 Ohm and capacitor C2 may have a capacitance of about 10 nF. Alternatively, a digital delay circuit may be implemented by cascading a certain number of logic gates (e.g., inverters, with the right overall polarity) in order to exploit the cumulative transmission delay of the chain.
[0068] In the example of FIG. 8, the sampling circuit 64 includes a D-type edge-triggered flip-flop (FF) having a data input (D) configured to receive a signal H having a fixed value (e.g., logic high), a clock input (CLK) configured to receive signal IN2 as the clock signal, a preset input (PRE) configured to receive a fixed value (e.g., logic low) opposite to the value of signal H, a clear input (CLR) configured to receive signal CLR as a clear signal, a first data output (Q), and a second data output (Q) configured to produce the debounced signal IN2′ having the expected polarity. Depending on the polarity of the downstream logic, the first data output (Q) could be selected to produce the debounced signal. It is also noted that a different type of flip-flop circuit (e.g., a JK flip-flop) may be implemented in the sampling circuit 64, depending on the desired implementation. In general, the flip-flop is connected such as to assert an output signal IN2′, (only) when it is out of reset, in response to an active edge of the respective clock signal which in this case is the second quadrature signal IN2, which in turn can be set by proper signal conditioning.
[0069] One or more embodiments as exemplified with reference to FIGS. 6, 7 and 8 may thus be advantageous insofar as their implementation relies on a simple (e.g., minimal) and fast logic. Additionally, in these embodiments the debouncing processing does not need a timer to be implemented. These embodiments may operate correctly even for high-speed applications, as long as the bouncing time interval is lower than 25% of the period of the quadrature signals IN1 and IN2. Additionally, these embodiments may self-adapt to pulse period changes (e.g., from standstill condition to low-speed movement to high-speed movement of the rotary encoder, which in the case of hand-driven rotary encoders or knobs may be typically limited to roughly one revolution per second). These embodiments may also be configured with a pre-conditioning logic (e.g., including a multiplexer and/or one or more inverters) placed upstream of the IN1 and IN2 inputs, for instance, in order to condition the polarity of the input signal(s) to change the leading edge polarity, or to multiplex different channels, etc.
[0070] In general, it is to be noted that the detailed implementation exemplified in FIG. 8 represents a possible embodiment of the present disclosure, which could be subject to various modifications without departing from the scope of the present application, regarding for instance the choice of the assertion/de-assertion polarity of signals, the choice of an alternative sampling circuit 64, the choice of alternative implementations for the logic circuitry in the edge detector circuit 60 and/or in the pulse skip and reset circuit 62, and the like.
[0071] Other embodiments will now be described, which rely on operation of a timer circuit for controlling the debouncing processing of quadrature signals IN1 and/or IN2.
[0072] FIG. 9 is a circuit block diagram exemplary of decoding circuitry 9 configured to debounce and decode signals produced, for example, by a rotary encoder. FIG. 10 is a time diagram exemplary of possible time evolution of signals in the decoding circuit of FIG. 9.
[0073] As exemplified in FIGS. 9 and 10, decoding circuitry 9 includes a decoder 40 substantially as disclosed with reference to FIG. 4. Additionally, the decoding circuitry 9 includes a first debouncer (DB) circuit 90.sub.1 coupled between the first output channel of the rotary encoder 10 and the first input of decoder 40 to debounce signal IN1 and produce a first debounced signal INF, and a second debouncer (DB) circuit 90.sub.2 coupled between the second output channel of the rotary encoder 10 and the second input of decoder 40 to debounce signal IN2 and produce a second debounced signal IN2′.
[0074] Each of the debouncer circuits 90.sub.1 and 90.sub.2 may include (e.g., consist of) a single-shot non-retriggerable counter, which substantially operates as a timer. FIG. 10 exemplifies possible operation of the first debouncer circuit 90.sub.1 (the same applying also to the second debouncer circuit 90.sub.2). The debouncer circuit 90.sub.1 receives the quadrature signal IN1, possibly affected by bouncing effects. The debouncer circuit 90.sub.1 includes an edge detector that produces a pulsed signal IN1e indicative of the rising and/or falling edges detected in the first quadrature signal IN1. For instance, the pulsed signal IN1e may be normally de-asserted and may include a short positive pulse (i.e., it may be briefly asserted) in response to each edge detected in signal IN1 (e.g., at both the rising edges and falling edges of signal IN1). Also in this case, as previously discussed, the polarity of signal IN1e may be inverted in one or more embodiments. The single-shot non-retriggerable counter of circuit 90.sub.1 is started in response to a first pulse being detected in the pulsed signal IN1e, and counts (see the counter value cnt.sub.int in FIG. 10) at a constant rate until reaching a determined (e.g., predetermined) stop value or threshold value C.sub.th. While the counter is not counting (i.e., it has not been triggered, or it has already reached its threshold value C.sub.th), the debouncer circuit 90.sub.1 passes (e.g., in a transparent way) the input quadrature signal IN1 to the output. To the contrary, while the counter is counting (i.e., between the first detected pulse of signal IN1e and the moment when the threshold value C.sub.th is reached), the output of the debouncer circuit 90.sub.1 is prevented from changing value (e.g., any change at the output is inhibited): see signal OUT_dis in FIG. 10, which when asserted prevents the output of the debouncer circuit 90.sub.1 from changing. Therefore, additional edges in signal IN1 that follow the first detected edge are ignored (e.g., not passed to the output of circuit 90.sub.1) until the counter reaches the threshold value C.sub.th, and the output signal IN1′ of the debouncer circuit 90.sub.1 is thereby debounced. In other words, the counter operates as a timer that inhibits any output change during a (pre)defined time interval following the first detected edge in the input signal IN1. After reaching the threshold value C.sub.th, the counter is reset and starts counting again (e.g., from zero) in response to detection of another pulse in the pulsed signal IN1e.
[0075] One or more embodiments as exemplified with reference to FIGS. 9 and 10 may thus be advantageous insofar as the output signals IN1′ and IN2′ of the debouncer circuits 90.sub.1 and 90.sub.2 are in-phase (e.g., not delayed) with respect to the respective input signals IN1 and IN2. A single clock cycle delay may be present (e.g., a propagation delay due to the synchronous design of the debouncing circuitry), but this may be negligible compared to the timing of the input signal (e.g., 10 ns delay in the case of a 100 MHz design). Advantageously, these embodiments allow for running the decoder in the x4 mode, thus using the full encoder resolution.
[0076] In the embodiments disclosed with reference to FIGS. 9 and 10, the debouncing window (time interval) may have a fixed duration, e.g., the threshold value C.sub.th may be fixed and may not vary with the clock rate of the encoder. Since the useful bouncing period may happen to be longer than the debouncing window, particularly at a low rotation rate of the encoder 10, other embodiments will now be described, where the duration of the debouncing window may be adjusted (e.g., continuously and dynamically).
[0077] FIG. 11 is a circuit block diagram exemplary of decoding circuitry 11 configured to debounce and decode signals produced, for example, by a rotary encoder, wherein the duration of the debouncing window is adjustable. FIG. 12 is a time diagram exemplary of possible time evolution of signals in the decoding circuit of FIG. 11.
[0078] As exemplified in FIGS. 11 and 12, decoding circuitry 11 includes a decoder 40 substantially as disclosed with reference to FIG. 4, as well as debouncer circuits 90.sub.1 and 90.sub.2 coupled to each channel of the rotary encoder 10. Additionally, the decoding circuitry 11 includes a debouncing period adjustment circuit 110 configured to control the debouncer circuits 90.sub.1 and 90.sub.2 so that the respective threshold values C.sub.th (and thus, the duration of the debouncing windows) are adapted (e.g., dynamically, “on-the-fly”) as a function of the period of the clock signal CLK.
[0079] As exemplified in FIGS. 11 and 12, circuit 110 is configured to sense the clock signal CLK output by the decoding logic circuit 42. At an operation step (Per) 111, circuit 110 is configured to measure a period of the clock signal CLK. For instance, the period may be computed as the time interval between the last two detected pulses of the clock signal CLK. Additionally or alternatively, the period may be computed as an average value over several periods of the clock signal CLK (e.g., a rolling average or moving average). At an operation step (ck) 112 (which may be executed contextually with step 111, e.g., during the clock period measurement), circuit 110 is configured to check whether a timeout has elapsed (e.g., in case the rotary encoder is in a standstill condition or moving very slowly, and the clock signal CLK does not contain any pulse or few pulses). In response to a positive outcome (Y) of step 112 (i.e., if the measured period exceeds the timeout interval), the measured clock period T.sub.MEAS is set to a certain maximum value T.sub.MAX (i.e., the measured clock period T.sub.MEAS is capped to T.sub.MAX) at an operation step (max) 113. Otherwise, in response to a negative outcome (N) of step 112 (i.e., if the measured period is shorter than the timeout interval), the measured clock period T.sub.MEAS is maintained to its measured value. At an operation step (set) 114, circuit 110 is configured to set the current value of the counter threshold C.sub.th as a function of the measured clock period T.sub.MEAS. For instance, the counter threshold C.sub.th may be set so that the counter in circuit 90.sub.1 takes a time T.sub.count equal to a certain percentage (e.g., 25%) of the measured clock period T.sub.MEAS to count from its reset value (e.g., zero) to the threshold value C.sub.th. By doing so, the output signal IN1′ of debouncer circuit 90.sub.1 is prevented from changing its value for a time interval T.sub.count after each pulse of signal IN1e, with time interval T.sub.count being dynamically adapted.
[0080] For instance, as exemplified in FIG. 12, the single-shot non-retriggerable counter of circuit 90.sub.1 is started in response to a first pulse being detected in the pulsed signal IN1e, and counts over a time window W.sub.1 at a constant rate until reaching a threshold value C.sub.th1 that is a function of a previous period T.sub.0 (not visible in FIG. 12). While the counter is counting, the output of the debouncer circuit 90.sub.1 is prevented from changing value (e.g., signal OUT_dis is asserted). After reaching the threshold value C.sub.th1, the counter is reset and starts counting again (e.g., from zero) in response to detection of another pulse in the pulsed signal IN1e. In this case, the counter counts over a time window W.sub.2 until reaching a threshold value C.sub.th2 that is a function of the last measured clock period T.sub.3 of signal CLK. For instance, C.sub.th2 may be selected so that W.sub.2=0.25*T.sub.3 or W.sub.2=0.4*T.sub.3. When another pulse is detected in the pulsed signal IN1e, the counter counts over a time window W.sub.3 until reaching a threshold value C.sub.th3 that is a function of the last measured clock period T.sub.5 of signal CLK. For instance, C.sub.th3 may be selected so that W.sub.3=0.25*T.sub.5 or W.sub.3=0.4*T.sub.5. In other words, the counter of circuit 90.sub.1 operates as a timer that inhibits any output change during an adaptive time interval following the first detected edge in the input signal IN1, wherein the duration of the time interval is set as a function of one or more of the clock periods(s) of clock signal CLK.
[0081] FIG. 13 is a circuit block diagram exemplary of possible implementation details of a debouncing period adjustment circuit 110, where the period of the clock signal CLK is computed as the time interval between the last two detected pulses of the clock signal CLK. FIG. 14 is a time diagram exemplary of possible time evolution of signals in the debouncing period adjustment circuit 110 of FIG. 13.
[0082] In the example of FIG. 13, the adjustment circuit 110 may include an edge detector (Det) 130 configured to receive the clock signal CLK and produce a pulsed signal ED indicative of the edges of the clock signal CLK (e.g., both rising and falling edges). Signal ED may thus comprise a pulse at each edge of signal CLK. Alternatively, if the clock signal CLK already includes (e.g., is composed of) a train of pulses (as disclosed, for instance, with reference to FIGS. 4 and 5), the edge detector 130 may be omitted, and signal ED may substantially correspond to the clock signal CLK. The adjustment circuit 110 includes a counter circuit (Count) 131 which receives signal ED and is configured to be reset and start counting (e.g., increasing an internal count number c.sub.131) at each pulse in signal ED. Advantageously, the counter circuit 131 may operate at the same rate as the internal counter of circuits 90.sub.1 and 90.sub.2. The adjustment circuit 110 includes a capture register (Reg) 132 configured to capture (e.g., store) the value c.sub.131 of the counter circuit 131 at each pulse in signal ED, before reset of the counter circuit 131. The adjustment circuit 110 comprises a divider circuit (Div) 133 (e.g., a shift register) configured to read the value c.sub.132 stored in the capture register 132 and divide it to produce a divided value c.sub.133. For instance, the divider 133 may implement a division by four (e.g., implementing a 2-bit right shift) or a division by two (e.g., implementing a 1-bit right shift). The adjustment circuit 110 comprises a comparator circuit (Comp) 134 configured to compare the value c.sub.131 of the counter circuit 131 to a threshold value c.sub.134. The adjustment circuit 110 comprises a multiplexer 136 configured to receive the output c.sub.133 from the divider 133 as a first input and a timeout value c.sub.135 from a timeout register (TO) 135 as a second input. The timeout value c.sub.135 may be equal to the threshold value c.sub.134 divided by the same division factor of divider 133 (e.g., c.sub.135=c.sub.134/4 or c.sub.135=c.sub.134/2). At the system start-up, the timeout value c.sub.135 may be passed at the output of multiplexer 136 until a valid clock period measure is carried out by circuits 131 and 132. During operation, once a first valid clock period measure has been carried out, the multiplexer 136 is controlled by control signals ctr1, ctr2 issued by the capture register 132 and by the comparator circuit 134, respectively, so that: if both control signals ctr1 and ctr2 are de-asserted (indicating that the value c.sub.132 stored in the capture register 132 is not valid and that the counter value c.sub.131 has not reached the threshold value c.sub.134) the multiplexer 136 keeps its output at the latest valid value; if control signal ctr2 is asserted (indicating that the counter value c.sub.131 has reached the threshold value c.sub.134) the multiplexer 136 passes the value c.sub.135 stored in the timeout register 135 to its output, independently from the value of control signal ctr1; and if control signal ctr1 is asserted and control signal ctr2 is de-asserted (indicating that the value c.sub.132 stored in the capture register 132 is valid and that the counter value c.sub.131 has not reached the threshold value c.sub.134) the multiplexer 136 passes the value c.sub.133 output by the divider circuit 133 to its output. The value passed by the multiplexer 136 is received by circuits 90.sub.1 and/or 90.sub.2 to be used as the counter threshold C.sub.th.
[0083] FIG. 15 is a circuit block diagram exemplary of possible implementation details of a debouncing period adjustment circuit 110, where the period of the clock signal CLK is computed as a rolling average value over several (e.g., eight) periods of the clock signal CLK.
[0084] Substantially, the example of FIG. 15 adds to the example of FIG. 13 a FIFO register 150 (e.g., an eight-level FIFO register), an adder circuit 152 and a divider circuit 154 (e.g., a divider by eight, possibly implemented by a 3-bit right shift register). The FIFO register 150 is coupled to the capture register 132 and is thus configured to store the last (e.g., eight) values c.sub.132 output by the compare register 132. The adder circuit 152 adds all the values stored in the FIFO register 150, and the divider circuit 154 divides the value output by the adder circuit 152 to produce an average value c′ 132 that is fed to the divider circuit 133, and then to the multiplexer 136.
[0085] One or more embodiments as exemplified with reference to FIGS. 11 to 15 may thus be further advantageous insofar as they provide a de-bouncing interval that auto-adapts to clock period changes, and thus to changes of the rotation speed of the rotary encoder (e.g., from a standstill condition to a low rotation speed to a high rotation speed).
[0086] It is noted that, while various embodiments have been exemplified in FIGS. 9 to 15 where a debouncer circuit is associated with (e.g., coupled to) each channel of the rotary encoder so as to debounce both quadrature signals IN1 and IN2 and allow the decoder circuitry to operate in the high-resolution x4 mode, one or more embodiments may comprise a single debouncer circuit associated with only one of the encoder channels, still allowing the decoder circuitry to operate in the lower resolution modes x2 and x1.
[0087] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.
[0088] The claims are an integral part of the technical teaching provided herein in respect of the embodiments.
[0089] The extent of protection is determined by the annexed claims.
