TEMPERATURE-COMPENSATED ENVELOPE DETECTOR CIRCUIT

Abstract

In accordance with an embodiment, an envelope detector includes a first transistor having a first current conduction terminal coupled to a first connection node; a second current conduction terminal coupled to an intermediate node; and a control terminal coupled the signal input node and to a biasing node; a second transistor having a first current conduction terminal coupled to the intermediate node; a second current conduction terminal coupled to a second connection node; and a control terminal coupled to the biasing node; and a first temperature compensating transistor that is diode-connected and coupled between a compensation output node and the biasing node. The second connection node is coupled to the compensation output node and the first connection node is coupled to a detector output.

Claims

1. An envelope detector circuit comprising: an envelope extracting portion comprising a first connection node, a second connection node, a signal input node configured to receive an input voltage, a biasing node, and an extraction branch comprising an extraction module having a first extraction transistor and a second extraction transistor, wherein: the first extraction transistor and the second extraction transistor are coupled to an intermediate node, the first extraction transistor comprises a first current conduction coupled to the first connection node, a second current conduction terminal coupled to the intermediate node, and a control terminal coupled to the signal input node and to the biasing node, and the second extraction transistor comprises a first current conduction terminal coupled to the intermediate node, a second current conduction terminal coupled to the second connection node; and a control terminal coupled to the biasing node; and a temperature compensating portion having a compensation output node coupled to the biasing node and including a first temperature compensating transistor; the first temperature compensating transistor being diode-connected, coupled between the compensation output node and the biasing node and configured to operate in a subthreshold condition, wherein one of the first connection node or the second connection node is coupled to the compensation output node and another of the first connection node or the second connection node is coupled to a detector output of the envelope detector circuit.

2. The envelope detector circuit according to claim 1, wherein the temperature compensating portion further comprises: a second temperature compensating transistor, the second temperature compensating transistor being diode-connected and coupled between a supply line and a compensating portion node, a third temperature compensating transistor, the third temperature compensating transistor being mirror-like coupled to the second temperature compensating transistor and coupled between the supply line and the compensation output node; a fourth temperature compensating transistor, the fourth temperature compensating transistor being mirror-like coupled to the first temperature compensating transistor and coupled between the compensating portion node and the compensation output node; a fifth temperature compensating transistor, the fifth temperature compensating transistor being diode-connected and coupled between the compensation output node and a reference potential line; and a resistor element coupled between the fourth temperature compensating transistor and the compensation output node.

3. The envelope detector circuit according to claim 2, wherein the first, the fourth and the fifth temperature compensating transistors are NMOS type transistors, and the second and the third temperature compensating transistors are PMOS type transistors.

4. The envelope detector circuit according to claim 1, wherein the extraction module is a first extraction module and the extraction branch comprises a plurality of further extraction modules, the first extraction module and the plurality of further extraction modules being cascade-coupled.

5. The envelope detector circuit according to claim 1, wherein the first current conduction terminal of the first extraction transistor is coupled to the detector output, and the second current conduction terminal of the second extraction transistor is coupled to the second connection node.

6. The envelope detector circuit according to claim 5, wherein: the extraction branch is a first extraction branch; the extraction module is a first extraction module; the envelope extracting portion comprises a second extraction branch; and the second extraction branch includes a second extraction module comprising: a third extraction transistor having a first current conduction terminal coupled to the first connection node, a second current conduction terminal coupled to the intermediate node, and a control terminal coupled to the signal input node and to the biasing node, and a fourth extraction transistor having a first current conduction terminal coupled to the intermediate node, a second current conduction terminal coupled to the second connection node, and a control terminal coupled to the biasing node.

7. The envelope detector circuit according to claim 6, wherein the first current conduction terminal of the third extraction transistor is coupled to the second connection node and the second current conduction terminal of the fourth extraction transistor is coupled to the detector output.

8. An envelope detector comprising: a proportional to absolute temperature (PTAT) bias circuit comprising a diode-connected transistor configured to conduct a PTAT current, and a first bias transistor having a conduction terminal coupled to a gate of the diode-connected transistor, wherein the gate of the diode-connected transistor is coupled to a conduction terminal bias node and a gate of the first bias transistor is coupled to a gate bias node; a first detection branch comprising: a first transistor having a conduction path coupled between the conduction terminal bias node and a first intermediate node, and a gate resistively coupled to the conduction terminal bias node and capacitively coupled to an RF input node, and a second transistor having a conduction path coupled between the first intermediate node and a first detector output node, and a gate coupled to the conduction terminal bias node, wherein the first intermediate node is capacitively coupled to the RF input node; and a second detection branch comprising: a third transistor having a conduction path coupled between the conduction terminal bias node and a second intermediate node, and a gate coupled to the conduction terminal bias node, and a fourth transistor having a conduction path coupled between the second intermediate node and a second detector output node, and a gate resistively coupled to the conduction terminal bias node and capacitively coupled to the RF input node, wherein the second intermediate node is capacitively coupled to the RF input node.

9. The envelope detector of claim 8, wherein the conduction terminal bias node and the gate bias node is configured to bias the first transistor, the second transistor, the third transistor and the fourth transistor to have a temperature compensated channel resistance.

10. The envelope detector of claim 8, wherein the first detector output node and the second detector output node are configured to provide a differential signal representative of an envelope of a signal at the RF input node.

11. The envelope detector of claim 10, wherein noise generated by the PTAT bias circuit is configured to have a higher power in a common mode portion of a signal generated by the first detector output node and the second detector output node than in the differential signal representative of the envelope of the signal at the RF input node.

12. The envelope detector of claim 8, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are NMOS transistors.

13. The envelope detector of claim 8, wherein the PTAT bias circuit further comprises: a second bias transistor having a conduction path coupled between a power supply node and a third intermediate node, the second bias transistor being diode-connected; a bias resistor having a first terminal coupled to a gate of the diode-connected transistor; a third bias transistor having a conduction path coupled between the third intermediate node and a second terminal of the bias resistor; and a fourth bias transistor having a conduction path coupled between the power supply node and a conduction path of the first bias transistor, wherein the first bias transistor is diode-connected.

14. The envelope detector of claim 8, further comprising: a first capacitor coupled between the first detector output node and a reference node; and a second capacitor coupled between the second detector output node and the reference node.

15. A method of detecting an envelope, comprising: detecting an RF signal using a first branch circuit comprising a first transistor having a conduction path coupled between a first detection output and a first intermediate node, and a second transistor having a conduction path coupled between a the first intermediate node and a first bias node to provide a first envelope signal at the first detection output; detecting the RF signal using a second branch circuit comprising a third transistor having a conduction path coupled between a second detection output and a second intermediate node, and a fourth transistor having a conduction path coupled between the second intermediate node and the first bias node to provide a second envelope signal at the first detection output; and biasing the first transistor, the second transistor, the third transistor and the fourth transistor to have a temperature compensated channel resistance.

16. The method of claim 15, further comprising receiving the RF signal at a gate of the first transistor, at a gate of the fourth transistor, at the first intermediate node, and at the second intermediate node.

17. The method of claim 15, wherein biasing comprises: providing a gate bias voltage to the gates of the first transistor, the second transistor, the third transistor and the fourth transistor; and providing a conduction terminal bias voltage to the first bias node, wherein a voltage difference between the gate bias voltage and the conduction terminal bias voltage is configured to cause the channel resistance of the first transistor, the second transistor, the third transistor and the fourth transistor to track temperature.

18. The method of claim 17, wherein: providing the gate bias voltage to the gate of the first transistor comprises providing the gate bias voltage to the gate of the first transistor via a first resistor; and providing the gate bias voltage to the gate of the fourth transistor comprises providing the gate bias voltage to the gate of the fourth transistor via a second resistor.

19. The method of claim 17, wherein providing the gate bias voltage and providing the conduction terminal bias voltage comprises using a proportional to absolute temperature (PTAT) bias circuit.

20. The method of claim 19, wherein noise generated by the PTAT bias circuit has a higher power in a common mode component of the first detection output and the second detection output than in a differential mode component of the first detection output and the second detection output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] For the understanding of the present invention, embodiments thereof are now described, purely as a non-limitative examples, with reference to the enclosed drawings, wherein:

[0040] FIG. 1 is a schematic block diagram of a demodulating device including an envelope detector;

[0041] FIG. 2 is a schematic circuit diagram of an embodiment of a known envelope detector that may be used in the demodulating device of FIG. 1;

[0042] FIG. 3 is a schematic circuit diagram of an embodiment of another known envelope detector that may be used in the demodulating device of FIG. 1;

[0043] FIG. 4 is a schematic circuit diagram of an embodiment of the present envelope detector; and

[0044] FIG. 5 is a schematic circuit diagram of another embodiment of the present envelope detector.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0045] FIG. 4 shows an envelope detector 50 that may be used in the demodulating device 1 of FIG. 1. As shown, envelope detector 50 includes an envelope extracting portion 51 and a temperature compensating circuit 52. Envelope extracting portion 51 has a general structure similar to the general structure of the envelope detector 10′ of FIG. 2.

[0046] Therefore, the modules and the components of envelope extracting portion 51 in common with the envelope detector 10′ of FIG. 2 are indicated by the same reference numbers, and the description of the structure and connection thereof are not repeated, except for where useful for the comprehension.

[0047] In particular, envelope extracting portion 51 is of passive type and includes a plurality of modules 11, 12 that are cascade coupled and have the same structure and connections of modules 11, 12 of FIG. 2.

[0048] Also here, only two modules 11, 12 that are adjacent in the cascade sequence are shown, but, in general, many modules may be comprised in the envelope extracting portion 51.

[0049] Also here, modules 11, 12 have signal input nodes 23 receiving the signal to be demodulated, also indicated as input voltage V.sub.in; in addition, modules 11, 12 have biasing nodes 24, receiving biasing voltage V.sub.G. Biasing voltage V.sub.G is here generated by temperature compensating circuit 52 aimed at generating biasing voltage V.sub.G so that dependency of the sensitivity of the envelope detector 50 on temperature is minimized. Specifically, temperature compensating circuit 52 is a Proportional-To-Absolute-Temperature (PTAT) circuit comprising here five PTAT transistors 55-59, of MOS type, working in subthreshold condition. PTAT transistors 55-59 are also called first, second, third, fourth and fifth PTAT transistors 55-59, hereinafter.

[0050] In detail, first PTAT transistor 55, here of PMOS type, is diode-connected and is coupled between a supply line 60 at voltage V.sub.DD and a first PTAT node 61. Therefore, first PTAT transistor 55 has its source terminal coupled to supply line 60 and its gate and drain terminals coupled together at first PTAT node 61. Second PTAT transistor 56, here also of PMOS type, is mirror-like coupled to first PTAT transistor 55. Thus, second PTAT transistor 56 has its source terminal coupled to supply line 60 and its gate terminal coupled to the gate terminal of first PTAT transistor 55. The drain terminal of second PTAT transistor 56 forms a PTAT output node 65, which is coupled to biasing nodes 24 of envelope extracting portion 51.

[0051] Third PTAT transistor 57, here of NMOS type, has its drain terminal coupled to first PTAT node 61; its source terminal coupled to a second PTAT node 62 through a resistor 63, and its gate terminal coupled to PTAT output node 65.

[0052] Fourth PTAT transistor 58, here of NMOS type, is diode-connected (mirror-like with third PTAT transistor 57) and is coupled between PTAT output node 65 and second PTAT node 62. Therefore, fourth PTAT transistor 58 has its gate and drain terminals coupled together and to PTAT output node 65 and its source terminal coupled to second PTAT node 62.

[0053] Fifth PTAT transistor 59, here of is of NMOS type, is also diode-connected and coupled between second PTAT node 62 and ground. Thus, it has its gate and drain terminals coupled together and to second PTAT node 62 and its source terminal coupled to ground.

[0054] A first filtering capacitor 66 is coupled between PTAT output node 65 and a reference potential line (here, ground) for preventing input voltage V.sub.in from entering the temperature compensating circuit 52. A second filtering capacitor 67 is coupled between the gate terminal of fifth PTAT transistor 59 (second connection node 19 of first module 11) and ground, also for preventing filtered input voltage V.sub.in from entering the temperature compensating circuit 52. A further filtering capacitor (not shown) may be coupled between the gates of first and second PTAT transistors 55, 56 and ground, to filter noise of the current mirror. First and second filtering capacitors 66, 67 may be much bigger than third coupling capacitors 28.

[0055] As indicated above and demonstrated below, by configuring the temperature compensating circuit 52 so that PTAT transistors 55-59 operate in subthreshold condition, biasing voltage VG generated by temperature compensating circuit 52 allows sensitivity of the envelope detector 50 to be temperature compensated.

[0056] In fact, as discussed in the above-mentioned article by V. Mangal et al., the sensitivity of envelope extracting portion 51 strongly depends on the input resistance R.sub.in seen between signal input nodes 23 and ground. In particular, input resistance R.sub.in is strongly dependent on the drain-to-source resistance R.sub.DS of extraction transistors 13, 14 (and precisely, of all drain-to-source resistances R.sub.DS of extraction transistors 13, 14 of all modules 11, 12). Thus, according to this disclosure, in order to have a temperature-compensated sensitivity of the envelope detector 50, temperature compensating circuit 52 generates a biasing voltage V.sub.G causing the drain-to-source resistance R.sub.DS of extraction transistors 13, 14 to be substantially unaffected by temperature, as demonstrated by the equations below.

[0057] As known in the art, conductance g.sub.DS (which is the inverse of its drain-to-source resistance R.sub.DS) of a transistor, such as extraction transistor 13, 14, may be calculated as follows.

[00001]$g_{\mathrm{DS}}=\frac{\partial I_D}{\partial V_{DS}},$

where I.sub.D is the drain current and V.sub.DS is the drain to source voltage of extraction transistor 13, 14.

[0058] As known, see, e.g., Analysis and Design of Analog Integrated Circuits, Gray, Hurst, Lewis, Meyer, 5th Edition, for a transistor working in subthreshold condition, drain current I.sub.D is:

[00002]$\begin{array}{cc}{I}_D=\frac{W}{L}{I}_T{e}^{\frac{V_{\mathrm{GS}}-V_{\mathrm{th}}}{n{V}_T}}\left[1-e^{-\frac{V_{DS}}{V_T}}\right],& \left(1\right)\end{array}$

Where, W and L are the width and length of the gate regions of extraction transistors 13, 14; I.sub.T is the reverse saturation current of a PN junction, referred to extraction transistors 13, 14, related to the used technology; V.sub.GS is the gate to source voltage of extraction transistors 13, 14; V.sub.th is the MOS threshold voltage; V.sub.T is the thermal voltage; and n is slope factor, given by n=1+C.sub.dep/C.sub.ox (wherein C.sub.dep is the capacitance of the depletion layer and C.sub.ox is the capacitance of the oxide layer of extraction transistors 13, 14).

[0059] By differentiating equation (1) and considering that, for a transistor working in subthreshold condition with a small V.sub.DS (drain to source voltage, tending to zero), it is possible to use the following approximation:

[00003]$e^{-\frac{V_{DS}}{V_T}}\sim 1$

with a few calculations, the equation (2) below may be obtained:

[00004]$\begin{array}{cc}\begin{array}{cc}{g}_{DS}=\frac{1}{V_T}\left(\frac{W}{L}\right)I_T& e^{-\frac{V_{\mathrm{th}}}{n{V}_T}}{e}^{\frac{V_{\mathrm{GS}}}{n{V}_T}},\end{array}& \left(2\right)\end{array}$

which, for transistors 13, 14 may be written as:

[00005]$\begin{array}{cc}\begin{array}{ccc}{g}_{\mathrm{DS},\mathrm{Tr}}=\frac{1}{V_T}{I}_{T,\mathrm{Tr}}& {e^{-\frac{V_{\mathrm{th},\mathrm{Tr}}}{n{V}_T}}\left(\frac{W}{L}\right)}_{Tr}& e^{\frac{V_{\mathrm{GS},\mathrm{Tr}}}{n{V}_T}}\end{array}.& \left(3\right)\end{array}$

[0060] Since fourth PTAT transistor 58 is coupled in parallel to the gate-to-source junction of extraction transistors 13, 14, their gate-to-source voltages V.sub.GS are the same, thus:

V.sub.GS,Tr=V.sub.GS,58.

[0061] In addition, by neglecting any differences between the drain-to-source voltages of fourth PTAT transistor 58 and extraction transistors 13, 14, their reverse saturation currents I.sub.T and their threshold voltages V.sub.th are also the same:

I.sub.T,Tr˜I.sub.T,58; V.sub.th,Tr˜V.sub.th,58   (4)

Considering the above, equation (3) may be rewritten as:

[00006]$\begin{array}{cc}\begin{array}{ccc}{g}_{\mathrm{DS},\mathrm{Tr}}=\frac{1}{V_T}{I}_{T,58}& {e^{-\frac{V_{\mathrm{th},58}}{n{V}_T}}\left(\frac{W}{L}\right)}_{Tr}& e^{\frac{V_{\mathrm{GS},58}}{n{V}_T}}\end{array}& \left(5\right)\end{array}$

by defining:

[00007]$\begin{array}{cc}\begin{array}{cc}{I}_{S,58}=I_{T,58}& e^{-\frac{V_{\mathrm{th},58}}{n{V}_T}},\end{array}& \left(6\right)\end{array}$

where I.sub.T,58 is the reverse saturation current of PN junction for fourth PTAT transistor 58, related to the used technology, equation (5) may thus be rewritten as:

[00008]$\begin{array}{cc}\begin{array}{ccc}{g}_{\mathrm{DS},\mathrm{Tr}}=\frac{1}{V_T}{I}_{S,58}& {\left(\frac{W}{L}\right)}_{Tr}& e^{\frac{V_{\mathrm{GS},58}}{n{V}_T}}.\end{array}& \left(7\right)\end{array}$

In addition:

[00009]$\begin{array}{cc}{I}_{DC,58}={I_{S,58}\left(\frac{W}{L}\right)}_{58}{e}^{\frac{V_{\mathrm{GS},58}}{n{V}_T}},& \left(8\right)\end{array}$

where I.sub.DC,58 is the direct current through fourth PTAT transistor 58 (bias current of fourth PTAT transistor 58).

[0062] Substituting equation (8) in equation (7), we obtain:

[00010]$\begin{array}{cc}{g}_{\mathrm{DS},\mathrm{Tr}}\sim \frac{I_{DC,58}}{V_T}\frac{{\left(W/L\right)}_{\mathrm{Tr}}}{{\left(W/L\right)}_{58}}.& \left(9\right).\end{array}$

[0063] On the other hand, third PTAT transistor 57 and fourth PTAT transistor 58 are mirror-like coupled and thus have same drain currents:

I.sub.D,57=I.sub.D,58

and work in a subthreshold condition. By dimensioning PTAT transistors 57, 58 so that:

[00011]${\left(\frac{W}{L}\right)}_{57}={N\left(\frac{W}{L}\right)}_{58}.$

It may be demonstrated that

[00012]$\begin{array}{cc}{I}_{57}=\frac{{nV}_T\ln N}{R},& \left(10\right)\end{array}$

where R is the resistance of resistor 63. By inserting equation (10) into equation (9), we have:

[00013]$\begin{array}{cc}{I}_{DC,58}\sim \frac{{nV}_T\ln \frac{{\left(W/L\right)}_{57}}{{\left(W/L\right)}_{58}}}{R}& \left(11\right)\end{array}$

so that equation (9) becomes:

[00014]$\begin{array}{cc}{g}_{DS}\sim \frac{n\ln \frac{{\left(W/L\right)}_{57}}{{\left(W/L\right)}_{58}}}{R}\frac{{\left(W/L\right)}_{\mathrm{Tr}}}{{\left(W/L\right)}_{58}},& \left(12\right)\end{array}$

which is dependent on only geometrical factors and is thus independent from temperature. Accordingly, the input resistance and thus the sensitivity of the envelope detector 50 is temperature compensated by temperature compensating circuit 52.

[0064] FIG. 5 shows an envelope detector 50′ that is noise-compensated.

[0065] In fact, the addition of temperature compensating circuit 52 may cause introduction of noise, both thermal and flicker, that may be propagated through envelope extracting portion 51. To solve this issue, envelope detector 50′ of FIG. 5 uses a differential approach. To this end, envelope detector 50′ again includes an envelope extracting portion, here identified by reference number 51′, and a temperature compensating circuit, here identified by reference number 52′. Temperature compensating circuit 52′ is exactly the same as temperature compensating circuit 52 of FIG. 4.

[0066] Envelope extracting portion 51′ comprises a first and a second branch 70, 71, wherein one of them (here, first branch 70) is exactly the same as the envelope extracting portion 51 of FIG. 4 and the other (here, second branch 71) has exchanged connections to cause an opposite current flow.

[0067] Therefore, since the basic elements of envelope detector 50′ of FIG. 5 are the same as for the envelope detector 50 of FIG. 4, they have been identified by the same reference numbers and the following description regards only the different connections of the second branch 70.

[0068] It is worth noting that envelope extracting portion 51′ of FIG. 5 shows a single module 11 for the first branch 70. Also here, more than one module may be provided; in this case, further modules, such as second module 12 in FIG. 4 may be cascade connected. In this case, first and second branch 70, 71 have the same number of modules 11, 12. Analogously, the second branch 71 of envelope extracting portion 51′ has a single module, indicated as module in, but further modules, with exactly the same structure as module 111, may be cascade connected to module in.

[0069] In FIG. 5, the extraction transistors of module 111, to be compared with first and second extraction transistors 13, 14, are indicated as third and fourth extraction transistors 113, 114. In detail, the third extraction transistor 113 (coupled with input voltage V.sub.in) of the second branch 70 is here coupled to first connection node 16 and to PTAT output node 65 with its drain terminal; to the intermediate node 17 with its source terminal; and to the first control node 18 with its gate terminal. The fourth extraction transistor 114 of the second branch 70 is coupled to intermediate node 17 with its drain terminal; to second connection node 19 with its source terminal; and to biasing input 24 with its gate terminal.

[0070] First and second branches 70, 71 work independently and generate opposite output voltages V.sub.o1 and V.sub.o2 at output 21 and 21′, respectively, where the noise generated by temperature compensating circuit 52 is propagated in the same way in both branches 70, 71. Therefore, the noise generated by temperature compensating circuit 52 (seen as common-mode) is cancelled out at the differential output V.sub.o1−V.sub.o2.

[0071] In various embodiments, the total signal-to-noise ratio SNR of envelope detector 50′ does not change from single ended solution of envelope detector 50 of FIG. 4. In particular, assuming that both the single-ended envelope detector 50 of FIG. 4 and the differential-ended envelope detector 50′ of FIG. 5 are coupled to a respective amplifier (single-input amplifier and differential amplifier, respectively, neither shown), the two amplifiers have the same noise factor. In fact:

[00015]$N{F}_{\mathrm{DIFF}}=1+\frac{4}{\frac{\mathrm{gm}}{2}{\left(2k\right)}^2{R}_{\mathrm{in}}}=N{F}_{SE},$

where NF.sub.DIFF is the noise factor of the differential amplifier coupled to outputs 21, 21′ of envelope detector 50′ of FIG. 5, g.sub.m is the transconductance of the amplifiers (which are biased with a same current; wherein the amplifiers are assumed to produce no flicker noise); k is the number of extraction transistors 13, 14; 113, 114 in each branch 70, 71, R.sub.in is the input resistance seen between signal input nodes 23 and ground and NF.sub.SE is the noise factor of a single-input amplifier coupled to output 21 of envelope detector 50 of FIG. 4.

[0072] In addition to the SNR, the envelope extracting portion 51′ of FIG. 5 does not negatively affect power consumption or delay.

[0073] The advantages of embodiment envelope detectors are clear from the description above. For example, some embodiment envelope detector advantageously have a sensitivity with minimized dependence on temperature. Furthermore, the disclosed embodiments do not require any external DC voltages; the extraction transistors are self-biased through the temperature compensating circuit 52, thus limiting power consumption. The differential approach prevents sensitivity degradation due to the noise of temperature compensating circuit 52.

[0074] Finally, it is clear that numerous variations and modifications may be made to the device described and illustrated herein, all falling within the scope of the invention as defined in the attached claims. For example, the single-ended solution may use the connection structure of second branch 71 of FIG. 5, instead of the one shown in FIG. 4.

[0075] In addition, fifth PTAT transistor 59 may be replaced by a plurality of diode-connected transistors, series-coupled on top of each other, depending on the DC output voltage V.sub.o, V.sub.o1, V.sub.o2 desired by a subsequent amplifier to operate correctly. The current mirror formed by first and second PTAT transistors 55, 56 may include a higher number of transistors and/or be implemented by a more complicated mirror topology; bipolar transistors may be used instead of MOS transistors; and/or resistor 63 may be implemented through an MOS transistor.

[0076] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.