DIFFERENTIAL AMPLIFIER CAPABLE OF OFFSET COMPENSATION OF DIFFERENTIAL OUTPUT SIGNAL AND ADAPTIVE CONTINUOUS-TIME LINEAR EQUALIZER INCLUDING THE SAME

Abstract

An adaptive continuous-time linear equalizer (CTLE) includes a CTLE cell including input terminals and output terminals, a low-pass filter configured to respectively output low-band differential signals obtained by respectively low-pass filtering differential output signals, and an error amplifier configured to amplify a difference between the low-band differential signals and output the difference as a control voltage. The CTLE cell includes first and second transistors each including an input terminal and an output terminal and an offset compensator configured to adjust a potential difference between a supply voltage source and the output terminal according to the control voltage.

Claims

1. A continuous-time linear equalizer (CTLE) cell constituting a CTLE that equalizes differential input signals and generates differential output signals, the CTLE cell comprising: a first transistor comprising a first input terminal to which a first of the differential input signals is applied and a first output terminal configured to output a first of the differential output signals; a second transistor comprising a second input terminal to which a second of the differential input signals is applied and a second output terminal configured to output a second of the differential output signals; and an offset compensator configured to adjust a potential difference between a supply voltage source and the second output terminal according to a control voltage corresponding to a difference between low-band differential signals obtained by respectively low-pass filtering the differential output signals.

2. The CTLE cell of claim 1, wherein the offset compensator comprises: a third transistor comprising a gate to which the control voltage is applied and a source electrically connected to the supply voltage source; a first resistor configured to electrically connect a drain of the third transistor to the second output terminal; and a second resistor configured to electrically connect the source of the third transistor to the second output terminal.

3. The CTLE cell of claim 2, wherein the third transistor comprises a P-MOSFET.

4. The CTLE cell of claim 2, wherein: the first transistor comprises a drain corresponding to the first output terminal and a gate corresponding to the first input terminal; and the second transistor comprises a drain corresponding to the second output terminal and a gate corresponding to the second input terminal.

5. The CTLE cell of claim 4, further comprising a third resistor configured to electrically connect the supply voltage source to the first output terminal.

6. The CTLE cell of claim 1, wherein the offset compensator is configured to adjust a potential difference between the supply voltage source and the second output terminal according to an average of the control voltage.

7. A continuous-time linear equalizer (CTLE) that equalizes differential input signals and respectively generates differential output signals, the CTLE comprising: a CTLE cell comprising input terminals to which the differential input signals are respectively applied and output terminals configured to respectively output the differential output signals; a low-pass filter configured to respectively output low-band differential signals obtained by respectively low-pass filtering the differential output signals; and an error amplifier configured to amplify a difference between the low-band differential signals and output the amplified difference as a control voltage, wherein: the CTLE cell comprises: a first transistor comprising a first input terminal of the input terminals and a first output terminal of the output terminals; a second transistor comprising a second input terminal of the input terminals and a second output terminal of the output terminals; and an offset compensator configured to adjust a potential difference between a supply voltage source and the second output terminal according to the control voltage.

8. The CTLE of claim 7, wherein the offset compensator comprises: a third transistor comprising a gate to which the control voltage is applied and a source electrically connected to the supply voltage source; a first resistor configured to electrically connect a drain of the third transistor to the second output terminal; and a second resistor configured to electrically connect the source of the third transistor to the second output terminal.

9. The CTLE of claim 8, wherein the third transistor comprises a P-MOSFET.

10. The CTLE of claim 8, wherein: the first transistor comprises a drain corresponding to the first output terminal and a gate corresponding to the first input terminal, and the second transistor comprises a drain corresponding to the second output terminal and a gate corresponding to the second input terminal.

11. The CTLE of claim 10, wherein the CTLE cell further comprises a third resistor configured to electrically connect the supply voltage source to the first output terminal.

12. The CTLE of claim 11, further comprising: a capacitor connected between the supply voltage source and an output terminal of the error amplifier and configured to generate an average of the control voltage, wherein the offset compensator is configured to adjust a potential difference between the supply voltage source and the second output terminal according to an average of the control voltage.

13. A continuous-time linear equalizer (CTLE) comprising: a low-pass filter that applies low-pass filtering to equalized differential signals to generate low-band differential signals; an error amplifier that amplifies a difference between complementary signals of the low-band differential signals to generate an amplified difference; and a CTLE cell that equalizes differential input signals to generate the equalized differential signals, the CTLE cell comprising an offset compensator that varies a potential between a supply voltage and one of complementary signals of the equalized differential signals based on the amplified difference.

14. The CTLE of claim 13, further comprising: an integrator that integrates the amplified difference to generate a control signal, wherein the offset compensator varies the potential between the supply voltage and the one complementary signal of the equalized differential signals in response to the control signal.

15. The CTLE of claim 14, wherein the offset compensator increases the potential between the supply voltage and the one complementary signal of the equalized differential signals as the control signal increases.

16. The CTLE of claim 15, wherein the offset compensator increases the potential between the supply voltage and the one complementary signal of the equalized differential signals by increasing an effective resistance between the supply voltage and the one complementary signal of the equalized differential signals.

17. The CTLE of claim 14, wherein the offset compensator decreases the potential between the supply voltage and the one complementary signal of the equalized differential signals as the control signal decreases.

18. The CTLE of claim 17, wherein the offset compensator decreases the potential between the supply voltage and the one complementary signal of the equalized differential signals by decreasing an effective resistance between the supply voltage and the one complementary signal of the equalized differential signals.

19. The CTLE of claim 14, wherein the offset compensator comprises: a transistor having a gate that receives an average value of the control signal and a source electrically connected to the supply voltage; a first resistor electrically connecting a drain of the transistor to an output terminal of the CTLE cell that conveys the one complementary signal of the equalized differential signals; and a second resistor configured to electrically connect the source of the transistor to the output terminal.

20. The CTLE of claim 19, wherein the transistor is a P-MOSFET.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Embodiments of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

[0046] FIG. 1 is a schematic diagram illustrating distortion of a waveform according to the related art;

[0047] FIG. 2 is a block diagram illustrating a continuous-time linear equalizer (CTLE) according to the related art;

[0048] FIG. 3 is a circuit diagram illustrating a differential amplifier of a CTLE cell constituting the CTLE of FIG. 2 according to the related art;

[0049] FIGS. 4A and 4B are waveform diagrams illustrating differential output signals of an ideal CTLE cell and a difference therebetween according to the related art;

[0050] FIGS. 5A and 5B are waveform diagrams illustrating differential output signals of an ideal CTLE cell in which an offset is generated and a difference therebetween according to the related art;

[0051] FIG. 6 is a block diagram illustrating a CTLE according to the disclosure;

[0052] FIG. 7 is a circuit diagram illustrating a differential amplifier of a CTLE cell constituting the CTLE of FIG. 6 according to the disclosure; and

[0053] FIG. 8 is a graph illustrating a resistance value of an offset compensator according to a control voltage.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] Hereinafter, a differential amplifier capable of offset compensation of a differential output signal and an adaptive continuous-time linear equalizer (CTLE) including the same according to the disclosure will be described in detail with reference to the accompanying drawings.

[0055] FIG. 6 is a block diagram illustrating a CTLE 2000 according to the disclosure.

[0056] Referring to FIG. 6, the CTLE 2000 according to the disclosure includes a CTLE cell 100, a low pass filter (LPF) 500, and an error amplifier 600. In addition, the CTLE 2000 according to the disclosure may further include a comparator 200, high pass filters 300a and 300b, a rectified error amplifier 400, and a capacitor C.sub.A.

[0057] The CTLE cell 100 equalizes the differential input signals RX.sub.1 and RX.sub.2 to output the differential output signals EQ.sub.1 and EQ.sub.2, respectively.

[0058] Specifically, the CTLE cell 100 includes the input terminals IN.sub.1 and IN.sub.2 to which the differential input signals RX.sub.1 and RX.sub.2 are respectively applied and the output terminals OUT.sub.1 and OUT.sub.2 outputting the differential output signals EQ.sub.1 and EQ.sub.2, respectively.

[0059] Hereinafter, the CTLE cell 100 according to the disclosure will be described in detail with reference to FIG. 7.

[0060] FIG. 7 is a diagram illustrating the CTLE cell 100 according to the disclosure. The CTLE cell 100 includes the differential amplifier shown in FIG. 6.

[0061] Referring to FIG. 7, the differential amplifier constituting the CTLE cell 100 includes the first transistor TR.sub.1, the second transistor TR.sub.2, and an offset compensator OFFSET_COMP. In addition, the differential amplifier constituting the CTLE cell 100 includes the resistor R.sub.D1, the resistor R.sub.D2, the resistor R.sub.s, and the capacitor Cs.

[0062] As shown in FIG. 7, the resistor R.sub.D1 and the first transistor TR.sub.1 are connected in series between a supply voltage source VDD and a current source I.sub.SS. That is, the resistor R.sub.D1 electrically connects the supply voltage source VDD to a drain D.sub.1 of the first transistor TR.sub.1.

[0063] Also, the offset compensator OFFSET_COMP and the second transistor TR.sub.2 are connected in series between the supply voltage source VDD and the current source I.sub.SS. That is, the offset compensator OFFSET_COMP electrically connects the supply voltage source VDD to a drain D.sub.2 of the second transistor TR.sub.2.

[0064] In addition, the resistor R.sub.s and the capacitor Cs are connected in parallel between a source S.sub.1 of the first transistor TR.sub.1 and a source S.sub.2 of the second transistor TR.sub.2.

[0065] Hereinafter, each element of the differential amplifier shown in FIG. 7 will be described in more detail.

[0066] The first transistor TR.sub.1 includes a gate G.sub.1 corresponding to the input terminal IN.sub.1 to which the differential input signal RX.sub.1 is applied, the drain D.sub.1 corresponding to the output terminal OUT.sub.1 outputting the differential output signal EQ.sub.1, and the source S.sub.1 electrically connected to the resistor R.sub.s and the capacitor Cs connected in parallel. The drain D.sub.1 is electrically connected to the supply voltage source VDD through the resistor R.sub.D1.

[0067] The second transistor TR.sub.2 includes a gate G.sub.2 corresponding to the input terminal IN.sub.2 to which the differential input signal RX.sub.2 is applied, the drain D.sub.2 corresponding to the output terminal OUT.sub.2 outputting the differential output signal EQ.sub.2, and the source S.sub.2 electrically connected to the resistor R.sub.s and the capacitor Cs connected in parallel. The drain D.sub.2 is electrically connected to the supply voltage source VDD through the offset compensator OFFSET_COMP.

[0068] The offset compensator OFFSET_COMP adjusts a potential difference between the supply voltage source VDD and the output terminal OUT.sub.2 according to a control voltage R.sub.CTRL corresponding to a difference between low-band differential signals EQ.sub.1L and EQ.sub.2L. Here, the control voltage R.sub.CTRL amplifies the difference between the low-band differential signals EQ.sub.1L and EQ.sub.2L obtained by low-pass filtering the differential output signals EQ.sub.1 and EQ.sub.2.

[0069] The control voltage R.sub.CTRL is expressed by Equation 3 below.

R.sub.CTRL=A.sub.2×(EQ.sub.2L−EQ.sub.1L)+R.sub.CTRL.DC  [Equation 3]

[0070] Here, A.sub.2 denotes a gain and R.sub.CTRL.DC is a DC bias value of R.sub.CTRL.

[0071] Specifically, the offset compensator OFFSET_COMP includes a third transistor TR.sub.3, a resistor R.sub.DS, and a resistor R.sub.D2.

[0072] The third transistor TR.sub.3 includes a gate G.sub.3 to which the control voltage R.sub.CTRL is applied, a source S.sub.3 electrically connected to the supply voltage source VDD, and a drain D.sub.3 electrically connected to the resistor R.sub.DS. Here, the third transistor TR.sub.3 may include a P-MOSFET.

[0073] The resistor R.sub.DS electrically connects the drain D.sub.3 of the third transistor TR.sub.3 to the output terminal OUT.sub.2.

[0074] The resistor R.sub.D2 electrically connects the source S.sub.3 of the third transistor TR.sub.3 to the output terminal OUT.sub.2.

[0075] The resistor R.sub.s is electrically connected to the source S.sub.1 of the first transistor TR.sub.1 and the source S.sub.2 of the second transistor TR.sub.2 and controls the low frequency amplification gain of the CTLE cell 100.

[0076] The capacitor Cs is connected in parallel to the resistor R.sub.s to adjust the high frequency amplification gain of the CTLE cell 100.

[0077] Referring back to FIG. 6, the LPF 500 of the CTLE 2000 according to the disclosure low-pass filters the differential output signals EQ.sub.1 and EQ.sub.2 output by the CTLE cell 100, respectively, and outputs the low-band differential signals EQ.sub.1L and EQ.sub.2L, respectively.

[0078] The error amplifier 600 amplifies a difference between the low-pass differential signals EQ.sub.1L and EQ.sub.2L output by the LPF 500 and outputs the difference as the control voltage R.sub.CTRL.

[0079] The control voltage R.sub.CTRL output by the error amplifier 600 is applied (as affected by capacitor C.sub.A) to the gate G.sub.3 of the third transistor TR.sub.3 included in the CTLE cell 100.

[0080] The capacitor C.sub.A generates an average value of the control voltage R.sub.CTRL provided as feedback to the CTLE cell 100. The capacitor C.sub.A is connected between the supply voltage source VDD and an output terminal of the error amplifier 600. The resistance value of the offset compensator OFFSET_COMP may be adjusted using the control voltage R.sub.CTRL obtained with respect to each pulse of the low-band differential signals EQ.sub.1L and EQ.sub.2L but may be adjusted according to the average of the control voltage R.sub.CTRL. In this case, the resistance value of the offset compensator OFFSET_COMP is adjusted to be relatively smoother.

[0081] The comparator 200, the high-pass filters 300a and 300b, and the rectified error amplifier 400 are the same as the comparator 20, the high-pass filters 30a and 30b, and the rectified error amplifier 40 of the CTLE of the related art described with reference to FIG. 2, and thus, detailed descriptions thereof will be omitted.

[0082] Hereinafter, the operation of the CTLE according to the disclosure will be described in detail with reference to FIGS. 6 to 8. However, the adjustment of the capacitor Cs and the resistor R.sub.s is the same as that of the CTLE cell described with reference to FIG. 3, and thus, detailed descriptions thereof will be omitted.

[0083] First, the differential input signals RX.sub.1 and RX.sub.2 are respectively applied through the input terminals IN.sub.1 and IN.sub.2 and the CTLE cell 100 equalizes the differential input signals RX.sub.1 and RX.sub.2 according to an initial value and outputs the differential output signals EQ.sub.1 and EQ.sub.2 respectively through the output terminals OUT.sub.1 and OUT.sub.2.

[0084] The differential output signals EQ.sub.1 and EQ.sub.2 output by the CTLE cell 100 are filtered by the LPF 500. The low-pass differential signals EQ.sub.1L and EQ.sub.2L output by the LPF 500 are applied to the error amplifier 600.

[0085] The error amplifier 600 amplifies a difference between the low-band differential signals EQ.sub.1L and EQ.sub.2L, outputs the difference as the control voltage R.sub.CTRL, and applies the control voltage R.sub.CTRL to the CTLE cell 100.

[0086] The third transistor TR.sub.3 may be a P-MOSFET.

[0087] When the control voltage R.sub.CTRL is applied to the gate G.sub.3, a resistance value between the source S.sub.3 and the drain D.sub.3 of the third transistor TR.sub.3 changes. For example, it is supposed that a voltage firstly supplied by a supply voltage source is 1V. When the control voltage R.sub.CTRL is equal to or greater than 0.8V, because the third transistor TR.sub.3 is completely turned off, a substantially open circuit is formed between the source S.sub.3 and the drain D.sub.3. When the control voltage R.sub.CTRL is equal to or smaller than 0.3V, because the third transistor TR.sub.3 is completely turned on, a substantially short circuit is formed between the source S.sub.3 and the drain D.sub.3. When the control voltage R.sub.CTRL is between 0.3V and 0.8V, the resistance value between the source S.sub.3 and the drain D.sub.3 increases as the control voltage R.sub.CTRL increases.

[0088] FIG. 8 is a graph illustrating a resistance value of the offset compensator OFFSET_COMP according to the control voltage R.sub.CTRL.

[0089] Referring to FIG. 8, a resistance value R.sub.EQ of the offset compensator OFFSET_COMP changes according to the control voltage R.sub.CTRL.

[0090] Specifically, the resistance value R.sub.EQ increases as the control voltage R.sub.CTRL increases and decreases as the control voltage R.sub.CTRL decreases.

[0091] That is, the resistance value R.sub.EQ of the offset compensator OFFSET_COMP is closer to the resistance value of the resistor R.sub.D2 as the control voltage R.sub.CTRL increases and is closer to R.sub.D2∥R.sub.DS as the control voltage R.sub.CTRL decreases.

[0092] In other words, the maximum value of the resistance value R.sub.EQ of the offset compensator OFFSET_COMP is R.sub.D2, and the minimum value is

[00001]$R_{D2}.Math.R_{\mathrm{DS}}\left(=\frac{R_{D2}{R}_{DS}}{R_{D2}+R_{DS}}\right).$

This is expressed as Equation 4 below.

[00002]$\begin{array}{cc}\frac{R_{D2}{R}_{DS}}{R_{D2}+R_{DS}}\le R_{EQ}\le R_{D2}& \left[\mathrm{Equation}4\right]\end{array}$

[0093] According to Equation 4, the resistance value R.sub.EQ of the offset compensator OFFSET_COMP increases or decreases according to a change in the control voltage R.sub.CTRL.

[0094] When the resistance value R.sub.EQ changes, the voltage applied to the offset compensator OFFSET_COMP changes, and as a result, a potential difference between the supply voltage source VDD and the output terminal OUT.sub.2, that is, the potential (or voltage) of the output terminal OUT.sub.2, changes.

[0095] This will be described in more detail below.

[0096] First, for convenience of explanation, it is supposed that the optimum value of the control voltage R.sub.CTRL is the optimum control voltage R.sub.CTRL.OPT=0.6V, and in this regard, the resistance value R.sub.EQ of the offset compensator OFFSET_COMP is the optimum resistance value R.sub.EQ.OPT=95Ω.

[0097] First, when the control voltage R.sub.CTRL=0.7V, R.sub.EQ>R.sub.EQ.OPT (see FIG. 8).

[0098] Therefore, a voltage drop by the offset compensator OFFSET_COMP is greater than a voltage drop when the optimum control voltage R.sub.CTRL.OPT=0.6V and the potential of the output terminal OUT.sub.2 is lower than a voltage drop when the optimum control voltage R.sub.CTRL.OPT=0.6V.

[0099] Accordingly, EQ.sub.1L>EQ.sub.2L is established between the low-pass differential signals EQ.sub.1L and EQ.sub.2L output by the LPF 500 and the control voltage R.sub.CTRL output by the error amplifier 600 decreases.

[0100] Second, when the control voltage R.sub.CTRL=0.5V, R.sub.EQ<R.sub.EQ.OPT (see FIG. 8).

[0101] Therefore, the voltage drop by the offset compensator OFFSET_COMP is less than the voltage drop when the optimum control voltage R.sub.CTRL.OPT=0.6V and the potential of the output terminal OUT.sub.2 is lower than a voltage drop when the optimum control voltage R.sub.CTRL.OPT=0.6V.

[0102] Accordingly, EQ.sub.1L<EQ.sub.2L is established between the low-pass differential signals EQ.sub.1L and EQ.sub.2L output by the LPF 500 and the control voltage R.sub.CTRL output by the error amplifier 600 increases.

[0103] The above-described process is repeated until the control voltage R.sub.CTRL converges to the optimum control voltage R.sub.CTRL.OPT. That is, when the control voltage R.sub.CTRL is less than the optimal control voltage R.sub.CTRL.OPT, the process of increasing the control voltage R.sub.CTRL occurs and when the control voltage R.sub.CTRL is greater than the optimal control voltage R.sub.CTRL.OPT, the process of decreasing the control voltage R.sub.CTRL occurs so that the control voltage R.sub.CTRL converges to the optimum control voltage R.sub.CTRL.OPT.

[0104] While the disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.