OSCILLATION CIRCUIT AND ELECTRONIC DEVICE

Abstract

An oscillation circuit includes an oscillator (X.sub.1), capacitors (C.sub.1, C.sub.2) connected between two terminals of the oscillator (X.sub.1), and an amplification circuit (A.sub.1) having an input terminal connected to a connecting point between the oscillator (X.sub.1) and the capacitor (C.sub.1) and an output terminal connected to a connecting point between the capacitor (C.sub.1) and the capacitor (C.sub.2). The amplification circuit (A.sub.1) includes an n-type transistor (M.sub.1) and a p-type transistor (M.sub.2) respectively having source terminals, the connecting point of which is connected to the output terminal of the amplification circuit (A.sub.1), a p-type transistor (M.sub.3) configured to connect a gate terminal of the n-type transistor (M.sub.1) to a power supply terminal at the time of an oscillation stop and disconnect the power supply terminal and the gate terminal of the n-type transistor (M.sub.1) at the time of an oscillation operation, and an n-type transistor (M.sub.4) configured to connect a gate terminal of the p-type transistor (M.sub.2) to ground at the time of the oscillation stop and disconnect a ground terminal and the gate terminal of the p-type transistor (M.sub.2) at the time of the oscillation operation. It is possible to implement low power consumption and high-speed oscillation activation of the oscillation circuit.

Claims

1. An oscillation circuit comprising: a power supply terminal; a ground terminal; an oscillator; and an amplification circuit including a first capacitor and a second capacitor series-connected between two terminals of the oscillator, an input terminal connected to the oscillator and the first capacitor, an output terminal connected to the first capacitor and the second capacitor, a first n-type transistor having a source terminal connected to the output terminal, a drain terminal connected to a first switch connected to the power supply terminal, and a gate terminal connected to the input terminal, a first p-type transistor having a source terminal connected to the output terminal, a drain terminal connected to a second switch connected to the ground terminal, and a gate terminal connected to the input terminal, a second p-type transistor having a source terminal connected to the power supply terminal, a drain terminal connected to the input terminal and the gate terminal of the first n-type transistor, and a second n-type transistor having a source terminal connected to the ground terminal and a drain terminal connected to the input terminal and the gate terminal of the first p-type transistor.

2. The oscillation circuit according to claim 1, wherein the first switch connects the power supply terminal and the drain terminal of the first n-type transistor at the time of an oscillation operation, and disconnects the power supply terminal and the drain terminal of the first n-type transistor at the time of an oscillation stop, the second switch connects the ground terminal and the drain terminal of the first p-type transistor at the time of the oscillation operation, and disconnects the ground terminal and the drain terminal of the first p-type transistor at the time of the oscillation stop, the gate terminal of the second p-type transistor is controlled to be turned off at the time of the oscillation operation and to be turned on at the time of the oscillation stop, and the gate terminal of the second n-type transistor is controlled to be turned off at the time of the oscillation operation and to be turned on at the time of the oscillation stop.

3. An electronic device comprising an oscillation circuit defined in claim 1.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a circuit diagram showing the arrangement of a conventional Colpitts oscillation circuit;

[0014] FIG. 2 is a circuit diagram showing the arrangement of an oscillation circuit according to an embodiment of the present invention;

[0015] FIG. 3 shows equivalent circuit diagrams of a PMOS transistor and an NMOS transistor for bias in the oscillation circuit when the transistors are OFF according to the embodiment of the present invention;

[0016] FIG. 4 is a timing chart showing the variation range of an output voltage of the oscillation circuit, and the variation ranges of the gate voltages and gate-source voltages of the PMOS transistor and NMOS transistor for bias according to the embodiment of the present invention;

[0017] FIG. 5 is a timing chart showing an oscillation waveform after oscillation activation in the oscillation circuit according to the embodiment of the present invention;

[0018] FIG. 6 is a timing chart showing the waveforms of the currents of the transistors and output voltages in the conventional Pierce oscillation circuit and the oscillation circuit according to the embodiment of the present invention;

[0019] FIG. 7 is a circuit diagram showing the arrangement of an inverter of the Pierce oscillation circuit;

[0020] FIG. 8 is a graph showing the phase noise characteristics of the conventional Pierce oscillation circuit and the oscillation circuit according to the embodiment of the present invention;

[0021] FIG. 9 shows equivalent circuit diagrams of an oscillator using langasite-type piezoelectric single crystal and a crystal oscillator; and

[0022] FIG. 10 is a circuit diagram showing the arrangement of the conventional Pierce oscillation circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[0023] An embodiment of the present invention will be described below with reference to the accompanying drawings. First, FIG. 1 shows the arrangement of a Colpitts oscillation circuit based on which an oscillation circuit according to this embodiment is obtained. The Colpitts oscillation circuit includes an oscillator X.sub.1, an amplification circuit A.sub.1, and two capacitors C.sub.1 and C.sub.2.

[0024] <Arrangement of Oscillation Circuit>

[0025] Based on the Colpitts oscillation circuit, FIG. 2 shows the oscillation circuit of this embodiment in which the power consumption of an amplifier is reduced. The oscillation circuit of this embodiment includes a power supply terminal (not shown), a ground terminal (not shown), an oscillator X.sub.1, capacitors C.sub.1 and C.sub.2 series-connected between two terminals of the oscillator X.sub.1, and an amplification circuit A.sub.1 that has an input terminal connected to the connecting point between the oscillator X.sub.1 and the capacitor C.sub.1 and an output terminal connected to the connecting point between the capacitors C.sub.1 and C.sub.2. Note that the power supply terminal is a terminal connected to the high-potential side (for example, V.sub.dd) of a power supply voltage, and the ground terminal is a terminal connected to the low-potential side (for example, earth potential or V.sub.ss) of the power supply voltage.

[0026] The amplification circuit A.sub.1 includes an NMOS transistor (n-type transistor) M.sub.1 having a source terminal connected to the output terminal of the amplification circuit A.sub.1, a PMOS transistor (p-type transistor) M.sub.2 having a source terminal connected to the output terminal of the amplification circuit A.sub.1, a PMOS transistor M.sub.3 having a gate terminal to which a bias reset signal BR is input, a drain terminal connected to the gate terminal of the NMOS transistor M.sub.1, and a source terminal connected to the power supply voltage V.sub.dd, an NMOS transistor M.sub.4 having a gate terminal to which a bias reset signal BR is input, a drain terminal connected to the gate terminal of the PMOS transistor M.sub.2, and a source terminal connected to ground, a capacitor C.sub.cut1 having one terminal connected to the input terminal of the amplification circuit A.sub.1 and the other terminal connected to the gate terminal of the NMOS transistor M.sub.1, a capacitor C.sub.cut2 having one terminal connected to the input terminal of the amplification circuit A.sub.1 and the other terminal connected to the gate terminal of the PMOS transistor M.sub.2, a switch SW.sub.1 that disconnects the power supply voltage V.sub.dd and the drain terminal of the NMOS transistor M.sub.1 at the time of an oscillation stop and connects the power supply voltage V.sub.dd and the drain terminal of the NMOS transistor M.sub.1 at the time of an oscillation operation, and a switch SW.sub.2 that disconnects ground and the drain terminal of the PMOS transistor M.sub.2 at the time of the oscillation stop and connects ground and the drain terminal of the PMOS transistor M.sub.2 at the time of the oscillation operation.

[0027] The capacitor C.sub.cut1 is connected between the input terminal of the amplification circuit and the gate terminal of the NMOS transistor M.sub.1 and the drain terminal of the PMOS transistor M.sub.3. The capacitor C.sub.cut2 is connected between the input terminal of the amplification circuit and the gate terminal of the PMOS transistor M.sub.2 and the drain terminal of the NMOS transistor M.sub.4. The capacitors C.sub.cut1 and C.sub.cut2 function as circuit parts that remove noise such as DC components. As the n-type transistors (M.sub.1 and M.sub.4) and the p-type transistors (M.sub.2 and M.sub.3), CMOS transistors may be used.

[0028] In the specification and claims of the present application, a case in which it is apparently described that “A and B are connected” includes a case in which A and B are electrically connected, a case in which A and B are functionally connected, and a case in which A and B are directly connected. In this case, A and B are target objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, and the like). Therefore, a predetermined connection relationship is not limited to, for example, a connection relationship shown in a diagram or expressed in words, and includes a connection relationship other than the connection relationship shown in the diagram or expressed in words.

[0029] As a case in which A and B are electrically connected, for example, one or more elements (for example, a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, and the like) that can electrically connect A and B may be connected between A and B.

[0030] If an n-type or p-type transistor is used as a switch, the switch includes an input terminal (one of a source terminal and a drain terminal), an output terminal (one of the source terminal and the drain terminal), and a terminal (gate terminal) for controlling conduction. By applying a positive or negative voltage to the gate terminal, the transistor can control a current flowing from the input terminal to the output terminal, thereby functioning as a switch. If the switch is turned on, the two terminals of the switch are connected. On the other hand, if the switch is turned off, the two terminals of the switch are disconnected.

[0031] The NMOS transistor M.sub.1 and the PMOS transistor M.sub.2 form a cascode-connected complementary pair. The gate terminal of the NMOS transistor M.sub.1 is connected to the power supply voltage V.sub.dd when the PMOS transistor M.sub.3 is turned on, and is fed back with the output voltage of the amplification circuit A.sub.1 via the capacitors C.sub.1 and C.sub.cut1. The gate terminal of the PMOS transistor M.sub.2 is connected to ground when the NMOS transistor M.sub.4 is turned on, and is fed back with the output voltage of the amplification circuit A.sub.1 via the capacitors C.sub.1 and C.sub.cut2.

[0032] <Operation of Oscillation Circuit>

[0033] The bias reset signals BR and BR respectively input to the gate terminals of the PMOS transistor M.sub.3 and the NMOS transistor M.sub.4, and an oscillation permission signal EN for controlling the switches SW.sub.1 and SW.sub.2 can be implemented by providing, in or outside the oscillation circuit, a control circuit (not shown) that controls the start and stop operations of oscillation and an oscillation operation.

[0034] Since high transconductance gm is required to activate oscillation, the bias reset signal BR is at high at the time of the oscillation stop and the bias reset signal BR is at low at the time of the oscillation stop. Therefore, the PMOS transistor M.sub.3 and the NMOS transistor M.sub.4 are turned on and the NMOS transistor M.sub.1 and the PMOS transistor M.sub.2 are turned on.

[0035] Furthermore, at the time of the oscillation stop, the oscillation permission signal EN is set at low, and the switches SW.sub.1 and SW.sub.2 are turned off. As the switches SW.sub.1 and SW.sub.2, for example, NMOS transistors can be used. The oscillation permission signal EN is input to the gate terminal of the NMOS transistor serving as the switch SW.sub.1 to connect the drain terminal to the power supply voltage V.sub.dd and connect the source terminal to the drain terminal of the NMOS transistor M.sub.1. The oscillation permission signal EN is input to the gate terminal of the NMOS transistor serving as the switch SW.sub.2 to connect the drain terminal to the drain terminal of the PMOS transistor M.sub.2 and connect the source terminal to ground.

[0036] On the other hand, at the time of the oscillation operation, the bias reset signal BR is set at low and the bias reset signal BR is set at high. Therefore, the PMOS transistor M.sub.3 and the NMOS transistor M.sub.4 are turned off. In the OFF state, the PMOS transistor M.sub.3 is represented by an equivalent circuit formed from a diode D.sub.1 and a resistor R.sub.1, as shown in (A) of FIG. 3. The NMOS transistor M.sub.4 is represented by an equivalent circuit formed from a diode D.sub.2 and a resistor R.sub.2, as shown in (B) of FIG. 3.

[0037] That is, if the PMOS transistor M.sub.3 is in the OFF state, a gate voltage V.sub.gN of the NMOS transistor M.sub.1 is biased by a voltage caused by the leakage current of the diode D.sub.1. Similarly, if the NMOS transistor M.sub.4 is in the OFF state, a gate voltage V.sub.gP of the PMOS transistor M.sub.2 is biased by a voltage caused by the leakage current of the diode D.sub.2. The resistor R.sub.1 indicates a resistance component through which the leakage current of the diode D.sub.1 flows, and the resistor R.sub.2 indicates a resistance component through which the leakage current of the diode D.sub.2 flows.

[0038] By exemplifying the PMOS transistor M.sub.3, the leakage current of the diode D.sub.1 always operates to raise the gate voltage V.sub.gN of the NMOS transistor M.sub.1 and maintain oscillation. If oscillation starts by a large signal, the gate terminal of the NMOS transistor M.sub.1 is dynamically biased by feedback from the output of the amplification circuit A.sub.1 via the capacitors C.sub.1 and C.sub.cut1. However, the gate voltage V.sub.gN of the NMOS transistor M.sub.1 is clamped, by the diode D.sub.1, at a voltage value whose highest value is V.sub.th3 V.sub.dd (V.sub.th3 is the threshold voltage of the PMOS transistor M.sub.3). Similarly, the gate voltage V.sub.gP of the PMOS transistor M.sub.2 is clamped, by the diode D.sub.2, at a voltage value whose lowest value is −V.sub.th4 (V.sub.th4 is the threshold voltage of the NMOS transistor M.sub.4).

[0039] FIG. 4 shows the variation ranges of an output voltage V.sub.out of the oscillation circuit (amplification circuit A.sub.1), the gate voltage V.sub.gN of the NMOS transistor M.sub.1, the gate voltage V.sub.gP of the PMOS transistor M.sub.2, a gate-source voltage V.sub.gsN of the NMOS transistor M.sub.1, and a gate-source voltage V.sub.gsP of the PMOS transistor M.sub.2 at the time of the oscillation operation.

[0040] Furthermore, at the time of the oscillation operation, the oscillation permission signal EN is set at high and the switches SW.sub.1 and SW.sub.2 are turned on.

[0041] <Oscillation Waveform of Oscillation Circuit>

[0042] FIG. 5 shows an oscillation waveform after oscillation activation. I.sub.N represents a source current of the NMOS transistor M.sub.1, and I.sub.P represents a source current of the PMOS transistor M.sub.2. It is known that the gate-source voltage V.sub.gsN of the NMOS transistor M.sub.1 and the gate-source voltage V.sub.gsP of the PMOS transistor M.sub.2 start from a relatively high voltage at the time of oscillation activation (when the bias reset signal BR and the oscillation permission signal EN are set at high), and then falls within the voltage range of −V.sub.th4 to V.sub.th3 in an oscillation stationary state. Therefore, the current flowing through each of the NMOS transistor M.sub.1 and the PMOS transistor M.sub.2 is very small in the stationary state.

[0043] FIG. 6 is a timing chart showing the waveforms of the output voltage V.sub.out of the oscillation circuit, the source current I.sub.N of the NMOS transistor M.sub.1, and the source current I.sub.P of the PMOS transistor M.sub.2 in the oscillation stationary state. In this example, C.sub.1=18 pF and C.sub.2=9 pF are set, and the capacity of a load connected to the output terminal of the oscillation circuit (amplification circuit A.sub.1) is set to 6 pF.

[0044] For the purpose of comparison, FIG. 6 shows an output voltage V.sub.out10 of the Pierce oscillation circuit and currents I.sub.N10 and I.sub.P10 of the transistors of the inverter when the capacitors C.sub.1 and C.sub.2 and the capacity of a load are set to the same values as in this embodiment. The inverter INV.sub.10 of the Pierce oscillation circuit shown in FIG. 10 includes a PMOS transistor M.sub.5 and an NMOS transistor M.sub.6, as shown in FIG. 7.

[0045] As is apparent from FIG. 6, as compared with the currents I.sub.N10 and I.sub.P10 of the Pierce oscillation circuit, the currents I.sub.N and I.sub.P of the oscillation circuit of this embodiment flow only at a timing when the output voltage V.sub.out becomes an extreme value, and current amounts are very small. Therefore, according to this embodiment, it is known that it is possible to largely reduce the power consumption in the oscillation state. In fact, it is known that a power consumption Pss in the stationary state of the oscillation circuit of this embodiment is as low as about 1/10 of the power consumption in the stationary state of the Pierce oscillation circuit.

[0046] <Phase Noise Characteristic of Oscillation Circuit>

[0047] FIG. 8 shows the phase noise characteristics of the conventional Pierce oscillation circuit and the oscillation circuit of this embodiment. In FIG. 8, N.sub.0 represents the phase noise of the Pierce oscillation circuit, and N.sub.1 represents the phase noise of the oscillation circuit of this embodiment. As compared with the conventional Pierce oscillation circuit, it is known that the phase noise as important oscillation circuit performance for a communication device is improved by about 9 dB within the range of the offset frequency up to 100 Hz with respect to the fundamental frequency of the oscillation circuit. As described above, it is apparent that the use of the oscillation circuit of this embodiment contributes to reduction of the phase noise of the communication device.

[0048] <Oscillator in Oscillation Circuit>

[0049] As the oscillator X.sub.1 of the oscillation circuit, various oscillators such as a crystal oscillator and an oscillator using langasite-type piezoelectric single crystal can be used. To activate oscillation of the oscillation circuit at higher speed to implement lower oscillation activation energy, in this embodiment, an oscillator using langasite-type piezoelectric single crystal is used as the oscillator X.sub.1. There are various langasite-type piezoelectric single crystals but an oscillator using Ca.sub.3TaGa.sub.3Si.sub.2O.sub.14 (to be referred to as CTGS) is used in an experiment. Langasite is a single crystal expressed by a chemical composition such as Ca.sub.3NbGa.sub.3Si.sub.2O.sub.14 (to be referred to as CHGS), Ca.sub.3Ta(Ga.sub.1-XAl.sub.X).sub.3Si.sub.2O.sub.14 (to be referred to as CTGAS), or Ca.sub.3Nb(Ga.sub.1-XAl.sub.X).sub.3Si.sub.2O.sub.14 (to be referred to as CNGAS) in addition to CTGS, and the langasite-type piezoelectric single crystal is not limited to the oscillator using CTGS. In FIG. 9, (A) and (B) show equivalent circuits of a CTGS oscillator used and the crystal oscillator (quartz) used for reference. (B) of FIG. 9 shows an equivalent circuit diagram obtained by simplifying (A) of FIG. 9. The left side of a line 100 in (A) or (B) of FIG. 9 shows the equivalent circuit of the oscillator and the right side of the line 100 shows the equivalent circuit of the oscillation circuit. Table 1 shows a capacitor C.sub.L, an inductance L.sub.m, a resistor R.sub.m, a capacitor C.sub.m, a resistor R.sub.x, and a Q value.

TABLE-US-00001 TABLE 1 CTGS Quartz C.sub.L (pF) 6 (C.sub.1 = 18 pF, C.sub.2 = 9 pF) L.sub.m (mH) 1.45 13.2 R.sub.m (Ω) 6.2 16.9 C.sub.m (fF) 30 3.6 R.sub.x (Ω) 10.2 24.3 Q 35267 117607

[0050] As a result of the experiment using the CTGS oscillator as the oscillator X.sub.1, an oscillation activation time Ts of the oscillation circuit of this embodiment was 0.37 ms and oscillation activation energy Es was 30 nJ. On the other hand, if the crystal oscillator was used as the oscillator X.sub.1, the oscillation activation time Ts of the oscillation circuit shown in FIG. 2 was 3.6 ms and the oscillation activation energy Es was 320 nj.

[0051] Therefore, if the CTGS oscillator was used as the oscillator X.sub.1, it was confirmed that, as compared with a case in which the crystal oscillator was used, it was possible to implement the oscillation activation time earlier by about one order of magnitude, and also reduce the oscillation activation energy by about one order of magnitude, thereby implementing low power consumption.

[0052] As described above, according to this embodiment, it is possible to implement high-speed oscillation activation, and implement an oscillation circuit of low power consumption in the oscillation stationary state after oscillation activation.

[0053] Therefore, if the oscillation circuit of this embodiment is applied to, for example, an electronic device such as a mobile phone or an IoT device, this can contribute to implementation of an electronic device of low power consumption.

INDUSTRIAL APPLICABILITY

[0054] The present invention is applicable to an oscillation circuit used in a small electronic device. Explanation of the Reference Numerals and Signs [0055] A.sub.1 . . . amplification circuit, C.sub.1, C.sub.2, C.sub.cut1, C.sub.cut2 . . . capacitor, M.sub.1-M.sub.4 . . . transistor, SW.sub.1, SW.sub.2 . . . switch, X.sub.1 . . . oscillator