PACKAGE STRUCTURE OF EMBEDDED POWER MODULE WITH LOW PARASITIC INDUCTANCE AND HIGH HEAT DISSIPATION EFFICIENCY

Abstract

A package structure of an embedded power module includes a top insulation layer, a top metal pattern layer, a solder layer, a device layer, a bottom metal pattern layer and a bottom insulation layer sequentially arranged from top to bottom. The device layer includes at least two MOSFET bare dies and several metal connection blocks, and is filled with insulation filler to isolate the MOSFET bare dies and the metal connection blocks from each other. The drain electrodes of the bare dies are connected with the top metal pattern layer through the solder layer, and the source electrodes and the gate electrodes of the bare dies are electrically connected to the bottom metal pattern layer, respectively. The upper and lower surfaces of the metal connection blocks are electrically connected to the top metal pattern layer and the bottom metal pattern layer, respectively.

Claims

1. A package structure of an embedded power module with low parasitic inductance and high heat dissipation efficiency, comprising a top insulation layer (9), a top metal pattern layer (4), a solder layer (6), a device layer (8), a bottom metal pattern layer (5) and a bottom insulation layer (10) sequentially arranged from top to bottom, wherein both the top insulation layer (9) and the bottom insulation layer (10) have partial openings, and exposed parts of the top metal pattern layer (4) and the bottom metal pattern layer (5) at opening positions serve as a top electrode terminal (11) and a bottom electrode terminal (12), respectively; the device layer (8) comprises at least two MOSFET bare dies (2) and several metal connection blocks (3), and is filled with insulation filler between the MOSFET bare dies (2) and the metal connection blocks (3) to isolate the MOSFET bare dies (2) and the metal connection blocks (3) from each other; and drain electrodes (203) of the MOSFET bare dies (2) are connected with the top metal pattern layer (4) through the solder layer (6), source electrodes (201) and gate electrodes (202) of the MOSFET bare dies (2) are electrically connected to the bottom metal pattern layer (5), respectively, and upper and lower surfaces of the metal connection blocks (3) are electrically connected to the top metal pattern layer (4) and the bottom metal pattern layer (5), respectively.

2. The package structure of the embedded power module according to claim 1, wherein the insulation filler is further extended and filled between the MOSFET bare dies (2) and the bottom metal pattern layer (5), and blind vias are provided in the insulation filler between the MOSFET bare dies (2) and the bottom metal pattern layer (5), a metal plating layer is provided on an inner wall of each blind via, and the source electrodes (201) and the gate electrodes (202) are electrically connected to the bottom metal pattern layer (5) through the metal plating layer, respectively.

3. The package structure of the embedded power module according to claim 1, wherein the insulation filler is further extended and filled between the metal connection blocks (3) and the bottom metal pattern layer (5), and blind vias are provided in the insulation filler between the metal connection blocks (3) and the bottom metal pattern layer (5), a metal plating layer is provided on an inner wall of each blind via, and the metal connection blocks (3) are electrically connected to the bottom metal pattern layer (5) through the metal plating layer.

4. The package structure of the embedded power module according to claim 1, wherein the upper surfaces of the metal connection blocks (3) are connected to the top metal pattern layer (4) through the solder layer (6).

5. The package structure of the embedded power module according to claim 1, wherein the metal connection blocks (3) have the same height as that of the MOSFET bare dies (2).

6. The package structure of the embedded power module according to claim 1, wherein the insulation filler is further extended and filled to a vacant portion of the top metal pattern layer (4), and is connected with a lower surface of the top insulation layer (9); or the insulation filler is further extended and filled to a vacant portion of the bottom metal pattern layer (5), and is connected with an upper surface of the bottom insulation layer (10).

7. The package structure of the embedded power module according to claim 1, wherein the top insulation layer (9) is further extended downward and filled to a vacant portion of the top metal pattern layer (4), and is connected with the insulation filler in the device layer (8); or the bottom insulation layer (10) is further extended upward and filled to a vacant portion of the top metal pattern layer (4), and is connected with the insulation filler in the device layer (8).

8. The package structure of the embedded power module according to claim 1, wherein the power module entirely presents a multi-layer plate-like structure.

9. The package structure of the embedded power module according to claim 1, wherein there is a plurality of top electrode terminals (11) and bottom electrode terminals (12), respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a typical package structure based on substrate and bonding wire in the prior art.

[0027] FIG. 2 is a schematic diagram of the package structure of an embedded power module with low parasitic inductance and efficient thermal management according to an embodiment of the application.

[0028] The description of reference signs in FIG. 1: 1-1 Packaging material; 1-2 Power bare die; 1-3 Bonding wire; 1-4 Direct Bonding Copper (DBC) substrate; 1-5 Heat dissipation substrate; 1-6 DBC solder; and 1-7 Solder.

[0029] The description of reference signs in FIG. 2: 1 Power module; 2 MOSFET bare die; 201 Source electrode; 202 Gate electrode; 203 Drain electrode; 3 Metal connection block; 301 Upper surface of the metal connection block; 302 Lower surface of the metal connection block; 4 Top metal pattern layer; 5 Bottom metal pattern layer; 6 Solder layer; 7 Blind via; 8 Device layer; 9 Top insulation layer; 10 Bottom insulation layer; 11 Top electrode terminal; and 12 Bottom electrode terminal.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The specific implementations of the application will be further described in detail below in combination with the accompanying drawings. In order to illustrate the technical solutions in the embodiments of the application more clearly, the following briefly introduces the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. The specific embodiments are to further describe the application, but the protection scope of the application is not limited thereto.

[0031] As shown in FIG. 2, the package structure of an embedded power module of the application comprises a top insulation layer 9, a top metal pattern layer 4, a solder layer 6, a device layer 8, a bottom metal pattern layer 5 and a bottom insulation layer 10 sequentially arranged from top to bottom. Thus, this power module entirely presents a multi-layer plate-like structure. Both the top insulation layer 9 and the bottom insulation layer 10 have partial openings. The exposed parts of the top metal pattern layer 4 and the bottom metal pattern layer 5 at the opening positions serve as a top electrode terminal 11 and a bottom electrode terminal 12, respectively.

[0032] The device layer 8 comprises at least two MOSFET bare dies 2 and several metal connection blocks 3, and is filled with insulation filler to isolate the MOSFET bare dies 2 and the metal connection blocks 3 from each other. The drain electrodes 203 of the MOSFET bare dies 2 are connected with the top metal pattern layer 4 through the solder layer 6, and the source electrodes 201 and gate electrodes 202 are electrically connected to the bottom metal pattern layer 5, respectively. The upper and lower surfaces of the metal connection blocks 3 are electrically connected to the top metal pattern layer 4 and the bottom metal pattern layer 5, respectively. The insulation filler is further extended and filled between the MOSFET bare dies 2 and the bottom metal pattern layer 5, and blind vias are provided in the insulation filler between the MOSFET bare dies 2 and the bottom metal pattern layer 5. A metal plating layer is provided on the inner wall of each blind via. The source electrodes 201 and the gate electrodes 202 are electrically connected to the bottom metal pattern layer 5 through the metal plating layer, respectively. Similarly, the insulation filler is further extended and filled between the metal connection blocks 3 and the bottom metal pattern layer 5, and blind vias are provided in the insulation filler between the metal connection blocks 3 and the bottom metal pattern layer 5. A metal plating layer is provided on the inner wall of each blind via. The metal connection blocks 3 are electrically connected to the bottom metal pattern layer 5 through the metal plating layer. The upper surfaces of the metal connection blocks 3 are connected to the top metal pattern layer 4 through the solder layer 6. The metal connection blocks 3 optionally have the same height as that of the MOSFET bare dies 2, and thus, the blind vias below the metal connection blocks 3 and the MOSFET bare dies 2 also have the same height.

[0033] Optionally, the insulation filler is further extended and filled to a vacant portion of the top metal pattern layer 4, and is connected with the lower surface of the top insulation layer 9 (as shown in FIG. 2). Alternatively, the insulation filler is further extended and filled to a vacant portion of the bottom metal layer 5, and is connected with the upper surface of the bottom insulation layer 10 (not shown in the figure). Optionally, the top insulation layer 9 is further extended downward and filled to the vacant portion of the top metal pattern layer 4, and is connected with the insulation filler in the device layer 8 (not shown in the figure). Alternatively, the bottom insulation layer 10 is further extended upward and filled to the vacant portion of the top metal pattern layer 4, and is connected with the insulation filler in the device layer 8 (as shown in FIG. 2).

[0034] In the application, the MOSFET bare dies 2 are provided with the source electrodes 201 and the gate electrodes 202 downwardly on the front side, and are provided with the drain electrodes 203 upwardly on the back side. As the prior art, optional example products include CREE's CPM2-1200-0080B, etc. Multiple MOSFET bare dies 2 can form different electrical connection relationships to realize the corresponding functions of the power module. The front faces of the MOSFET bare dies 2 are downward, which can shorten the distance from the source electrodes 201 and the gate electrodes 202 of the dies to the bottom electrode terminals of the power module and the circuit board, thus reducing the parasitic inductance of drive circuit. Specifically, the MOSFET bare dies 2 can be silicon-based or silicon-carbide-based, or other power bare dies such as IGBTs, etc.

[0035] The top metal pattern layer 4 and the bottom metal pattern layer 5 refer to patterned metal layers for electrical connection. The specific patterns are determined according to the function of the module and the connection mode of the dies. The example in FIG. 2 is a half-bridge structure composed of two dies connected in series.

[0036] The metal connection blocks 3 are used to realize the electrical connection between the top metal pattern layer 4 and the bottom metal pattern layer 5, and the specific arrangement mode depends on the function of the power module, which can be flexibly changed according to different functions. For example, the role of the “separately arranged” metal connection block 3 on the right side in FIG. 2 is to lead the electrode on the right lower surface of the power module to the terminal on the top surface to integrate components such as decoupling capacitor, etc. The upper surface and the lower surface of the metal connection block 3 are connected to the metal pattern layer respectively by solder layer and the metal plating layer poured into the blind via, which is determined by the packaging implementation process.

[0037] There may be a plurality of top electrode terminals 11 and bottom electrode terminals 12, respectively, and the specific number and position are determined according to the function and requirements of the power module, which are not limited in the application. In FIG. 2, a half-bridge module composed of two MOSFETs connected in series is taken as an example. Five electrode terminals of the half-bridge structure are arranged at the bottom, and two electrode terminals are arranged at the top to connect an absorption capacitor. In actual production, the specific positions of the terminals are determined by the design scheme of the metal pattern layer. As an application example, the bottom electrode terminals 12 can be used to connect to the circuit board, and the top electrode terminals 11 can be connected to a component such as a decoupling capacitor, etc.

[0038] Exemplary description of the manufacturing process of the package structure of an embedded power module in the application is indicated as follows: [0039] 1. producing the top metal pattern layer on a carrier; [0040] 2. welding bare dies and metal connection blocks; [0041] 3. laminating the plastic packaging material and the bottom metal pattern layer; [0042] 4. drilling vias and metalizing the blind vias; and [0043] 5. removing the carrier, processing top and bottom insulation layers, and treating the terminal surfaces.

[0044] In summary, through the chip-embedded design of double-sided heat dissipation without bonding wires or lead wires, the application realizes a package structure with low parasitic inductance and high heat dissipation efficiency by applying micro-vias, electroplating and other PCB processes, which has characteristics of low cost, high flexibility and easy development. The power module based on the embedded package has the advantages of small size, light weight, no bonding wire, double-sided heat dissipation, etc., and is a solution with great development potential.