SELF-DRIVEN ACTIVE CLAMP CIRCUIT

Abstract

A self-driven active clamp circuit applied to a flyback converter having a transformer and a switch has a clamp switch and a resistor. The clamp switch is connected between a first capacitor and a second capacitor in series. Another terminal of the first capacitor is connected to a first terminal of a primary-side winding of the transformer. Another terminal of the second capacitor is connected to a second terminal of the primary-side winding of the transformer and the switch of the flyback converter. A terminal of the resistor is connected to a control terminal of the clamp switch. Another terminal of the resistor is connected to the second terminal of the primary-side winding of the transformer and the switch of the flyback converter.

Claims

1. A self-driven active clamp circuit applied to a flyback converter having a transformer and a switch, the self-driven active clamp circuit comprising: a clamp switch connected between a first capacitor and a second capacitor in series, wherein another terminal of the first capacitor is connected to a first terminal of a primary-side winding of the transformer, and another terminal of the second capacitor is connected to a second terminal of the primary-side winding of the transformer and the switch of the flyback converter; and a resistor, wherein a terminal of the resistor is connected to a control terminal of the clamp switch, and another terminal of the resistor is connected to the second terminal of the primary-side winding of the transformer and the switch of the flyback converter.

2. The circuit as claimed in claim 1 further comprising a diode, wherein an anode of the diode is connected to the control terminal of the clamp switch, and a cathode of the diode is connected to the second terminal of the primary-side winding of the transformer and the switch of the flyback converter.

3. The circuit as claimed in claim 1, wherein the clamp switch is a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate as the control terminal, a drain connected to the first capacitor, and a source connected to the second capacitor.

4. The circuit as claimed in claim 2, wherein the clamp switch is a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate as the control terminal, a drain connected to the first capacitor, and a source connected to the second capacitor.

5. The circuit as claimed in claim 3, wherein only when a voltage between the drain and the source of the clamp switch is reduced to 0 V, a gate voltage of the clamp switch rises to turn on the clamp switch, such that the clamp switch operates in zero voltage switching (ZVS).

6. The circuit as claimed in claim 4, wherein only when a voltage between the drain and the source of the clamp switch is reduced to 0V, a gate voltage of the clamp switch rises to turn on the clamp switch, such that the clamp switch operates in zero voltage switching (ZVS).

7. The circuit as claimed in claim 5, wherein when the clamp switch is turned on, the primary-side winding of the transformer generates an inverse voltage to charge the first capacitor and the second capacitor.

8. The circuit as claimed in claim 6, wherein when the clamp switch is turned on, the primary-side winding of the transformer generates an inverse voltage to charge the first capacitor and the second capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a circuit diagram of the self-driven active clamp circuit of the present invention applied to the flyback converter;

[0011] FIG. 2A is a waveform diagram of the output voltage Vo as shown in FIG. 1;

[0012] FIG. 2B is a waveform diagram of the voltage V.sub.C2 between two terminals of the second capacitor (C2) as shown in FIG. 1;

[0013] FIG. 2C is a waveform diagram of the voltage V.sub.C1, between two terminals of the first capacitor (C1) as shown in FIG. 1;

[0014] FIG. 2D is a waveform diagram of the drain-source voltage V.sub.Q2-DS of the clamp switch (Q2) as shown in FIG. 1;

[0015] FIG. 2E is a waveform diagram of the voltage V.sub.Q2-G between the gate and the source of the clamp switch (Q2) as shown in FIG. 1;

[0016] FIG. 2F is a waveform diagram of the drain-source voltage V.sub.Q1-DS of the switch (Q1) of the flyback converter as shown in FIG. 1;

[0017] FIG. 2G is a waveform diagram of the gate voltage V.sub.Q1-G of the switch (Q1) of the flyback converter as shown in FIG. 1;

[0018] FIG. 2H is a waveform diagram of the voltage V.sub.p between two terminals of the primary-side winding of the transformer as shown in FIG. 1;

[0019] FIG. 3 is a circuit diagram of the operation that the switch (Q1) is turned off and the clamp switch (Q2) is turned on; and

[0020] FIG. 4 is a circuit diagram of the operation that the switch (Q1) is turned on and the clamp switch (Q2) is turned off.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT(S)

[0021] The self-driven active clamp circuit of the present invention is applied to a flyback converter. FIG. 1 shows an example of a circuit configuration of the flyback converter. Working principle of the flyback converter is not the focus in the present invention, so is introduced briefly as follows.

[0022] At first, fundamental components of the flyback converter may comprise a transformer 20, a switch Q1, and an output circuit 30. A primary-side winding 21 of the transformer 20 is connected to the switch Q1 in series. The switch Q1 may be formed by a metal-oxide-semiconductor field-effect transistor (hereinafter referred to as MOSFET), having a gate connected to a pulse width modulation (hereinafter referred to as PWM) controller 40. The PWM controller 40 outputs a PWM signal to the switch Q1 to turn on or off the switch Q1. A drain of the switch Q1 is connected to the primary-side winding 21. The source of the switch Q1 is grounded. A terminal of the primary-side 21 of the transformer 20 is connected to an input power Vin, such as a DC (direct current) power as an example herein.

[0023] The output circuit 30 is connected to a secondary-side winding 22 of the transformer 20 and comprises two output terminals 31, 32 to be connected to load(s). The primary-side winding 21 and the secondary-side winding 22 of the transformer 20 are not connected to a same ground.

[0024] The self-driven active clamp circuit 10 of the present invention is connected to the transformer 20 and the switch Q1 and comprises a clamp switch Q2, a first capacitor C1, a second capacitor C2, and a resistor R. The self-driven active clamp circuit 10 of the present invention may further comprise a diode D. A terminal of the clamp switch Q2 is connected to the first capacitor C1. Another terminal of the clamp switch Q2 is connected to the second capacitor C2. Hence, the clamp switch Q2 is connected between the first capacitor C1 and a second capacitor C2 in series. A control terminal of the clamp switch Q2 is connected to the resistor R and the diode D.

[0025] In an embodiment of the present invention, the clamp switch Q2 is formed by a MOSFET. A parasitic capacitance C3 exists between a gate and a source of the clamp switch Q2. The gate of the clamp switch Q2 is deemed as the above-mentioned control terminal. A drain and the source of the clamp switch Q2 are connected to the first capacitor C1 and the second capacitor C2 respectively.

[0026] A terminal of the first capacitor C1 is connected to the primary-side winding 21 of the transformer 20 and the input power Vin. Another terminal of the first capacitor C1 is connected to the drain of the clamp switch Q2.

[0027] A terminal of the second capacitor C2 is connected to the source of the clamp switch Q2. Another terminal of the second capacitor C2 is connected to the drain of the switch Q1 of the flyback converter.

[0028] An anode of the diode D is connected to the gate of the clamp switch Q2. A cathode of the diode D is connected to the drain of the switch Q1 of the flyback converter. The resistor R is connected to two terminals of the diode D, such that the resistor R is connected across the diode D.

[0029] With reference to the voltage waveform diagrams shown in FIGS. 2A to 2H, the vertical axis represents voltage value (V), and the horizontal axis represents the time. The circuit operation of the present invention is described as follows.

[0030] Time segment t0: Under the boundary current mode (BCM), the voltage V.sub.P on the primary-side winding 21 of the transformer 20 is gradually reduced to 0 V The voltage V.sub.C2 on the second capacitor C2 is reduced to 0V, too. The parasitic capacitance C3 is discharged via the diode D, such that the voltage on the parasitic capacitance C3 is reduced to 0 V rapidly. As a result, the gate voltage of the clamp switch Q2 will be lower than a turn-on threshold voltage (Vgs-th). Then, the clamp switch Q2 is turned off. At that time, as the voltage reduction of the voltage V.sub.P on the primary-side winding 21, the drain-source voltage V.sub.Q1-DS of the switch Q1 is reduced to 0 V from a prior high voltage level, and a signal of high is sent to the gate voltage V.sub.Q1-G of the switch Q1. Control mode of the switch Q1 reaches a zero voltage switching (ZVS).

[0031] Time segment t1: The switch Q1 is turned on. In other words, the switch Q1 changes to on-state from a prior off-state. The voltage V.sub.P of the primary-side winding 21 rises to Vin from 0 V

[0032] Time segment t2: When gate voltage V.sub.Q1-G of the switch Q1 is reduced to a low voltage level (such as the low level in the PWM signal), the switch Q1 changes to the off-state. Because the switch Q1 changes to off-state from a prior on-state, an inverse voltage is generated on the primary-side winding 21 of the transformer 20, so the voltage V.sub.P of the primary-side winding 21 shown in FIG. 2H is negative. With reference to FIG. 3, the voltage V.sub.P charges the second capacitor C2 and the first capacitor C1 via a body diode of the clamp switch Q2. Within the charging duration of the second capacitor C2 and the first capacitor C1, the second capacitor C2 and the first capacitor C1 also absorb the current spike induced by the leakage inductance of the transformer 20. Then, the second capacitor C2 and the first capacitor C1 will be gradually charged to reach a steady state. Since the body diode is turned on previously, the drain-source voltage V.sub.Q2-DS of the clamp switch Q2 is reduced to be lower than approximation of the forward voltage (VF) of the body diode before a driving signal is sent to the clamp switch Q2, as shown in the position “S” of FIGS. 2B and 2C. Within the charging duration of the second capacitor C2, as shown in FIG. 3, the second capacitor C2 may charge the parasitic capacitance C3 via the resistor R. When the voltage on the parasitic capacitance C3 reaches the turn-on threshold voltage (Vgs-th) of the clamp switch Q2, the clamp switch Q2 changes to on-state to implement the zero voltage switching (ZVS) and absorb the current spike. The resistor R plays a role of a delay component. While charging and based on the delay time determined by the resistor R and the parasitic capacitance C3, the gate voltage V.sub.Q2-G of the clamp switch Q2 reaches the turn-on threshold voltage (Vgs-th) only when the drain-source voltage V.sub.Q2-DS is reduced to approximation of the forward voltage (VF) of the body diode, such that drive and control for the clamp switch Q2 can meet the requirement of the zero voltage switching.

[0033] Time segment t3: Under the boundary current mode (BCM), the voltage V.sub.P of the primary-side winding 21 of the transformer 20 will be reduced to 0V gradually. The voltage V.sub.C2 on the two terminals of the second capacitor C2 is reduced to 0 V, too. The parasitic capacitance C3 is discharged via the diode D, such that the voltage on the parasitic capacitance C3 is reduced to 0 V rapidly. As a result, the gate voltage of the clamp switch Q2 will be lower than the turn-on threshold voltage (Vgs-th). Then, the clamp switch Q2 is turned off. Because the clamp switch Q2 can be turned off rapidly, the switching loss of the clamp switch Q2 will be decreased. The drain-source voltage V.sub.Q1-DS of the switch Q1 is gradually reduced to 0 V from a prior high voltage level, and the operation within the time segment t0 will be repeated.

[0034] Time segment t4: The switch Q1 is turned on. As shown in FIG. 4, the operation within the time segment t1 will be repeated.

[0035] In a preferred embodiment, in order to minimize the on-state resistance (R.sub.DS) and the loss of the clamp switch Q2 while turned on, an ideal driving voltage around 10V as an example should be retained on the gate of the clamp switch Q2. In general, the sum of voltage of the first capacitor C1 and the second capacitor C2, represented as V.sub.C1+V.sub.C2, is approximately equal to the voltage V.sub.P of the primary-side winding 21 while discharging, wherein V.sub.P is as the inverse voltage. At that time, the relationship regarding the voltage VP, a winding number N.sub.P of the primary-side winding 21, and a winding number Ns of the secondary-side winding 22 may be represented as V.sub.P=[(N.sub.S/N.sub.P)×V.sub.O]. In the design practice for the converter, the voltage V.sub.P is limited by the winding ratio and fails to approximate the ideal driving voltage of 10 V due to various demands for input/output. In the present invention, by selecting a proper capacitance value for the second capacitor C2, the ideal driving voltage approximating 10 V will be obtained on the second capacitor C2 according to the voltage division by the first capacitor C1 and the second capacitor C2. The gate of the clamp switch Q2 will have a proper driving voltage. Then the present invention will achieve the ideal driving effect.

[0036] In conclusion, the self-driven active clamp circuit of the present invention can autonomously turn on and off the clamp switch Q2 according to the polarity of VP of the primary-side winding 21 without adding further more driving circuits. The self-driven active clamp circuit of the present invention not only absorbs the current spike, but also provides the gate of the clamp switch Q2 with the ideal driving voltage by the properly selected second capacitor C2, such that the clamp switch Q2 while turned on may have lower on-state resistance (R.sub.DS), and the loss will be reduced.