METHOD OF MAKING A CAPACITIVE OPTICAL MODULATOR

Abstract

A semiconductor device can be formed by etching a cavity in a first silicon layer that overlies an insulating layer, epitaxially growing a germanium or silicon-germanium layer in the cavity, epitaxially growing a second silicon layer in the cavity, etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, selectively etching a portion of the second strip to decrease the width of the second strip, filling cavity portions arranged on either side of the first and second strips with an insulator, depositing an upper insulating layer over the first and second strips, and bonding a layer of III-V material to the upper insulating layer.

Claims

1. A method comprising: etching a cavity in a first silicon layer that overlies an insulating layer, the cavity having sidewalls and a floor; epitaxially growing a germanium or silicon-germanium layer in the cavity, the germanium or silicon-germanium layer being grown from the floor of the cavity; epitaxially growing a second silicon layer in the cavity, the second silicon layer being grown from the germanium or silicon-germanium layer to fill the cavity; etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, the first strip on the second strip and having the same width as the second strip; selectively etching a portion of the second strip to decrease the width of the second strip so that the width of the first strip is greater than the width of the second strip; etching a portion of the first silicon layer to expose a portion of the insulating layer between one edge of the first strip and one of the sidewalls; filling cavity portions arranged on either side of the first and second strips with an insulator; depositing an upper insulating layer over the first and second strips; and bonding a layer of III-V material to the upper insulating layer.

2. The method of claim 1, wherein etching the second silicon layer and the germanium or silicon-germanium layer to define the first and second strips comprising anisotropically etching the second silicon layer and the germanium or silicon-germanium layer.

3. The method of claim 1, wherein selectively etching a portion of the second strip comprises isotropically etching the portion of the second strip.

4. The method of claim 1, wherein filling the cavity portions comprises: depositing a layer of the insulator filling the cavity portions; and performing a chemical-mechanical planarization down to an upper surface of the first silicon layer.

5. The method of claim 1, wherein bonding the layer of III-V material to the upper insulating layer comprises layer molecular bonding.

6. The method of claim 1, wherein the layer of III-V material has a thickness substantially equal to a thickness of the first strip.

7. The method of claim 1, wherein the layer of III-V material comprises InGaAsP or InP.

8. The method of claim 1, wherein the upper insulating layer comprises HfO.sub.2, Al.sub.2O.sub.3 or SiO.sub.2.

9. The method of claim 1, wherein the layer of III-V material comprises InGaAsP and the upper insulating layer comprises Al.sub.2O.sub.3.

10. The method of claim 1, wherein the first strip, the upper insulating layer, and the layer of III-V material form a capacitive electro-optical modulator.

11. The method of claim 1, wherein the germanium or silicon-germanium layer comprises silicon-germanium with a germanium atom concentration in the range from 10 to 20%.

12. A method, the method comprising: etching a cavity in a first silicon layer having a first conductivity type, the cavity having sidewalls and a floor; epitaxially growing a germanium or silicon-germanium layer having the first conductivity type in the cavity, the germanium or silicon-germanium layer being grown from the floor of the cavity; epitaxially growing a second silicon layer having the first conductivity type in the cavity, the second silicon layer being grown from the germanium or silicon-germanium layer to fill the cavity; etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, the first strip on the second strip and having the same width as the second strip; selectively etching a portion of the second strip to decrease the width of the second strip so that the width of the first strip is greater than the width of the second strip; filling cavity portions arranged on either side of the first and second strips with an insulator; depositing an insulating layer; bonding a layer of III-V material to the insulating layer, the layer of III-V material having a second conductivity type opposite the first conductivity type; forming a first electrode electrically at a portion of the first silicon layer at a sidewall of the cavity, the first electrode being electrically coupled to the first strip and the second strip by the first silicon layer; and forming a second electrode that is electrically coupled to the layer of III-V material at a location laterally spaced from the first and second strips.

13. The method of claim 12, further comprising applying a non-zero voltage between the first and second electrodes.

14. The method of claim 12, wherein bonding the layer of III-V material to the insulating layer comprises molecular bonding.

15. The method of claim 12, wherein the first conductivity type is p-type and the second conductivity type is n-type.

16. The method of claim 12, further comprising, after selectively etching the portion of the second strip and prior to filling the cavity portions, etching a portion of the first silicon layer to expose a portion of the insulating layer between one edge of the first strip and one of the sidewalls.

17. The method of claim 16, wherein the second electrode is formed at a location that overlies the portion of the insulating layer that was exposed when etching the first silicon layer.

18. A method comprising: etching a cavity in a first silicon layer that overlies an insulating layer, the cavity having sidewalls and a floor; epitaxially growing a germanium or silicon-germanium layer in the cavity, the germanium or silicon-germanium layer being grown from the floor of the cavity; epitaxially growing a second silicon layer in the cavity, the second silicon layer being grown from the germanium or silicon-germanium layer to fill the cavity; anisotropically etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, the first strip on the second strip and having the same width as the second strip; isotropically etching a portion of the second strip to decrease the width of the second strip so that the width of the first strip is greater than the width of the second strip; depositing a layer of insulator to fill cavity portions arranged on either side of the first and second strips with the insulator; performing a chemical-mechanical planarization of the insulator down to an upper surface of the first silicon layer; depositing an upper insulating layer over the first and second strips, the upper insulating layer comprising HfO.sub.2, Al.sub.2O.sub.3 or SiO.sub.2; and bonding, by molecular bonding, a layer of III-V material to the upper insulating layer, the layer of III-V material comprising InGaAsP or InP.

19. The method of claim 18, further comprising, after isotropically etching the portion of the second strip and prior to depositing the layer of insulator, etching a portion of the first silicon layer to expose a portion of the insulating layer between one edge of the first strip and one of the sidewalls.

20. The method of claim 18, wherein the first strip, the second strip and the first silicon layer have a first conductivity type; wherein layer of III-V material has a second conductivity type opposite the first conductivity type; and wherein the first strip, the upper insulating layer, and the layer of III-V material form a capacitive electro-optical modulator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a simplified cross-section view illustrating a step of an embodiment of a method of manufacturing a hybrid III-V/Si type electro-optical capacitive modulator;

[0025] FIG. 2 is a simplified cross-section view illustrating steps of an embodiment of a method of manufacturing a hybrid III-V/Si type electro-optical capacitive modulator;

[0026] FIG. 3 is a simplified cross-section view illustrating other steps of an embodiment of a method of manufacturing a hybrid III-V/Si type electro-optical capacitive modulator;

[0027] FIG. 4 is a simplified cross-section view illustrating other steps of an embodiment of a method of manufacturing a hybrid III-V/Si type electro-optical capacitive modulator;

[0028] FIG. 5 is a simplified cross-section view illustrating other steps of an embodiment of a method of manufacturing a hybrid III-V/Si type electro-optical capacitive modulator;

[0029] FIG. 6 is a simplified cross-section view illustrating an alternative embodiment of the steps of FIG. 3; and

[0030] FIG. 7 is a simplified cross-section view illustrating the implementation, after the step of FIG. 6, of the steps of FIGS. 4 and 5.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0031] The same elements have been designated with the same reference numerals in the different drawings. In particular, the structural and/or functional elements common to the different embodiments may be designated with the same reference numerals and may have identical structural, dimensional, and material properties.

[0032] For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the integrated optoelectronic circuits and the applications where a modulator such as described may be provided have not been detailed, the described modulators being compatible with usual circuits and applications.

[0033] Throughout the present disclosure, the term electrically “connected” is used to designate a direct electrical connection between circuit elements, whereas the term “coupled” is used to designate an electrical connection between circuit elements that may be direct, or may be via one or more other elements.

[0034] In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., unless otherwise specified, it is referred to the orientation of the drawings.

[0035] The terms “about,” “approximately,” “substantially,” and “in the order of” are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question.

[0036] Unless otherwise specified, a first layer or a first layer portion resting on a second layer or a second layer portion means that the first layer or layer portion rests on and in contact with the second layer or layer portion.

[0037] An embodiment of a method of manufacturing a hybrid III-V/Si-type electro-optical capacitive modulator will now be described in relation with FIGS. 1, 2, 3, 4, and 5, these drawings being cross-section views illustrating steps of the method. The cross-section views of FIGS. 1 to 5 are taken in a cross-section plane orthogonal to a direction of propagation of an optical signal in the modulator, for example, a signal having its wavelength(s) in near infrared, for example, in the range from 1 to 2 μm, preferably equal to approximately 1.3 μm or approximately 1.55 μm, for example, to 1.3 μm or 1.55 μm.

[0038] FIG. 1 illustrates a step of an embodiment of a method of manufacturing a hybrid III-V/Si-type electro-optical capacitive modulator.

[0039] At this step, cavity 100 has been etched in a silicon layer 102. Layer 102 is preferably of silicon-on-insulator or SOI type, that is, it rests on an insulating layer 104, for example, made of silicon oxide, itself resting on a support substrate 106, for example, made of silicon.

[0040] Cavity wo is etched across a portion only of the thickness of layer 102, so that the other portion of the thickness of layer 102 remains in place on layer 104, at the bottom of cavity 100. In other words, a silicon layer 108 is left in place at the bottom of cavity 100, layer 108 corresponding to the portion of the thickness of layer left in place at the bottom of cavity 100. The thickness of layer 108 is for example determined by the etch time.

[0041] As an example, the thickness of layer 102 is approximately equal to 300 nm, for example, equal to 300 nm. The thickness of layer 108 is for example in the range from 30 to 100 nm, for example, approximately equal to 50 nm, preferably equal to 50 nm.

[0042] Preferably, although this is not shown in FIG. 1, the cavity extends longitudinally in the direction of propagation of an optical signal in the modulator, that is, here, in a direction orthogonal to the plane of FIG. 1. As an example, in top view, not shown, the cavity has a rectangular shape.

[0043] As an example, the width of cavity 100, for example, measured along a direction orthogonal to the propagation direction of a signal in the modulator and parallel to the upper surface of layer 108, is in the range from 2 to 5 μm, for example, approximately equal to 3.5 μm, preferably equal to 3.5 μm.

[0044] Although this has not been shown in FIG. 1, an etch mask is deposited on layer 102 prior to the etching of cavity 100, the etch mask of cavity 100 comprising an opening emerging onto layer 102, at the location of cavity 100.

[0045] FIG. 2 illustrates steps of an embodiment of a method of manufacturing a hybrid III-V/Si-type capacitive electro-optical modulator, and more particularly steps carried out after the step of FIG. 1.

[0046] At these steps, a germanium or silicon-germanium layer 200, for example, made of silicon-germanium with a germanium atom concentration in the range from 10 to 20%, has been formed in cavity 100, all over layer 108. Preferably, layer 200 is formed by epitaxy from layer 108, and more generally from the exposed surfaces of the silicon of layer 108 in cavity 100.

[0047] The thickness of layer 200 is smaller than the depth of cavity wo etched at the step of FIG. 1. In other words, the level of the upper surface of layer 200 is below the level of the upper surface of layer 102.

[0048] As an example, the thickness of layer 200 is in the range from 50 to 150 nm, preferably from 80 to 120 nm, for example, equal to approximately 100 nm, preferably equal to 100 nm.

[0049] A silicon layer 202 is then formed, in cavity 100, all over layer 200. Layer 202 is preferably formed by epitaxy from layer 202.

[0050] The thickness of layer 202 is selected so that cavity 100 is filled with layers 200 and 202. Preferably, the thickness of layer 202 is selected so that its upper surface is flush with the upper surface of layer 102.

[0051] According to an embodiment, layer 202 is directly formed with the desired thickness.

[0052] According to another embodiment, layer 202 is formed with a thickness greater than the desired thickness, and a chemical-mechanical polishing or CMP step is then carried out to take layer 202 down to the desired thickness.

[0053] As an example, the thickness of layer 202 is in the range from wo to 200 nm, preferably from 125 to 175 nm, for example, approximately equal to 150 nm, preferably equal to 150 nm.

[0054] Although this is not shown in FIG. 2, preferably, at the steps of FIG. 2, the mask for etching cavity 100 is left in place on layer 102.

[0055] FIG. 3 illustrates steps of an embodiment of a method of manufacturing a III-V/Si-type hybrid capacitive electro-optical modulator, and more particularly of the steps carried out after the steps of FIG. 2.

[0056] In FIG. 3, a portion of layers 200 and 202 is removed by etching down to layer 108. The etching is implemented to define a first silicon strip 300 in layer 202, and a second germanium or silicon-germanium strip 302 in layer 200, strips 300 and 302 corresponding to portions of respective layers 202 and 200.

[0057] Although this is not shown in FIG. 3, strips 300 and 302 extend lengthwise in the propagation direction of an optical signal in the modulator, from one end to the other of cavity 100 taken lengthwise. The stack of layers 300 and 302 is then laterally bordered, all along its length, with two cavities 100L and 100R respectively arranged on either side of the stack. Cavities 100L and 100R correspond to respective portions of cavity 100.

[0058] The etching to define strips 300 and 302 is preferably an anisotropic etch step. This etching is for example implemented after the forming of an etch mask resting on layer 202, above and opposite the future strips 300 and 302. Preferably, when strips 300 and 302 are defined, the etch mask of cavity 100 is left in place.

[0059] After the etching to define strips 300 and 302, although this is not illustrated herein, silicon strip 300 entirely rests on germanium or silicon-germanium strip 302. In other words, the entire lower surface of strip 300 is in contact with the entire upper surface of strip 302. Still in other words, strips 300 and 302 have a same width and aligned edges.

[0060] In FIG. 3, after having defined by etching strips 300 and 302 in respective layers 202 and 200, the width of strip 302 is decreased with respect to that of strip 300.

[0061] To achieve this, a step of selective etching of the material of strip 302 over that of strip 300 is implemented. This etch step is an isotropic etch step. As an example, the decrease of the width of strip 302 is determined by the etching time. Preferably, during this etching, the etch mask of cavity 100 and/or the etch mask for defining strips 300 and 302 are left in place.

[0062] After having decreased the width of strip 302 with respect to that of strip 300, as shown in FIG. 3, strip 300 comprises a central portion or strip resting on strip 302, and two suspended lateral portions or strips, on either side of strip 302.

[0063] As an example, the width of strip 300 is in the range from 300 nm to 5 μm, for example, from 350 to 550 nm, for example, approximately equal to 450 nm, preferably equal to 450 nm. The width of strip 302, after its has been decreased by etching, is for example in the range from 25 to 100 nm, for example, from 25 to 75 nm, for example, equal to approximately 50 nm, preferably equal to 50 nm.

[0064] FIG. 4 illustrates steps of an embodiment of a method of manufacturing a hybrid III-V/Si-type capacitive electro-optical modulator, and more particularly steps carried out after the steps of FIG. 3.

[0065] At these steps, cavity 100, and more exactly cavities 100L and 100R (FIG. 3) arranged on either side of the stack of strips 300 and 302, are filled with an insulator 400, for example, silicon oxide, for example, made of the same insulating material as layer 104.

[0066] This step of filling cavities 100L and 100R is implemented so that the upper surface of insulator 400, the upper surface of strip 300, and the upper surface of layer 102 are at the same level. In other words, insulator 400 is flush with the upper surface of layer 102 and the upper surface of strip 300.

[0067] According to an embodiment, a layer of insulator 400 is deposited over the entire structure with a thickness greater than or equal to the depth of cavity 100, and thus of cavities 100L and 100R, to totally fill cavities 100L and 100R. A step of chemical-mechanical polishing or CMP down to the upper surface of layer 102 is then implemented.

[0068] Preferably, the etch mask of cavity 100 (step of FIG. 1) and the etch mask to define strips 300 and 302 (step of FIG. 3) are removed prior to the filling of cavities 100R and 100L by insulator 400.

[0069] An insulating layer 402 is then deposited over the planar upper surface of the structure, that is, over the upper surface of layer 102, the upper surface of strip 300, and the upper surface of insulator 400. Layer 402 is intended to form the insulator between two electrodes of a capacitor of the modulator, this capacitor enabling to modulate an optical signal propagating in the modulator when a voltage is applied between its two electrodes.

[0070] As an example, layer 402 has a thickness in the range from 5 to 15 nm, for example approximately equal to 10 nm, preferably equal to 10 nm. More generally, the thickness of layer 402 is for example adapted according to the targeted application, for example, equal to approximately 5 nm, preferably equal to 5 nm, for a low-voltage operation, or for example equal to approximately 15 nm, preferably equal to 15 nm, for an operation at high frequencies in the order of 35 GHz.

[0071] As an example, layer 402 is formed of one or a plurality of insulating layers, for example, of HfO.sub.2, Al.sub.2O.sub.3 and/or SiO.sub.2, preferably of a single Al.sub.2O.sub.3 layer. Preferably, layer 402 is, at least on its upper surface side, made of a material selected to allow the molecular bonding of a layer of III-V material to layer 402.

[0072] FIG. 5 illustrates steps of an embodiment of a method of manufacturing a III-V/Si-type hybrid capacitive electro-optical modulator, and more particularly steps carried out after the steps of FIG. 4.

[0073] In FIG. 5, a layer 500 of a III-V material has been bonded to layer 402, by molecular bonding. In other words, layer 500 has been transferred onto layer 402.

[0074] According to an embodiment, the thickness of layer 500 before being bonded to layer 402 is already substantially equal, preferably equal, to the thickness of strip 300.

[0075] According to another embodiment, the thickness of layer 500 before being bonded to layer 402 is greater than that of strip 300, and the step of bonding or transferring layer 500 onto layer 402 is then followed by a step of etching or CMP to decrease the thickness of layer 500 down to a thickness substantially equal, preferably equal, to the thickness of strip 300.

[0076] As an example, the thickness of strip 300 is for example in the range from wo to 200 nm, preferably approximately equal to 150 nm, preferably equal to 150 nm.

[0077] Further, in FIG. 5, once layer 500 has been bonded to layer 402 and adjusted, if necessary, to the desired thickness, a portion of layer 500 is removed by etching down to layer 402. The etching may be carried on across the entire thickness of layer 402, to remove the portions of layer 402 exposed after the etching of layer 500.

[0078] The portion of layer 500 left in place comprises a first portion or strip 501 arranged above and opposite strip 300. In other words, the edges of strips 501 and 300 are aligned. The portion of layer 500 left in place further comprises a second portion or strip 502 extending laterally from strip 501. The two strips 501 and 502 are delimited by dotted lines in FIG. 5. Preferably, strip 502 is only opposite insulator 400.

[0079] In the structure or modulator illustrated in FIG. 5, strip 300, strip 501 of layer 500 and the portion or strip or layer 402 interposed between strips 300 and 501 form the waveguide of the modulator. The waveguide is capable of propagating in guided fashion an optical signal to be modulated.

[0080] Strip 300 is in contact with strip 302, itself in contact with layer 108. Layer 108 is in contact with portions 504 of layer 102 laterally bordering cavity 100 lengthwise, which portions 504 have not been etched at the step of FIG. 1. Although this is not illustrated herein, the portions 504 of layer 102 are electrically coupled to a first terminal of application of a voltage of the modulator. Portions 504, layer 108, and strips 302 and 300 then form a first electrode of the capacitor of the modulator.

[0081] Portions 504, layer 108, and strips 302 and 300 are doped with a first conductivity type, for example, type P.

[0082] The strips 501 and 502 of layer 500 are in contact with each other. A portion of strip 502, preferably arranged on the side opposite to strip 501, is electrically coupled to a second terminal of application of a voltage of the modulator. Layer 500 then forms a second electrode of the capacitor of the modulator.

[0083] Layer 500 is doped with the second conductivity type, for example, type N.

[0084] In the modulator of FIG. 5, when a non-zero voltage is applied between the first and second terminals of the modulator, charges are stored in strip 501, respectively 300, along the strip of layer 402 in contact with strips 501 and 300. This results in a corresponding modification of the optical index of the waveguide of the modulator, and thus in a modulation of the signal propagating in the waveguide of the modulator.

[0085] An advantage of the modulator illustrated in FIG. 5 is that the two strips 300 and 502 have the same thickness, which enables to center the optical mode of the signal to be modulated on the strip of layer 402 interposed between strips 300 and 501, where the charge storage is maximum. This results in a better modulation than if this optical mode was off-centered with respect to the strip of layer 402 interposed between strips 300 and 501, as would for example be the case in a modulator where strips 300 and 501 would not have the same thickness.

[0086] Further, in the modulator of FIG. 5, the thickness of strips 300 and 501 is different from that of layer 102, without it being necessary to increase the thickness of layer 402. More generally, in the modulator of FIG. 5, the thickness of strips 300 and 501 and the thickness of layer 402 may be selected to obtain a cross-section of the modulator waveguide which corresponds to a given confinement of the optical mode of the signal to be modulated, preferably a maximum confinement of this optical mode in the waveguide. In other words, the thicknesses may be selected to increase, preferably to maximize, the overlapping of the optical mode of the signal to be modulated and of the portions of strips 300 and 501 where charges or free carriers are stored. This results in an increase in the efficiency of the modulation of this optical mode.

[0087] Further, the thickness of layer 402 may be selected independently from the thickness of strips 300 and 501, to optimize the operation of the modulator.

[0088] Such advantages of the modulator of FIG. 5 particularly result from the method of manufacturing the modulator, described in relation with FIGS. 1 to 5. Indeed, such a method particularly enables to select the thickness of strips 300 and 501, as well as that of layer 402, while keeping, at the step of FIG. 4, a layer 402 having a planar upper surface enabling to bond or to transfer layer 500 of III-V material onto layer 402.

[0089] Although this is not illustrated, the previously-described method may comprise an additional step of partially etching layer 500, and more particularly a portion of strip 502 extending from strip 501 to a portion of strip 502 electrically coupled to the second terminal of application of a modulation voltage. This enables to further improve the confinement of the optical mode of the signal to be modulated in the waveguide of the modulator.

[0090] According to an aspect of an embodiment, the doping levels in the various layers, regions, portions, strips of the modulator of FIG. 5 may be adapted to optimize the operation of the modulator. As an example: [0091] portions 504 are doped with a first doping level, for example, in the range from 5.10.sup.19 at.Math.cm.sup.−3 to 5.10.sup.20 at.Math.cm.sup.−3, preferably equal to 10.sup.20 at.Math.cm.sup.−3; [0092] first strips 108A of layer 108 laterally extending from portions 504 to a second strip 108B of layer 108 comprising a central portion arranged under and opposite strips 300 and 501, are doped with a second doping level smaller than the first doping level, for example, a second doping level in the range from 10.sup.19 at.Math.cm.sup.−3 to 10.sup.20 at.Math.cm.sup.−3, preferably equal to 5.10.sup.19 at.Math.cm.sup.−3; [0093] strip 108A, strip 302, and strip 300 are doped with a third doping level smaller than the second doping level, for example, a third doping level in the range from 5.10.sup.18 at.Math.cm.sup.−3 to [0094] 5.10.sup.16 at.Math.cm.sup.−3, preferably equal to 5.10.sup.17 at.Math.cm.sup.−3; [0095] strip 501 and, preferably, a portion of strip 502 laterally extending from strip 501, are doped with the third doping level; [0096] a central portion of strip 502 is doped with the second doping level; and [0097] a lateral portion of strip 502, arranged on the side opposite to 501, is doped with the third doping level.

[0098] The portions and the strips doped with the first doping level are located sufficiently far from the modulator waveguide to be doped with the first high doping level, without however disturbing the propagation and the modulation of a signal in the waveguide. The first high doping level enables to decrease the resistivity of these portions and strips, and thus to increase the cut-off frequency of the modulator.

[0099] The implementation of the doping steps, with the desired levels, the various regions, strips, portions, layers of the modulator of FIG. 5 is within the abilities of those skilled in the art.

[0100] The way in which the waveguide of the modulator is optically coupled or connected to a first silicon waveguide defined in layer 102 and delivering the optical signal to be modulated and to a second silicon waveguide defined in layer 102 and receiving the modulated signal is not detailed and is within the abilities of those skilled in the art. In particular, it will be within the abilities of those skilled in the art to achieve such an optical coupling between the first and second waveguides and the modulator waveguide so as to provide a progressive variation of the effective optical index, for example, by appropriately varying the width of the first and second silicon waveguides and the width of strips 302, 300, 501, and/or 502.

[0101] FIG. 6 is a simplified cross-section view illustrating an alternative embodiment of the steps of FIG. 3.

[0102] In this variation, in addition to the steps described in relation with FIG. 3, an additional etch step, preferably an anisotropic etching, is provided to suppress the portion of layer 108 arranged on one side of the stack of strips 302 and 300 taken lengthwise, on the right-hand side in the example of FIG. 6.

[0103] For this purpose, after having defined strips 300 and 302 from layers 200 and 202, and before or after, preferably before, decreasing the width of strip 302 with respect to that of strip 300, an additional etch mask is formed on the portion of layer 108 to be left in place. In other words still, the additional mask is formed on the portion of layer 108 forming the bottom of one of cavities 100L and 100R, cavity 100R in the example of FIG. 6.

[0104] Preferably, at this step, the etch mask of cavity 100 and the etch mask for defining strips 300 and 302 are left in place, the additional etch mask then overlapping these two masks and resting on the portion of layer 108 to be left in place.

[0105] FIG. 7 is a simplified cross-section view illustrating the modulator obtained after the implementation of the steps of FIGS. 4 and 5 from the structure described in relation with FIG. 6.

[0106] In this variation, as compared with what has been described in relation with FIG. 5, during the step of etching layer 500 to only leave in place a strip 501 above strip 300 and a strip 502 extending laterally from strip 501, strip 502 is preferably arranged on the side of strip 501 where layer 108 has been removed by etching during the step described in relation with FIG. 6. Preferably, as shown in FIG. 7, and similarly to what has been described in relation with FIG. 5, strip 502 is only present opposite insulator 400. Further, the portion 504 of layer 102 laterally bordering cavity 100 on the side of strip 502, that is, the portion 504 arranged on the right-hand side of FIG. 7, may not be coupled or connected to the first terminal of application of a voltage of the modulator. This portion 504 (on the right-hand side of FIG. 7) may be arranged farther from strip 300 than the other portion 504 (on the left-hand side of FIG. 7), for example, to avoid forming a stray capacitance between the portion 504 laterally bordering cavity 100 on the side of strip 502 (portion 504 on the right-hand side of FIG. 7) and strip 502.

[0107] The inventors have observed that the modulator of FIG. 5 or of FIG. 7 enable to reach modulation frequencies greater than 30 GHz, or even greater than 35 GHz, for example, substantially equal to 40 GHz, particularly when the modulator has the previously-indicated preferred dimensions and doping level.

[0108] Various embodiments and variations have been described. It will be understood by those skilled in the art that certain features of these various embodiments and variations may be combined, and other variations will occur to those skilled in the art.

[0109] Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereinabove. In particular, the dimensions, particularly the thicknesses, and/or the doping levels of the different layers, portions, strips of the modulators of FIGS. 5 and 7 may be determined by those skilled in the art according to the optical signal to be modulated, particularly to its wavelengths and to the considered optical mode, and/or to the targeted modulation frequency.

[0110] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.