Control Unit, Radio Frequency Power Generator, and Method for Generating Synchronized Radio Frequency Output Signals

Abstract

A control unit for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i) each having a respective output frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i), including a signal comparator configured to compare a reference signal having a reference frequency (f.sub.ref) and a reference phase (Φ.sub.ref) with a feedback signal having a feedback frequency (f.sub.PLL) and a feedback phase (Φ.sub.PLL), and configured to generate an error signal representative of a difference between the reference signal and the feedback signal; and a data processing unit receiving as an input signal the error signal generated by the signal comparator, and outputting a plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) as a function of the error signal; wherein a plurality of waveform generators (DDS.sub.PLL, DDS.sub.i) each receiving at least one of the plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) output by the data processing unit, wherein each waveform generator (DDS.sub.PLL, DDS.sub.i) generates a time-dependent amplitude signal (A.sub.PLL(t), A.sub.i(t)) as a function of the received respective waveform tuning signal (FTW.sub.PLL, FTW.sub.i), wherein one predetermined amplitude signal (A.sub.PLL(t)) of the generated plurality of amplitude signals (A.sub.PLL(t), A.sub.i(t)) represents the feedback signal input to the signal comparator, and the other amplitude signals (A.sub.i(t)) represent the respective radio frequency (RF) output signals (RF.sub.out,i) to be generated, and wherein the data processing unit is configured to adjust both the waveform tuning signal (FTW.sub.PLL) corresponding to the one predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal such as to minimize the error signal, and the other waveform tuning signals (FTW.sub.i) corresponding to the other amplitude signals (A.sub.i(t)) representing the radio frequency (RF) output signals (RF.sub.out,i) based on the adjusted waveform tuning signal (FTW.sub.PLL) of the predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal.

The disclosure further describes a radio frequency (RF) power generator, an arrangement of at least two such radio frequency (RF) power generators, and a method each for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i).

Claims

1. A control unit for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i) each having a respective output frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i), comprising: a signal comparator configured to compare a reference signal having a reference frequency (f.sub.ref) and a reference phase (Φ.sub.ref) with a feedback signal having a feedback frequency (f.sub.PLL) and a feedback phase (Φ.sub.PLL), and configured to generate an error signal representative of a difference between the reference signal and the feedback signal; and a data processing unit receiving as an input signal the error signal generated by the signal comparator, and outputting a plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) as a function of the error signal; wherein a plurality of waveform generators (DDS.sub.PLL, DDS.sub.i) each receiving at least one of the plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) output by the data processing unit, wherein each waveform generator (DDS.sub.PLL, DDS.sub.i) generates a time-dependent amplitude signal (A.sub.PLL(t), A.sub.i(t)) as a function of the received respective waveform tuning signal (FTW.sub.PLL, FTW.sub.i); wherein one predetermined amplitude signal (A.sub.PLL(t)) of the generated plurality of amplitude signals (A.sub.PLL(t), A.sub.i(t)) represents the feedback signal to the signal comparator and the other amplitude signals (A.sub.i(t)) represent the respective radio frequency (RF) output signals (RF.sub.out,i) to be generated, and wherein the data processing unit is configured to adjust both the waveform tuning signal (FTW.sub.PLL) corresponding to the one predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal such as to minimize the error signal, and the other waveform tuning signals (FTW.sub.i) corresponding to the other amplitude signals (A.sub.i(t)) representing the radio frequency (RF) output signals (RF.sub.out,i) based on the adjusted waveform tuning signal (FTW.sub.PLL) of the predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal.

2. The control unit as claimed in claim 1, wherein the signal comparator is configured to compare at least one of a phase difference and a frequency difference of the reference signal and the feedback signal, wherein the error signal is representative of at least one of said phase difference and frequency difference.

3. The control unit as claimed in claim 1, wherein the signal comparator is at least one of a phase discriminator (PD), phase-frequency discriminator (PFD), a frequency mixer, and a counter.

4. The control unit as claimed in claim 1, wherein the reference signal comprises one of a precision crystal oscillator signal, an oven-controlled crystal oscillator (OCXO) signal, an atomic clock signal, a high-precision oscillator signal synchronized with an atomic clock, and a common exciter (CEX) signal generated by an RF generator.

5. The control unit as claimed in claim 1, further comprising a reference signal source configured to generate the reference signal.

6. The control unit as claimed in claim 1, further comprising a series connection of a loop filter and an analog-to-digital-converter (ADC) configured and arranged such as to generate a digital representation of the error signal from the signal comparator, and to feed the digital representation of the error signal to the data processing unit, wherein the data processing unit is a digital data processing unit outputting a plurality of digital waveform tuning words (FTW.sub.PLL, FTW.sub.i) as the waveform tuning signals as input for the plurality of waveform generators (DDS.sub.PLL, DDS.sub.i).

7. The control unit as claimed in claim 6, wherein the waveform tuning word (FTW.sub.PLL, FTW.sub.i) comprises at least one of a frequency information, a phase information, and an amplitude information for generating the time-dependent amplitude signal (A.sub.PLL(t), A.sub.i(t)).

8. The control unit as claimed in claim 6, wherein each of the waveform generators (DDS.sub.PLL, DDS.sub.i) comprises a direct digital synthesis (DDS) core generating a bitstream representative of digital amplitude values constituting the respective time-dependent amplitude signal (A.sub.PLL(t), A.sub.i(t)).

9. The control unit as claimed in claim 8, further comprising at least one digital-to-analog-converter (DAC) converting the digital amplitude values (A.sub.PLL(t), A.sub.i(t)) contained in the bitstreams generated by the waveform generators (DDS.sub.PLL, DDS.sub.i) into the feedback signal and the radio frequency (RF) output signals (RF.sub.out,i), respectively.

10. The control unit as claimed in claim 9, wherein the digital-to-analog-converter (DAC) is one of a multi-channel digital-to-analog-converter, a plurality of single-channel digital-to-analog-converters, a plurality of dual-channel digital-to-analog-converters or a combination thereof.

11. The control unit as claimed in claim 9, further comprising at least one signal reconstruction filter (F.sub.i) filtering at least one of the radio frequency (RF) output signals (RF.sub.out,i) after conversion by the digital-to-analog converter (DAC).

12. The control unit as claimed in claim 9, further comprising a feedback signal reconstruction filter (F.sub.PLL) filtering the feedback signal after conversion by the digital-to-analog converter (DAC).

13. The control unit as claimed in claim 9, further comprising a system clock (CLK) generating a system clock signal, wherein the plurality of waveform generators (DDS.sub.PLL, DDS.sub.i) and the digital-to-analog converter (DAC) are driven by the system clock signal.

14. The control unit as claimed in claim 13, wherein a waveform generator clock signal for driving the waveform generators (DDS.sub.PLL, DDS.sub.i) and a DAC clock signal for driving the digital-to-analog converter (DAC) are different predetermined rational fractions (m.sub.1/n.sub.1, m.sub.2/n.sub.2) of the system clock signal.

15. The control unit as claimed in claim 1, further comprising a memory device storing a plurality of predeterminable waveform set values (f.sub.sv,i) each corresponding to one respective of the waveform tuning signals (FTW.sub.i) of the radio frequency (RF) output signals (RF.sub.out,i) to be generated, wherein the data processing unit is further configured to output the plurality of waveform tuning signals (FTW.sub.i) as a function of the waveform set values (f.sub.sv,i).

16. The control unit as claimed in claim 15, further comprising a control device configured to modify the waveform set values (f.sub.sv,i) stored in the memory device according to a predefined schedule.

17. The control unit as claimed in claim 1, wherein at least one of the data processing unit and the plurality of waveform generators (DDS.sub.PLL, DDS.sub.i) is/are formed by at least one of a field programmable gate array (FPGA), a System-on-Chip (SoC), and an application-specific integrated circuit (ASIC).

18. A radio frequency (RF) power generator for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i) each having a respective output frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i), comprising: a DC power supply; at least one power amplifier (PA.sub.i) receiving power from the DC power supply, and configured to amplify at least one of the plurality of radio frequency (RF) output signals (RF.sub.out,i); and a control unit for generating the plurality of radio frequency (RF) output signals (RF.sub.out,i), wherein the control unit is configured as claimed in claim 17.

19. The RF power generator as claimed in claim 18, further comprising a common exciter input (CEX.sub.in) connected to the control unit for receiving an external common exciter signal (CEX) as the reference signal.

20. The RF power generator as claimed in claim 18, further comprising at least one common exciter output (CEX.sub.out) providing a respective one of the plurality of radio frequency (RF) output signals (RF.sub.out,i) as an external common exciter signal (CEX).

21. The RF power generator as claimed in claim 18, further comprising a user interface device for at least one of setting the output frequencies (f.sub.i), phases (Φ.sub.i), and amplitudes (A.sub.i) of the radio frequency (RF) output signals (RF.sub.out,i) and monitoring an operational state of the power generator.

22. An arrangement of at least two radio frequency (RF) power generators each for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i) each having a respective output frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i), and each comprising: a DC power supply; at least one power amplifier (PA.sub.i) receiving power from the DC power supply, and configured to amplify at least one of the plurality of radio frequency (RF) output signals (RF.sub.out,i); and a control for generating the plurality of radio frequency (RF) output signals (RF.sub.out,i), wherein the control unit is configured as claimed in claim 17, wherein one of the power generators further comprises at least one common exciter output (CEX.sub.out) providing a respective one of the plurality of radio frequency (RF) output signals (RF.sub.out,i) as an external common exciter signal (CEX), and at least one other of the power generators further comprises a common exciter input (CEX.sub.in) connected to the control unit for receiving an external common exciter signal (CEX) as the reference signal; and wherein the power generators are interconnected such that the common exciter output (CEX.sub.out) of the one of the power generators is connected to the common exciter input (CEX.sub.in) of the at least one other of the power generators.

23. A method for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i) each having a respective output frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i), comprising the steps of: (i) comparing a reference signal having a reference frequency (f.sub.ref) and a reference phase (Φ.sub.ref) with a feedback signal having a feedback frequency (f.sub.PLL) and a feedback phase (Φ.sub.PLL); (ii) generating an error signal representative of a difference between the reference signal and the feedback signal; (iii) generating a plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) as a function of the error signal; (iv) generating a plurality of time-dependent amplitude signals (A.sub.PLL(t), A.sub.i(t)) each one as a function of a respective one of the plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i); (v) selecting one predetermined amplitude signal (A.sub.PLL(t)) of the generated plurality of amplitude signals (A.sub.PLL(t), A.sub.i(t)) as a representation of the feedback signal in step (i); and (vi) outputting the other amplitude signals (A.sub.i(t)) as the respective radio frequency (RF) output signals (RF.sub.out,i) to be generated, wherein in step (iii) the one waveform tuning signal (FTW.sub.PLL) corresponding to the one predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal is adjusted such as to minimize the error signal in step (ii), and the other waveform tuning signals (FTW.sub.i) corresponding to the other amplitude signals (A.sub.i(t)) representing the radio frequency (RF) output signals (RF.sub.out,i) are adjusted based on the adjusted waveform tuning signal (FTW.sub.PLL) of the predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal.

24. The method as claimed in claim 23, further comprising the steps of: (vii) setting at least one of a frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i) as predeterminable signal parameters for at least one of the plurality of radio frequency (RF) output signals (RF.sub.out,i); (viii) repeating steps (i) to (vi) for a predetermined time interval (TI); and repeating steps (vii) and (viii) a predefined number of times.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0093] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0094] The disclosure will now be described, by way of example, based on embodiments with reference to the accompanying drawings.

[0095] In the drawings, schematically:

[0096] FIG. 1 illustrates a functional diagram of an exemplary embodiment of an RF power generator according to the disclosure comprising an exemplary embodiment of a control unit according to the disclosure.

[0097] FIG. 2 illustrates a functional diagram of another exemplary embodiment of an RF power generator according to the disclosure comprising another exemplary embodiment of a control unit according to the disclosure.

[0098] FIG. 3 illustrates a functional diagram of yet another exemplary embodiment of an RF power generator according to the disclosure comprising a more detailed functional diagram of the control unit in FIG. 2.

[0099] FIG. 4 shows a functional diagram of an exemplary embodiment of an arrangement of two RF power generators according to the disclosure.

[0100] FIG. 5 depicts a functional diagram of another exemplary embodiment of an arrangement of two RF power generators according to the disclosure.

[0101] FIG. 6 shows a functional diagram of still another exemplary embodiment of an arrangement of two RF power generators according to the disclosure.

[0102] FIG. 7 illustrates a functional diagram of an exemplary embodiment of an arrangement of three RF power generators according to the disclosure.

[0103] FIG. 8 shows a functional diagram of another exemplary embodiment of an arrangement of three RF power generators according to the disclosure.

[0104] FIG. 9 shows a flow chart of an exemplary embodiment of a method for generating RF output signals according to the disclosure.

[0105] In the Figures, like numbers refer to like objects throughout. Objects in the Figures are not necessarily drawn to scale.

DESCRIPTION OF THE DISCLOSURE

[0106] Various embodiments of the disclosure will now be described by means of the Figures.

[0107] FIG. 1 illustrates a functional diagram of an exemplary embodiment of an RF power generator 1 according to the disclosure comprising an exemplary embodiment of a control unit 2 according to the disclosure.

[0108] FIG. 2 illustrates a functional diagram of another exemplary embodiment of an RF power generator 20 according to the disclosure comprising another exemplary embodiment of a control unit 21 according to the disclosure.

[0109] First, the control unit 2 will be described in more detail hereinafter. Hereby, reference is made to FIGS. 1 and 3 in an alternating fashion, the latter showing i.a. a more detailed functional diagram of the control unit 21 in FIG. 2. However, with regard to the description of the control unit 2 of the RF generator 1 in FIG. 1, references made to FIG. 3 relate only to common components shared by both the control unit 2 and the control unit 21. Essentially, the control unit 2 in FIG. 1 and the control unit 21 in FIGS. 2 and 3, respectively, only differ in the way a reference signal is generated and input to the respective control units 2 and 21, respectively, as will become clearer along with the description of FIG. 2.

[0110] In FIG. 1 it is observed that the control unit 2 for generating a plurality (in the present case i=1 to k) of synchronized RF output signals RF.sub.out,i each having a respective output frequency f.sub.i, phase Φ.sub.i, and amplitude A.sub.i, comprises a signal comparator 3, e.g. a phase discriminator (PD), phase-frequency discriminator (PFD), a frequency mixer, or a counter, configured to compare a reference signal 4 having a reference frequency f.sub.ref and a reference phase Φ.sub.ref with a feedback signal 5 having a feedback frequency f.sub.PLL and a feedback phase Φ.sub.PLL. The control unit 2 is configured to generate an error signal 6 representative of a difference between the reference signal 4 and the feedback signal 5. In particular, the signal comparator 3 compares at least one of a phase difference and a frequency difference of the reference signal 4 and the feedback signal 5 so that the error signal 6 is representative of at least one of said phase difference and frequency difference.

[0111] Further, the control unit 2 as illustrated in FIG. 1 comprises a data processing unit 7, e.g. a digital data processing unit such as a microprocessor, microcontroller, digital signal processor and the like, receiving as an input signal the error signal 6 generated by the signal comparator 3, and outputting a plurality of waveform tuning signals FTW.sub.PLL, FTW.sub.i (cf. FIG. 3) as a function of the error signal 6. It is to be noted that the error signal 6 input to the data processing unit 7 may comprise a digital representation 6′ of the error signal 6 as will be elucidated in more detail further below. In the presented case, waveform tuning signals FTW.sub.PLL, FTW.sub.i are formed by digital waveform tuning words, wherein the waveform tuning words each comprise at least one of a frequency information, a phase information, and an amplitude information.

[0112] As can be viewed in FIGS. 1 and 3, the control unit 2 further comprises a plurality of waveform generators DDS.sub.PLL, DDS.sub.i (in the present case each one embodied as a direct digital synthesis cores) each receiving one of the plurality of waveform tuning signals FTW.sub.PLL, FTW.sub.i output by the data processing unit 7, wherein each waveform generator DDS.sub.PLL, DDS.sub.i generates a time-dependent amplitude signal A.sub.PLL(t), A.sub.i(t) as a function of the received respective waveform tuning signal FTW.sub.PLL, FTW.sub.i. In the control unit 2 of FIG. 1, the time-dependent amplitude signals A.sub.PLL(t), A.sub.i(t) are formed as a digital bitstream representing digital amplitude values for each corresponding RF output signal RF.sub.out,i.

[0113] One predetermined amplitude signal, i.e. amplitude signal A.sub.PLL(t), of the generated plurality of amplitude signals A.sub.PLL(t), A.sub.i(t) represents the feedback signal 5 input to the signal comparator 3, and the other amplitude signals A.sub.i(t) represent the respective RF output signals RF.sub.out,i to be generated.

[0114] Furthermore, in the control unit 2 of FIG. 1 the data processing unit 7 is configured to adjust both the waveform tuning signal FTW.sub.PLL corresponding to the one predetermined amplitude signal A.sub.PLL(t) representing the feedback signal 5 such as to minimize the error signal 6, and the other waveform tuning signals FTW.sub.i corresponding to the other amplitude signals A.sub.i(t) representing the RF output signals RF.sub.out,i based on the adjusted waveform tuning signal FTW.sub.PLL of the predetermined amplitude signal A.sub.PLL(t) representing the feedback signal 5.

[0115] The control loop formed by the signal comparator 3 receiving the reference signal 4 and the feedback signal 5, and the data processing unit 7 can be considered a PLL control loop, without being limited thereto.

[0116] FIG. 1 shows that the control unit 2 further comprises a reference signal source 8, i.e. a signal source internal to the control unit 2, configured to generate the reference signal 4. Preferably, in the example shown in FIG. 1, the internal reference signal source 8 may be a precision crystal oscillator or an oven-controlled crystal oscillator (OCXO), and the like.

[0117] Furthermore, FIG. 1 illustrates that the control unit 2 comprises a series connection of a loop filter 9 and an analog-to-digital-converter ADC configured and arranged such as to generate a digital representation 6′ of the error signal 6 from the signal comparator 3, and to feed the digital representation of the error signal 6′ to the data processing unit 7.

[0118] FIG. 1 also shows that in the control unit 2 the data processing unit 7 and the plurality of waveform generators DDS.sub.PLL, DDS.sub.i are formed by a field programmable gate array FPGA, however, not being limited thereto. A System-on-Chip (SoC), an application-specific integrated circuit (ASIC), and the like are also conceivable for implementing the data processing unit 7 and/or the waveform generators DDS.sub.PLL, DDS.sub.i.

[0119] The exemplary control unit 2 depicted in FIG. 1 also comprises at least one digital-to-analog-converter DAC, in the present case a multi-channel DAC, converting the digital amplitude values A.sub.PLL(t), A.sub.i(t) contained in the bitstreams generated by the waveform generators DDS.sub.PLL, DDS.sub.i into the feedback signal 5 and the RF output signals RF.sub.out,i, respectively.

[0120] It is to be noted that, instead of one multi-channel DAC shown in FIG. 1, a plurality of single-channel digital-DACs, a plurality of dual-channel DACs, a plurality of x-channel DACs or any combination thereof may be used.

[0121] The control unit 2 in FIG. 1 further comprises a plurality of signal reconstruction filters F.sub.i filtering the respective RF output signals RF.sub.out,i after conversion by the digital-to-analog converter DAC.

[0122] As indicated in FIG. 1 by means of a dashed rectangular box drawn around a feedback signal reconstruction filter F.sub.PLL, depending on the specific design of the signal comparator 3, the feedback signal reconstruction filter F.sub.PLL filtering the feedback signal 5 after conversion by the digital-to-analog converter DAC may be provided or may be omitted.

[0123] According to FIG. 1, the exemplary control unit 2 also comprises a system clock CLK generating a system clock signal 10. The plurality of waveform generators DDS.sub.PLL, DDS.sub.i and the digital-to-analog converter DAC are driven by the system clock signal 10, wherein a more detailed description of the system clock signal 10 and its specific use by the waveform generators DDS.sub.PLL, DDS.sub.i and the DAC will be given along with the discussion of FIG. 3 further below.

[0124] Still further, according to the embodiment of the control unit 2 shown in FIG. 1, a memory device 11, e.g. RAM, EPROM, Flash, ROM, and the like, storing a plurality of predeterminable waveform set values f.sub.sv,i each corresponding to one respective of the waveform tuning signals FTW.sub.i of the RF output signals RF.sub.out,i to be generated, wherein the data processing unit 7 is further configured to output the plurality of waveform tuning signals FTW.sub.i as a function of the waveform set values f.sub.sv,i. As with the waveform tuning signals FTW.sub.i, the waveform set values f.sub.sv,i may comprise a frequency information, a phase information, and/or an amplitude information with regard to the respective RF output signal to be generated.

[0125] Yet further, the control unit 2 presented in FIG. 1 also comprises a control device 12, e.g. a microprocessor, microcontroller, and the like, configured to modify the waveform set values f.sub.sv,i stored in the memory device 11 according to a predefined schedule, e.g. a plasma processing method. In the present case, the memory device 11 and the control device 12 are formed as one integrated electronic component/unit, however, without being limited thereto.

[0126] As observed in FIG. 1, the control unit 2 is part of the RF power generator 1 for generating the plurality of synchronized RF output signals RF.sub.out,i each having a respective output frequency f.sub.i, phase Φ.sub.i, and amplitude A.sub.i. To this end, the RF power generator 1 comprises a DC power supply 13, and power amplifiers PA.sub.i each receiving power from the DC power supply 13. Each power amplifier PA.sub.i is configured to amplify the respective RF output signal RF.sub.out,i. The detailed and specific settings of the DC power supply 13 may vary depending on the required gain of the power amplifiers and may be controlled by the control device 12 as required by the waveform set values f.sub.sv,i. For example, a lookup table and an algorithm to determine the best settings of the output power level of the DC power supply 13 may be used.

[0127] As already mentioned further above, the control unit 21 of the RF power generator 20 illustrated in FIG. 2 essentially differs from the control unit 2 shown in FIG. 1 only in that the reference signal 4 is not generated by an internal reference signal source 8 (cf. FIG. 1) but input to the control unit 21 from an external reference signal source 14. This reference signal source 14 being external to the control unit 21 and the RF power generator 20 may be an atomic clock providing an atomic clock reference signal, a high-precision oscillator synchronized with an atomic clock providing a high-precision oscillator signal, a precision crystal oscillator, an oven-controlled crystal oscillator (OCXO), or another RF power generator (not shown in FIG. 2) generating a common exciter CEX signal which is input to a common exciter input CEX.sub.in.

[0128] FIG. 3 illustrates a functional diagram of yet another exemplary embodiment of an RF power generator 30 according to the disclosure comprising a more detailed functional diagram of the control unit 21 in FIG. 2.

[0129] As shown in FIG. 3, the RF power generator 30 comprises a common exciter input CEX.sub.in connected to the control unit 21 for receiving an external common exciter signal CEX as the reference signal 4.

[0130] Furthermore, the exemplary RF power generator 30 further comprises two common exciter outputs CEX.sub.out1,2 each providing a respective one of the plurality of RF output signals RF.sub.out,k-1, RF.sub.out,k as an external common exciter signal CEX. It is to be noted that in the case according to FIG. 3, the two RF output signals RF.sub.out,k-1, RF.sub.out,k output on the respective CEX output CEX.sub.out1,2 have not been power-amplified by one of the power amplifiers PA.sub.i. Instead, they are output after being filtered by the respective signal reconstruction filters F.sub.k-1, F.sub.k. However, a small preamplification of the CEX output signals on CEX.sub.out1,2 by an appropriate preamplifier (not shown) may be provided.

[0131] As illustrated in FIG. 3, the RF generator 30 also comprises a user interface device 31, e.g. a touch screen, for setting the output frequencies f.sub.i, phases Φ.sub.i, and/or amplitudes A.sub.i of the respective RF output signals RF.sub.out,i and for monitoring an operational state of the RF power generator 30.

[0132] It is to be noted that in the case presented in FIG. 3, the user interface device 31 is part of the RF power generator 30. However, alternatively, it may be a component of the control unit 21 too.

[0133] FIG. 3 also illustrates that a waveform generator clock signal 32 (herein also referred to as an FPGA clock signal) for driving the waveform generators DDS.sub.PLL, DDS.sub.i and a DAC clock signal 33 for driving the digital-to-analog converter DAC are different predetermined rational fractions m.sub.1/n.sub.1 and m.sub.2/n.sub.2, respectively, of the system clock signal 10. Detailed description of how to determine the respective clock signals 32, 33 is given in the general part of this specification.

[0134] FIG. 4 shows a functional diagram of an exemplary embodiment of an arrangement 35 of two RF power generators, e.g. RF power generators 20 and 30, according to the disclosure. In this exemplary case, RF power generator 30 comprises a common exciter input CEX.sub.in and a common exciter output CEX.sub.out as well as two RF power output signals RF.sub.out1,2. RF power generator 20 comprises one common exciter input CEX.sub.in and one RF power output signal RF.sub.out3.

[0135] For example, such an arrangement may be used as a dual-frequency plasma power supply, e.g. 13.56 MHz and 60 MHz, or 13.56 MHz and 400 kHz as shown in FIG. 4. Due to the synchronization concept according to the disclosure described herein, the two power output signals RF.sub.out1 and RF.sub.out2 of the power generator 30 in FIG. 4 are automatically frequency-locked.

[0136] Another application scenario may be the combination of frequency-locked power generators of different brands. Then, power generator 30 in FIG. 4 acts as a master generator providing appropriate CEX signals to synchronize all connected power generators, i.e. generator 20 in FIG. 4 for example.

[0137] In particular, any existing conventional power generator which requires a dedicated CEX input signal can be synchronized with such a master power generator as the generator 30 in FIG. 4 for example. Moreover, the synchronized power generators may even be phase-shifted with respect to the master generator, and even cable length-induced phase shifts Φ.sub.c (as mentioned in the general description part of this specification) may already be compensated on the master generator side.

[0138] In FIG. 4, the master generator 30 generates two frequencies (in this case 400 kHz and 13.56 MHz) as its own power output signals RF.sub.out1,2, and provides a third frequency CEX signal CEX.sub.out to generator 20 (also maybe a conventional generator which can only be synced with its specific operating frequency, in this case 40.68 MHz for example).

[0139] FIG. 5 depicts a functional diagram of another exemplary embodiment of an arrangement 40 of two RF power generators according to the disclosure.

[0140] In the illustrated example, two linked RF power generators, e.g. generators 30 and 20, are synchronized to each other, wherein power generator 20 uses a CEX input signal CEX.sub.in already phase-shifted by ΔΦ in the master generator 30.

[0141] FIG. 6 shows a functional diagram of still another exemplary embodiment of an arrangement 45 of two RF power generators, e.g. power generators 20 and 30, according to the disclosure.

[0142] In the illustrated example, power generator 20 of the two linked RF power generators 20 and 30 is synchronized via a CEX.sub.out signal from generator 30 and additionally phase-shifted internally by ΔΦ.

[0143] FIG. 7 illustrates a functional diagram of an exemplary embodiment of an arrangement 50 of three RF power generators according to the disclosure.

[0144] In the illustrated example, a so-called daisy chain of three phase-locked power generators, e.g. the RF power generators 30, 30′, 30″, wherein 30′ and 30″ denote hardware duplicates of the power generator 30, is formed, in which each generator adds an individual phase shift ΔΦ.sub.1, ΔΦ.sub.2 via its internal digital waveform generator(s). Cable length-induced phase shifts ΔΦ.sub.c as shown in FIG. 4 are not explicitly indicated in FIG. 7, however, they may be compensated as described with FIG. 4 above. The three daisy chain-linked RF power generators 30, 30′, 30″ generate the same output frequency. Only the CEX.sub.out signals for the next generator in the chain are phase-shifted individually by each generator.

[0145] FIG. 8 shows a functional diagram of another exemplary embodiment of an arrangement 55 of several RF power generators 30, 30.sub.2, . . . 30.sub.n according to the disclosure, wherein the generators 30.sub.2 . . . 30.sub.n are hardware duplicates of the power generator 30.

[0146] In the illustrated example, a parallel combination of phase-locked generators 30.sub.2 . . . 30.sub.n of the same frequency with different phase-shifts ΔΦ.sub.i, e.g. in a star-like configuration, with one central master generator 30 is shown. All generators are synchronized via CEX signals from the master generator 30. The required phase-shifts ΔΦ.sub.i can either be implemented in the CEX signals on the master generator end or be added by the respective digital waveform generators in the slave generators 30.sub.2 . . . 30.sub.n.

[0147] In FIG. 8, the generators 30.sub.2 . . . 30.sub.n share the same CEX.sub.out signal from generator 30 without phase-shift ΔΦ towards the reference frequency at CEX.sub.in1 of the master generator 30, and add individual phase-shifts ΔΦ.sub.i internally.

[0148] It is to be noted, that cable-length induced phase-shifts are explicitly mentioned only in FIG. 4, but omitted in FIGS. 5 to 8 although they are present. In all embodiments, phaseshifts caused by cables may be compensated by using the disclosure, i. e. by adding a compensating phaseshift in the master or slave generator.

[0149] FIG. 9 shows a flow chart of an exemplary embodiment of a method for generating synchronized RF output signals RF.sub.out,i each having a respective output frequency f.sub.i, phase Φ.sub.i, and amplitude A.sub.i, according to the disclosure.

[0150] In the inner loop shown in FIG. 9, synchronization of the multiple RF output signals having different frequencies is carried out. The entire process is controlled by a process schedule or recipe with updates of the required RF output signal parameters in regular time intervals TI according to the outer loop shown in FIG. 9.

[0151] In particular, in step S100, one of the RF output signals is selected as a control loop feedback signal, e.g. feedback signal 5. In other words, the feedback signal is set to the same frequency as an external or internal precision reference frequency and an appropriate amplitude and phase offset for use as the feedback signal (PLL control signal).

[0152] In step S110, a starting or set value for the frequency tuning word FTW.sub.PLL of the feedback signal is set, e.g. selected from a lookup table.

[0153] In step S120, all other RF output signals are defined by frequency, amplitude, and phase offset. If RF output signals are supposed to vary over time, a suitable time interval for changing RF output signal parameters is determined.

[0154] In step S130, for each required frequency, frequency tuning words FTW.sub.i (i=1 . . . k) based on the frequency tuning word FTW.sub.PLL of the feedback signal is calculated according to formula given hereinabove (cf. general description of the disclosure).

[0155] In step S140, the time-dependent amplitude value sequences A.sub.i(t) for each frequency tuning word FTW.sub.i is generated via the respective DDS.sub.i cores.

[0156] In step S150, the amplitude sequences A.sub.PLL(t), A.sub.i(t) for each frequency are converted into analog signals by the multi-channel DAC.

[0157] In Step 160, the output signals are filtered by respective signal reconstruction filters F.sub.i (optionally also F.sub.PLL) to produce sinusoidal output waveforms with frequencies f.sub.PLL and f.sub.i.

[0158] In Step 170, the feedback signal f.sub.PLL is compared to the reference signal f.sub.ref and the error signal 6 is produced.

[0159] In step 180, a digitized representation 6′ of the error signal 6 is used to calculate an optimized frequency tuning word FTW.sub.PLL.

[0160] In step 190, it is checked if the predetermined time interval TI has expired. If it is not expired, the method returns to step S130 (inner loop).

[0161] Otherwise, any changes to the RF output signal parameters are carried out as required by the desired signal modulation of a plasma process, for example. Thereafter, the method continues with step S120 (outer loop).

[0162] While the disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive.

[0163] From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the art and which may be used instead of or in addition to features already described herein.

[0164] Variations to the disclosed embodiments can be understood and effected by those skilled in the art, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality of elements or steps. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0165] Any reference signs in the claims should not be construed as limiting the scope thereof.

REFERENCE NUMERALS

[0166] 1 RF power generator [0167] 2 control unit [0168] 3 signal comparator [0169] 4 reference signal [0170] 5 feedback signal [0171] 6 error signal [0172] 6′ digital representation of 6 [0173] 7 data processing unit [0174] 8 internal reference signal source [0175] 9 loop filter [0176] 10 system clock signal [0177] 11 memory device [0178] 12 control device [0179] 13 DC power supply [0180] 14 external reference signal source [0181] 20 RF power generator [0182] 21 control unit [0183] 30 RF power generator [0184] 31 user interface device [0185] 32 waveform generator clock signal/FPGA clock signal [0186] 33 DAC clock signal [0187] 35 RF power generator arrangement [0188] 40 RF power generator arrangement [0189] 45 RF power generator arrangement [0190] 50 RF power generator arrangement [0191] 55 RF power generator arrangement [0192] A amplitude [0193] A(t) time-dependent amplitude signal [0194] A.sub.PLL(t) time-dependent amplitude signal of feedback signal [0195] ADC analog-to-digital-converter [0196] CEX common exciter [0197] CEX.sub.in common exciter input [0198] CEX.sub.out common exciter output [0199] CLK system clock [0200] DAC digital-to-analog-converter [0201] DDS direct digital synthesis core [0202] DDS.sub.PLL direct digital synthesis core for feedback signal [0203] f frequency [0204] f.sub.PLL frequency of feedback signal [0205] f.sub.ref frequency of reference signal [0206] f.sub.sv frequency set value [0207] F signal reconstruction filter [0208] FPGA field programmable gate array [0209] FTW frequency tuning word [0210] FTW.sub.PLL frequency tuning word of feedback signal [0211] Φ phase [0212] Φ.sub.PLL phase of feedback signal [0213] Φ.sub.ref phase of reference signal [0214] ΔΦ phase shift [0215] ΔΦ.sub.c cable length-induced phase shift [0216] PA power amplifier [0217] PLL phase-locked loop [0218] RF radio frequency [0219] RF.sub.out radio frequency output signal