Analogue-to-digital converter (ADC)

Abstract

There is provided a dual-slope analog-to-digital converter (ADC), comprising an input signal terminal, configured to provide an analog signal, and a reference signal terminal, configured to provide a predetermined reference signal. The ADC further comprises an integrator, that is operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal. In addition, a voltage supply is operatively coupled to said integrator and configured to selectively provide at least one first supply voltage to said integrator via a second switch unit, a comparator is operatively coupled to an output of said integrator at a first comparator input and a predetermined threshold voltage at a second comparator input, configured to provide an actuation signal at a comparator output in accordance with a predetermined comparator logic, and a controller is adapted to control any one of said first switch unit and said second switch unit. The ADC is further adapted to provide a first voltage to said integrator from said voltage supply, so as to integrate over a first time period a first current corresponding to one of said reference signal and said analog signal, and, following said first time period, to provide a second voltage to said integrator from said voltage supply, so as to integrate over a second time period a second current corresponding to the other one of said reference signal and said analog signal, in order to generate a digital output signal corresponding to said analog signal, and wherein said first current and said second current flow in the same direction during respective said first time period and said second time period.

Claims

1. A dual-slope analogue-to-digital converter (ADC), comprising: an input signal terminal, configured to provide an analogue signal, and a reference signal terminal, configured to provide a predetermined reference signal; an integrator, operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal; a voltage supply, operatively coupled to said integrator and configured to selectively provide at least one first supply voltage to said integrator via a second switch unit; a comparator, operatively coupled to an output of said integrator at a first comparator input and a predetermined threshold voltage at a second comparator input, configured to provide an actuation signal at a comparator output in accordance with a predetermined comparator logic; a controller, adapted to control any one of said first switch unit and said second switch unit, and said ADC being adapted to provide a first voltage to said integrator from said voltage supply, so as to integrate over a first time period a first current corresponding to one of said reference signal and said analogue signal, and, following said first time period, to provide a second voltage to said integrator from said voltage supply, so as to integrate over a second time period a second current corresponding to the other one of said reference signal and said analogue signal, in order to generate a digital output signal corresponding to said analogue signal, and wherein said first current and said second current flow in the same direction during respective said first time period and said second time period.

2. A dual-slope analogue-to-digital converter (ADC) according to claim 1, wherein said voltage supply is configured to selectively provide at least one second supply voltage to said integrator adapted to change an existing voltage of said integrator to said second voltage.

3. A dual-slope analogue-to-digital converter (ADC) according to claim 1, wherein said first voltage is equal to said second voltage.

4. A dual-slope analogue-to-digital converter (ADC) according to claim 1, wherein said first time period is defined by said threshold voltage.

5. A dual-slope analogue-to-digital converter (ADC) according to claim 1, wherein said first voltage is different to said second voltage.

6. A dual-slope analogue-to-digital converter (ADC) according to claim 1, wherein said first time period is defined by a predetermined value.

7. A dual-slope analogue-to-digital converter (ADC) according to claim 1, wherein said second time period is defined by said threshold voltage.

8. A dual-slope analogue-to-digital converter (ADC) according to claim 5, wherein said threshold voltage is equal to said first voltage.

9. A dual-slope analogue-to-digital converter (ADC) according to claim 1, wherein said first switch unit comprises a first switch, operatively coupled between said reference signal terminal and said integrator, and a second switch operatively coupled between said input signal terminal and said integrator.

10. A dual-slope analogue-to-digital converter (ADC) according to claim 9, wherein each one of said first switch and said second switch is a Field-Effect-Transistor of a first type.

11. A dual-slope analogue-to-digital converter (ADC) according to claim 10, wherein said first type is NMOS.

12. A dual-slope analogue-to-digital converter (ADC) according to claim 11, wherein each one of said analogue signal and said predetermined reference signal is a current sink.

13. A dual-slope analogue-to-digital converter (ADC) according to claim 10, wherein said first type is PMOS.

14. A dual-slope analogue-to-digital converter (ADC) according to claim 13, wherein each one of said analogue signal and said predetermined reference signal is a current source.

15. A dual-slope analogue-to-digital converter (ADC) according to claim 1, said controller comprising a timer, operatively coupled to said comparator, and adapted to provide an oscillating signal of a predetermined frequency.

16. A dual-slope analogue-to-digital converter (ADC) comprising: an input terminal, configured to provide an analogue signal, and a reference signal terminal, configured to provide a predetermined reference signal; an inegrator, operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from an one of said input signal terminal and said reference signal terminal; a voltage supply, operatively coupled to said integrator and configured to selectively provide at least one first supply voltage to said integrator via a second switch unit; a comparator, operatively coupled to an output of said integrator at a first comparator input and a predetermined threshold voltage at a second comparator input, configured to provide an actuation signal at a comparator output in accordance with a predetermined comparator logic; a controller, adapted to control any one of said first switch unit and said second switch unit, and said ADC being adapted to provide a first voltage to said integrator from said voltage supply, so as to integrate over a first time period a first current corresponding to one of said reference signal and said analogue signal, and, following said first time period, to provide a second voltage to said integrator from said voltage supply, so as to intergrate over a second time period a second current corresponding to the other one of said reference signal and said analogue signal, in order to generate a digital output signal corresponding to said analogue signal, and wherein said first current and said second current flow in the same direction during respective said first time period and said second time period, wherein said second switch unit comprises a third switch, configured to selectively provide said first supply voltage to said integrator, a fourth switch, configured to provide a third supply voltage to said integrator, and at least a fifth switch, configured to selectively provide said second supply voltage to said integrator.

17. A dual-slope analogue-to-digital converter (ADC) according to claim 16, wherein each one of said third switch, said fourth switch and at least said fifth switch is a Field-Effect-Transistor of a first type.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Preferred embodiments of the present invention will now be described, by way of example only and not in any limitative sense, with reference to the accompanying drawings, in which:

(2) FIG. 1 (Prior Art) shows (a) a simplified schematic block diagram of a known dual-slope Analogue-to-Digital Converter (ADC) using an integrator OpAmp and (b) a corresponding integrator voltage V.sub.int output over respective time periods;

(3) FIG. 2 shows (a) a simplified schematic block diagram of a first embodiment of the ADC of the present invention and (b) a corresponding integrator voltage V.sub.int output over respective time periods when operated in a first mode;

(4) FIG. 3 shows (a) the simplified schematic block diagram of the ADC shown in FIG. 2 and (b) a corresponding integrator voltage V.sub.int output over respective time periods when operated in a second mode;

(5) FIG. 4 shows (a) a simplified schematic block diagram of an alternative embodiment of the ADC of the present invention and (b) a corresponding integrator voltage V.sub.int output over respective time periods when operated in the second mode, and

(6) FIG. 5 shows (a) a simplified schematic block diagram of yet another alternative embodiment of the ADC of the present invention and (b) a corresponding integrator voltage V.sub.int output over respective time periods when operated in the first mode.

(7) FIG. 6 shows one way to determine the unknown current i.sub.2,

(8) FIG. 7 shows another way to determine the unknown current i.sub.2,

(9) FIG. 8 shows yet another way to determine the unknown current i.sub.2,

(10) FIG. 9 shows a further way to determine the unknown current i.sub.2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

(11) The exemplary embodiments of this invention will be described in relation to dual-slope Analogue-to-Digital Converters (ADCs), and in particular to dual-slope ADCs using N-type Metal-Oxide-Semiconductor circuits with an integrating capacitor.

(12) However, it is understood by a person skilled in the art that that any other suitable integrator may be used. Further, it is understood by the person skilled in the art that P-type Metal-Oxide-Semiconductor circuits are equally suitable to provide the characterising feature of the invention, that is, currents flowing from or to the integrator are in the same direction for corresponding analogue and reference signal. Also, it is understood that the scope of the invention is not limited only to the structure of the described example embodiment(s).

(13) In addition, controllers and counters used for the operation of common dual-slope ADCs are well known in the art and are not described in any more detail. Therefore, controller and counter units, as well as, any other logic circuit that usually provided at the output of the comparator 114 (i.e. threshold detector) are not included in the accompanying schematics of the ADCs of the present invention but are assumed to be an operative part of any one of the described ADCs of the present invention.

(14) Referring now to FIG. 2, there is illustrated a first embodiment of a low-cost linear dual-slope, or integrating, ADC 100 that utilises, for example, Field-Effect-Transistors (FETs) in a unipolar process (e.g. NMOS) for at least the first switch 102 and the second switch 103 between respective signal input terminal 104 and reference input terminal 106 and the integrator 108.

(15) From the schematic block diagram in FIG. 2, the ADC 100 comprises, inter alia, an integrating capacitor C.sub.int (i.e. integrator 108) that is connected to a voltage supply rail 110 between a first voltage source V.sub.H via a third switch 111 and a second voltage source V.sub.L via a fourth switch 112. In this particular example, the voltage level of the first voltage source V.sub.H is higher than the voltage level of the second voltage source V.sub.L, but it is understood that any suitable voltage level may be applied to the integrator 108. Further, the terms “higher” and “lower” are understood in connection with voltage levels provided by the voltage supply rail 110, which is configured to provide at least one voltage source, i.e. V.sub.H or V.sub.dd, that is at a higher voltage level than the other voltage source, i.e. V.sub.L or Gnd, provided by the voltage supply rail 110.

(16) The signal input terminal 104 and the reference input terminal 106 are operably coupled to the integrator 108 via respective first and second switch 102, 103, and an output of the integrator 108 (i.e. the upper plate of the capacitor) is further coupled to an input of a comparator 114 which also has a predetermined threshold voltage 116 as its second input (V.sub.2).

(17) A third voltage source 118 is operably connected to the integrator 108 (e.g. the lower plate of the capacitor C.sub.int) via a fifth switch 120 and which is configured to selectively provide a ‘boost’ voltage (V.sub.B) 118 so as to change the voltage level of the integrator 108, for example, back to the starting voltage V.sub.1.

(18) During use (i.e. in NMOS configuration), the analogue signal to be sensed or measured may be applied to the signal input terminal 104 as a sink current I.sub.AN. In the event the analogue signal I.sub.AN is provided from a sensor 250 (see FIG. 4(a)) that does not have a current (sink) output, the analogue signal may be converted into a sink current first before it is applied to the integrator 108 via the first switch 102. In addition to the analogue signal, a known reference current I.sub.Ref is applied to the reference input terminal 106, either from an external reference or directly generated in the IC. The reference current I.sub.Ref is also applied to the integrator 108 (e.g. upper plate of the capacitor C.sub.int) as a sink current via the second switch 103.

(19) A first mode of operation is now described with reference to FIGS. 2(a) and 2(b), which shows the integrator voltage output V.sub.int over time.

(20) At the start, the first 102, second 103 and fifth switch 120 are in an open configuration, and the third 111 and fourth switch 112 are in a closed configuration, so as to charge integrator 108 between the first (higher) voltage source V.sub.H and the second (lower) voltage source V.sub.L. The charging process produces a high (starting) voltage V.sub.1 across the integrating capacitor C.sub.int. In this particular example, V.sub.1=V.sub.H−V.sub.L. At time t.sub.1, third switch 111 is then opened and second switch 103 is closed, resulting in a discharge of the integrator 108 (e.g. upper plate of C.sub.int) to the reference current sink I.sub.Ref at a first linear rate.

(21) The duration of this linear discharge is then timed by a counter or timer circuit provided with the IC (not shown) until the comparator 114 (i.e. threshold detector) senses that the voltage of the integrator 108 (e.g. the upper plate of C.sub.int) has reached threshold voltage V.sub.2. At this time, i.e. t.sub.2, the second switch 103 and the fourth switch 112 are opened, and the fifth switch 120 is closed. This configuration connects integrator 108 (e.g. the lower plate of capacitor C.sub.int) to the third voltage source 118 so as to provide a ‘boost’ voltage V.sub.B.

(22) In case the ‘boost’ voltage V.sub.B is chosen such that V.sub.B=(V.sub.1−V.sub.2), then the voltage of the integrator 108 (e.g. the voltage at the upper plate of capacitor C.sub.int) is quickly raised back to V.sub.1, as V.sub.2+(V.sub.1−V.sub.2)=V.sub.1. At this point (i.e. t.sub.2 in the timing diagram of FIG. 2(b)), first switch 102 is closed, resulting in a discharge of the integrator 108 (e.g. the upper plate of capacitor C.sub.int) to the analogue current sink I.sub.AN. The discharge is at a second linear rate corresponding to the magnitude of the analogue current sink I.sub.AN. As with the integration of the reference current I.sub.Ref, the duration of this discharge is timed until the comparator 114 (i.e. threshold detector) senses that the voltage of integrator 108 (e.g. voltage at upper plate of capacitor C.sub.int) has again reached threshold voltage V.sub.2. At this point, with time periods (t.sub.2−t.sub.1) and (t.sub.3−t.sub.2), as well as, reference current I.sub.Ref known, it is possible to work out the magnitude of I.sub.AN using the following equation:

(23) $\begin{array}{cc}{I}_{\mathrm{AN}}=\frac{I_{\mathrm{REF}}.Math.\left(t_2-t_1\right)}{\left(t_3-t_2\right)};& \left(\mathrm{Eq}.2\right)\end{array}$

(24) In the voltage output V.sub.int diagram illustrated in FIG. 2(b), it is understood that time t.sub.2, at which first switch 102 is closed, may be in reality t.sub.2′, which includes a short delay required by any one or any combination of the components of the ADC 100 to establish the switched voltages (e.g. V.sub.1) or other settling or noise reduction steps.

(25) A second mode of operation is now described for the first embodiment with reference to FIGS. 3(a) and 3(b), which shows the integrator voltage output V.sub.int over time.

(26) In this case, the first (higher) voltage source V.sub.H is equal to the threshold voltage V.sub.2 116 and the second (lower) voltage source V.sub.L is a ground reference, i.e. V.sub.L=0V.

(27) At the start, first switch 102, second switch 103 and fifth switch 120 are in an open configuration, and third switch 111 and fourth switch 112 are in a closed configuration, establishing threshold voltage V.sub.2 at the integrator 108 (i.e. integrating capacitor C.sub.int) (V.sub.H−V.sub.L=V.sub.2). At time t.sub.1, third switch 111 is opened and second switch 103 is closed, resulting in a discharge of the integrator 108 (e.g. the upper plate of C.sub.int) to the reference current sink I.sub.Ref at a first linear rate. The duration of this linear discharge period is predetermined, i.e. it is set by a timer.

(28) At time t.sub.2 (i.e. after the set time has passed), the integrator 108 (e.g. the upper capacitor C.sub.int plate) voltage has decreased to a voltage level V.sub.4 and second switch 103 and fourth switch 112 are opened, wherein the fifth switch 112 is closed. This configuration connects the integrator 108 (e.g. the lower plate of capacitor C.sub.int) to the third voltage source 118 so as to provide ‘boost’ voltage V.sub.B.

(29) The applied ‘boost’ voltage V.sub.B raises the integrator voltage (e.g. the voltage at upper plate of capacitor C.sub.int) to a voltage level V.sub.5. Here, V.sub.5=V.sub.4+V.sub.B. First switch 102 may then be closed to discharge the integrator 108 (e.g. the upper plate of C.sub.int) to the analogue current sink I.sub.AN. The duration of the discharge is timed until the comparator 114 (i.e. threshold detector) detects when the integrator voltage (e.g. voltage at upper plate of C.sub.int) has decreased to threshold voltage V.sub.2 (e.g. at time t.sub.3).

(30) Respective time periods t.sub.2−t.sub.1 (which is pre-set) and t.sub.3−t.sub.2 (which is determined using a counter prompted by the comparator 114) are known. Voltage V.sub.4 may be measured or calculated from known reference current I.sub.Ref, known pre-set time period t.sub.2−t.sub.1 and known integrator characteristics (e.g. capacitor C.sub.int properties). Consequently, unknown analogue current sink I.sub.AN may then be calculated from voltage V.sub.5−V.sub.2, time period t.sub.3−t.sub.2 and the known integrator characteristics (e.g. capacitor C.sub.int properties).

(31) It is understood by the person skilled in the art that ‘boost’ voltage V.sub.B and threshold voltage V.sub.2 may be selected so as to provide a suitable dynamic range, as well as, convenience. In one particular example threshold voltage V.sub.2 may be chosen to be half of a high supply voltage V.sub.dd, whilst ‘boost’ voltage V.sub.B may be chosen to be a quarter of the same high supply voltage V.sub.dd.

(32) FIG. 4(a) and (b) illustrate a second, alternative embodiment of the present invention, where both voltages V.sub.B and V.sub.2 are generated through suitable voltage dividers that are provided across the IC's voltage supply rail 110.

(33) As will be apparent to those skilled in the art, other modes of operation are possible.

(34) For example, the second embodiment shown in FIG. 4(a) provides another suitable circuit 200 for implementing the ADC of the present invention. The applied mode of operation relates closely to the second mode of operation described for the embodiment shown in FIG. 3(a).

(35) During operation, an analogue signal is first converted from an external signal, for example, from sensor 250, to a desired current magnitude I.sub.AN (e.g. a current sink 204), for example by using a current mirror 202 that may be formed from transistors T1 and T2. Both, the initial high reference voltage (here V.sub.2 at time t.sub.1) applied to the integrator 208 (e.g. the top plate of C.sub.int) and the voltage threshold V.sub.2 for triggering the end of the second integrator 108 discharge period (i.e. at time t.sub.3), are provided by a voltage divider that is formed from a resistor network comprising resistor 216 and two further resistors 218, each one of the two resistors 218 having a resistance that is equal to one half (i.e. ½) of the resistance provided by resistor 216. The resistor network is connected in series between the higher voltage source V.sub.dd and the lower voltage source Gnd of the voltage supply rail 210.

(36) In this particular example, the high reference voltage (V.sub.2) and voltage threshold V.sub.2 is equal to one half (i.e. ½) of the potential difference between the higher and lower voltage sources, i.e. (V.sub.H−V.sub.L)/2=V.sub.dd/2. In addition, the required ‘boost’ voltage V.sub.B is provided via fifth switch 220 by a different tap from the ADC's voltage divider. Here, V.sub.B is a quarter (i.e. ¼) of high supply V.sub.dd. However, it is understood by the skilled person that other suitable voltage levels may be used when operating the ADC 200.

(37) FIG. 5(a) and (b) illustrates yet another, third embodiment of the ADC of the present invention. In particular, the ADC 300 is a specific, simplified variant of the first embodiment illustrated in FIG. 2(a). This simplified approach uses the high voltage source V.sub.H to also provide the ‘boost’ voltage source V.sub.B directly to the integrator 308 (e.g. to the upper plate of capacitor C.sub.int) via third switch 311.

(38) This third embodiment 300 of the ADC of the present invention may be used in the first mode of operation, where the initial part of the cycle is similar to the cycle described for the first embodiment 100 (see FIGS. 2(a) and (b)) with V.sub.1 being the initial high starting voltage at t.sub.1 (provided from V.sub.H of the voltage supply rail). However, at the end of the first discharge period to current sink I.sub.Ref (at t.sub.2), i.e. when the comparator 314 (threshold detector) senses that the voltage of the integrator 308 (e.g. the upper plate of C.sub.int) has reached threshold voltage V.sub.2 (or, when a pre-set time t.sub.2 has been reached, if used in the second mode of operation), the second switch 303 and the fourth switch 312 are opened, but third switch 311 is closed, so as to connect the integrator 308 (e.g. the upper plate of capacitor C.sub.int) to the higher voltage source V.sub.H. Since V.sub.H=V.sub.1 the rest of the cycle may continue according to the first or second mode of operation (i.e. measuring the time t.sub.3 when the comparator 314 senses that the voltage of the integrator 308 has reached threshold voltage V.sub.2).

(39) From the embodiments and mode of operations described, it is understood by the person skilled in the art, that the order of the discharge ramps (i.e. for I.sub.Ref and I.sub.AN) is irrelevant. For example, first switch 102, 202, 302 may be closed first to discharge the integrator 108, 208, 308 to the analogue current sink I.sub.AN, before opening second switch 103, 203, 303 to discharge the integrator 108, 208, 308 to the reference current sink I.sub.Ref. Further, switch timings described above are simplified and delays between certain switch operations may be introduced without affecting accuracy, for example, to reduce noise, as would be appreciated by one skilled in the art. Further, as mentioned before, the various embodiments of the ADC of the present invention may be effected utilising either one of NMOS and PMOS. It is understood by the person skilled in the art that, when used with PMOS, analogue signal and reference signal will be a current source (i.e. current flowing towards the integrator). Further, the modes of operation of the various ADC embodiments described herein are illustrative and components of those modes may be mixed as desired. For example, the decision as to whether a particular integrator discharge (or charge) period is determined by a predetermined time or by detection of a voltage threshold crossing is in the hands of the circuit designer. Similarly, the choices of supply voltage(s) (e.g. V.sub.H, V.sub.L, V.sub.B, etc.) and threshold voltage(s) (V.sub.2, etc.) may be made freely within the constraints of the IC technology and wider circuit design.

(40) It will be appreciated by persons skilled in the art that the above embodiment(s) have been described by way of example only and not in any limitative sense, and that various alterations and modifications are possible without departing from the scope of the invention as defined by the appended claims.

(41) Calculation for the ADC are based on the conservation of the charge
Q−CV=IT

(42) For the dual-slope ADC of the prior art, it is important that the start voltage level and the end voltage level are the same (no error). The equations for determining the unknown current i.sub.2 are shown in FIG. 6.

(43) For dual-slope ADC of the invention (first embodiment with separate ‘boost ’ voltage V.sub.B) and when operated in the first mode operation. The equations for determining the unknown current i.sub.2 are shown in FIG. 7.

(44) For dual-slope ADC of the invention (first embodiment with separate ‘boost ’ voltage V.sub.B) and when operated in the second mode operation. Here, an unknown V.sub.Bhas been introduced, which has to ensure that voltage level returns to above V.sub.2. The equations for determining the unknown current i.sub.2 are shown in FIG. 8.

(45) For dual-slope ADC of the invention (second embodiment with ‘boost ’ voltage V.sub.Bfrom V.sub.dd via the third switch 311) and when operated in the first mode operation. In this case, V.sub.1 is chosen to be a known voltage such as V.sub.dd making it easy to return to V.sub.1. The equations for determining the unknown current i.sub.2 are in FIG. 9.