METHOD OF MEASURING TIMING HOLDOVER PERFORMANCE IN AN R-PHY SYSTEM

Abstract

Systems and methods for measuring the amount of drift of a clock in a remote device relative to a clock in a core, both in a distributed access architecture, by measuring the change in fullness of a dejitter buffer in the remote device that holds data provided from the core.

Claims

1. A remote device in a distributed access architecture of a communications network, the remote device operatively connected to a core providing data to the remote device, the remote device including a dejitter buffer and a processor configured to measure sequential values, each value representing an instantaneous fullness state of the dejitter buffer, and use the values to determine a magnitude of drift of a first clock of the remote device relative to a second clock of the core.

2. The remote device of claim 1 comprising an RPD.

3. The remote device of claim 1 including a low pass filter that filters the sequential values.

4. The remote device of claim 3 where the low pass filter blocks variations in the sequential values due to network jitter.

5. The remote device of claim 3 where the output of the low pass filter is used to determine a sequence of fractional frequency offset values.

6. The remote device of claim 5 where the processor accumulates the sequence of fractional frequency offset values to provide an accumulated value and compares the accumulated value to a threshold.

7. The remote device of claim 6 where the remote device provides an alert based on the comparison.

8. A method comprising: measuring sequential values representing a fullness state of a dejitter buffer of a first network device having a first clock; and using the sequential values to determine a magnitude of drift of the first clock relative to a second clock associated with a second device providing data to the dejitter buffer.

9. The method of claim 8 where the first network device is at least one of a remote physical device (RPD) and a remote MACPHY device (RMD).

10. The method of claim 8 including applying a low pass filter to the sequential values.

11. The method of claim 10 where the low pass filter blocks variations in the sequential values due to network jitter.

12. The method of claim 10 where the output of the low pass filter is used to determine a sequence of fractional frequency offset values.

13. The method of claim 12 including accumulating the sequence of fractional frequency offset values to provide an accumulated value.

14. The method of claim 13 including comparing the accumulated value to a threshold.

15. The method of claim 14 including providing an alert based on the comparison.

16. A method comprising: repeatedly measuring a fullness state of a buffer to provide a first sequence of values; low pass filtering the first sequence of values to provide a second sequence of values; accumulating a rate of change of the second sequence of values to provide an output signal; and providing an alert when the outputs signal exceeds a threshold.

17. The method of claim 16 implemented in a remote device in a distributed access architecture of a communications network.

18. The method of claim 17 where the buffer is a dejitter buffer.

19. The method of claim 18 where the dejitter buffer receives data from a video core.

20. The method of claim 19 where the alert signals that a drift of a clock of the remote device has drifted relative to a clock of the core by an amount exceeding a threshold.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

[0013] FIG. 1 shows an exemplary traditional HFC architecture having video EQAM units, which package MPTS transport streams to send to downstream nodes.

[0014] FIG. 2 shows an exemplary architecture that includes a plurality of cores, that each send data and/or video to a remote physical device (RPD).

[0015] FIG. 3A shows an exemplary system where the video/CCAP core of FIG. 2 transmits video data to the RPD in sync mode.

[0016] FIG. 3B shows an exemplary system where the video/CCAP core of FIG. 2 transmits video data to the RPD in async mode.

[0017] FIG. 4 shows an exemplary method according to some embodiments of the present disclosure.

[0018] FIG. 5 shows an exemplary apparatus that provides input data for the method of FIG. 4.

DETAILED DESCRIPTION

[0019] The disclosed systems and methods will be described using a distributed access architecture that provides video and data, but those of ordinary skill in the art will appreciate that the disclosed embodiments may be used in other synchronized architectures that are subject to holdover, and that provide data to a remote device that is stored in a dejitter buffer.

[0020] As noted previously, video EQAM (VEQ) devices are used to receive a large number of channels of video, and output an RF-modulated (i.e., QAM or quadrature amplitude modulated) signal combining the multiple different channels that the VEQ receives. FIG. 1, for example, shows a traditional architecture 10 by which an HFC network 12 includes a head end 14 that delivers content to subscriber equipment 24 as subscriber premises, shown in the figure as a cable modem but those of ordinary skill in the art will understand that subscriber equipment could include set-top boxes, gateways, wireless phones, computers, etc.

[0021] The HFC network 12 includes a head end 14, a plurality of hubs 20, and associated with each hub, a plurality of nodes 22 and a plurality of subscriber equipment 24 such as cable modems. The head end 14 typically includes a cable modem termination system (CMTS)13 and a plurality of video EQAM units 16. Each of the nodes 22 has one or more corresponding access points, and each subscriber may have one or more corresponding network elements 24, shown in FIG. 1 as a cable modem.

[0022] As also noted previously, in these traditional HFC architectures 10, video is modulated onto the RF network by VEQs 16, which receives Internet-Protocol (IP) encapsulated Single & Multiple Program Transport Streams (SPTSs & MPTSs) from various sources (content providers, etc.) through content delivery network 26. The content delivery network is typically a switching network by which packetized IP data is routed from one address to another and may exhibit unpredictable and variable delays in the packets received. Therefore, the VEQ 16 preferably removes this jitter from the network ingress stream before mapping and modulating the video data onto a plurality of QAM channels. As also noted earlier, to deliver an MPTS stream onto a QAM channel in accordance with ISO 13818-1 requires that the VEQ recover the ingress Program Clock Reference (PCR) values encoded within each transport stream and re-stamp it with the VEQ's internal 27 MHz clock so that all streams are delivered with the same time base.

[0023] FIG. 2 shows an alternate distributed access architecture (DAA) in which some of the functionality of the VEQ is moved to a node. Specifically, FIG. 2 shows what is known as n Remote-Physical Architecture (R-PHY) 50 in which one or more of cores, such as a CCAP core 54a, a video core 54b, an OOB core 54c, etc., send data to a Remote Physical Device (RPD) 56, which is in turn connected to one or more “consumer premises equipment (CPE) devices 18 such as a set-top box, cable modem, etc. Though an R-PHY architecture is illustrated in FIG. 2, it should be understood that the description herein may be equally applicable to other DAA architectures, such as R-MACPHY architectures, for example. In some embodiments, a timing grandmaster device 52 may be available to provide timing information to both the video/CCAP/OOB cores 54a-54c and the RPD 56. Specifically, the timing grandmaster 52 has a first master port 60a connected to slave clocks 62 in the CCAP core 54 and a second master port 60b connected to slave clock 64 in the RPD 56, though alternatively the respective slave clocks 64 of the core 54a-54c and the RPD 56 may both be connected to a single master port in the timing grandmaster device 52. The cores 54a-54c may be connected to the timing grandmaster 52 through one or more switches 66 while the RPD 56 may be connected to the timing grandmaster 52 through one or more switches 68. Although FIG. 2 shows only one RPD 56 connected to the timing grandmaster 52, many such RPDs may be simultaneously connected to the grandmaster 52, with each RPD having a slave clock 64 receiving timing information from a port 60b in the grandmaster clock 52.

[0024] Even though the architecture of FIG. 2 shows a common grandmaster device 52 capable of synchronizing the video/CCAP/OOB cores 54a-54c to the RPD 56, the architecture of FIG. 2 may be also configured to operate asynchronously with respect to video data, where the grandmaster device 52 does not send common timing information to the RPD 56 relative to the video core 54b. For example, the RPD 56 may be configured to operate asynchronously if the video core 54b does not support IEEE1588 timing protocols, or if the RPD 56 is desired to be more resilient to holdover periods in the case the RPD and/or the core loses connection to the timing grandmaster and a specified threshold amount of drift is exceeded. Moreover, in an R-MACPHY system, an RMD will typically be set to async mode by default to eliminate the need for 1588 timing, since DOCSIS services do not need it although the RMD may be switched to sync mode if other services such as wireless backhaul requires IEEE 1588 services, or if the oscillator of the video core 54b is of poor quality and needs an external timing source. Therefore, the system shown in FIG. 2 may be configured to either operate in sync mode or in async mode to process video content, and the video core 54b and RPD (RMD) 55 each therefore may in some embodiments include hardware capable of operating in either mode, with software that enables configuration by a video core of itself and connected downstream devices into either alternate one of these modes when setting up video channels.

[0025] In sync (synchronous) mode, the RPD (or RMD) and its video core 102 are synchronized in time to the same reference clock. In this sync mode, the RPD is required to detect lost video packets using the Layer 2 Tunneling Protocol v. 3 (L2TPv3) sequence number monitoring, and insert MPEG null packets for each missing packet. FIG. 3, for example, shows a system in a configuration 100 where a video core 102 communicates with an RPD 104 in synchronous mode using a common grandmaster timing server 106. The timing server 106 maintains an identical timing lock (i.e. frequency and phase) with both the clock 108 in the video core 102 and the clock 110 in the RPD 104. The video core 102 has a video streamer 112 that forwards video data packet to the RPD 104 via a Downstream External PHY Interface (DEPI) using L2TPv3. The video packets sent from the video core 102 to the RPD 104 will typically include all information necessary to decode the packetized elementary video transport stream, such as Program Identifiers (PIDs), Program Clock Reference (PCR) data, etc.

[0026] The RPD 110 in turn, receives the video packets sent from the video core 108 in a dejitter buffer 116 of a processing device 114. The dejitter buffer 116 receives and outputs packet data at a rate that removes network jitter resulting from differing paths of received packet data, or other sources of varying network delay between the video core and the RPD. Because some packets sent by the video streamer 112 may be lost or misplaced during transport to the RPD 104, the packets output from the dejitter buffer 116 may preferably be forwarded to a module 118 that, in the case of sync mode, inserts null packets in the data stream to account for those lost packets, so as to maintain the proper timing rate of the transmitted video. The transport stream, with any necessary insertion of null packets is then forwarded to a PHY device 120, which may decode the packetized elementary stream into a sequence of decoded video frames for downstream delivery to end-users by outputting QAM-modulated data in a format expected by customer-premises equipment, like set-top boxes. Alternatively, the PHY device may simply forward the packetized data, without decoding, to e.g., a cable modem for decoding by a user device such as a computer, tablet, cell phone, etc.

[0027] In sync mode, because the RPD 104 and its Video Core 102 must be synchronized to the same reference clock, the frequency of the PCR clock contained within the ingress MPTS matches that of the local clock on the remote device. Therefore, there is no frequency offset on the RPD between the ingress and egress streams, and as noted earlier, to maintain proper timing information in the video data being transmitted, the RPD 104 need only remove network jitter, detect lost video packets using the L2TPv3 Sequence number monitoring, and insert MPEG NULL packets for each missing packet.

[0028] Alternatively, however, the RPD and video core may be configured to operate in an asynchronous (async) mode. In async mode, the RPD 104 and its video core 102 are not synchronized in time to the same reference clock. Instead, the RPD 104 is required to detect the difference between its own clock 110 and the clock 108 of the video core 102 and be able to either insert or remove MPEG packets as necessary to maintain expected MPEG bitrate, and also adjust the MPEG PCR values due to the removal/insertion of the MPEG packets.

[0029] FIG. 3B, for example, shows the hardware of FIG. 2 configured to instead operate in async mode. In this configuration 101, the clock 108 of the video core 102 and the clock 110 of the RPD 104 are not synchronized and may therefore drift relative to each other. The video streamer 112 of the video core 102 forwards packets of the packetized video data elementary stream to the RPD 104, which again receives the data in dejitter buffer 116 to remove network jitter, as described previously. However, unlike the configuration of FIG. 2, the packets output from the dejitter buffer 116 are forwarded to the module 118 which both adds null packets when needed, and drops packets when needed, in order to maintain the proper constant bit rate of the data received from the dejitter buffer 116.

[0030] Further, because the RPD and its video core are not synchronized in time to the same reference clock, the frequency of the PCR in the ingress MPTS will be offset from that of local RPD clock. Thus, as well as performing the above functions common to those performed in sync mode, the RPD must also detect the magnitude of the frequency offset from the video core and correct for it. To this end, after packets are added/dropped as needed, a PCR module 119 re-stamps the video packets with updated PCRs due to the removal/insertion of MPEG packets before forwarding the re-stamped packets to the PHY device 120.

[0031] As noted previously, in distributed access architectures, the remote device such as an RPD is typically configured to operate in sync mode with respect to a video core, where the RPD and video core maintain a timing lock, and synchronization must be maintained by both frequency and phase in order for DOCSIS time scheduling to properly function. Also, the remote device such as an RPD is configured to maintain a timing lock with data cores, such as CCAP core 54a and OOB core 54c in FIG. 2. For example, the Remote DTI (R-DTI) specification requires that an RPD and CCAP core to be phase aligned with less than 1 ms difference and the R-PHY specification specifies IEEE-1588 as the method to perform this frequency and phase synchronization in a R-PHY system.

[0032] While the remote device and the core(s) maintain a timing lock, no significant difficulties arise; however, problems occur whenever the remote device or the core loses connection to a common timing source, such as a grandmaster timer or otherwise lose synchronization with each other. In this instance the RPD enters what is called “holdover” where the remote device will drift in frequency and phase relative to the core(s). The magnitude of this drift is dependent on many factors such as temperature variations, internal oscillator performance, etc. For example, an RPD with a typical TCXO oscillator might drift 1 ms in phase within few hours, and in a worst case scenario, even in several minutes. With respect to video delivery, an RPD in holdover may simply switch operation to async mode. However, when the phase difference between a clock of a remote device and that of its core grows too large during holdover, cable modems may go offline, and therefore the R-DTI specification provides for a notification from a remote device such as an RPD when its drift during holdover exceeds a specified threshold.

[0033] Usually, holdover issues are addressed by attempting to improve holdover performance either through use of a better oscillator or having frequency assistance from the network (SyncE) to avoid frequency drift. However, both of these solutions are costly both in power and price. In addition, SyncE requires that the network support it, which in many cases is not present.

[0034] As just noted, the R-DTI specification provides for a notification from a remote device such as an RPD when its drift during holdover exceeds a specified threshold, but this specification does not provide a mechanism for how the RPD should detect the magnitude of its drift. Ordinarily, a device in holdover is not able to measure the magnitude of its own drift, since it lost its time reference, and therefore the typical method to determine the amount of drift is to simply presume that the remote device has crossed the threshold after a predetermined time has passed during holdover, the amount of time based on the hardware characteristics of the clock or oscillator in the remote device.

[0035] The present disclosure provides a novel mechanism by which a remote device may measure the amount of drift that has occurred during holdover, in real time. Specifically, the embodiments disclosed in this specification take advantage of the fact that, even though data services cannot operate indefinitely without synchronization to the date core, video services can. Accordingly, the present specification describes embodiments that allow a remote device such as an RPD to detect a fractional frequency offset relative to a core by detection and analysis of fluctuations in the bitrate of incoming video or other data streams from the video core while in holdover. The video stream from the video core in a distributed architecture is preferably configured to transmit video data at constant bitrate (CBR) based on the video core clock e.g., a 27 MHz MPEG clock (which is locked to the reference clock in synchronous mode).

[0036] On the assumption that the data core, such as core 54a or 54c of FIG. 2, is still locked to the reference clock while the RPD is in holdover, and while the RPD operates in async mode during holdover (either because the RPD id configured to operate in async mode or because the RPD switches to async mode upon entering holdover from sync mode), any frequency drift between that assumed frequency of the MPEG clocks and the remote device will be reflected by bit rate fluctuations of the video stream as detected by the remote device, which for purposes of this specification will be presumed to be an RPD but those of ordinary skill in the art will realize that it may be another remote device, such as an RMD.

[0037] The RPD preferably includes a video dejitter buffer such as the buffer 116 of FIG. 3 that can hold at least 10 ms of video packets. When the RPD and the video core clocks are synced, any fluctuations in the buffer depth are caused by network jitter. When the RPD and the video core are not in sync due to the RPD going into holdover, the clock drift in the RPD will result in additional fluctuations of the buffer depth. However, the network fluctuation caused by network jitter is much higher in frequency that fluctuations caused by frequency drift; therefore, the RPD can perform low pass filtering (LPF) techniques to filter out the fluctuations caused by network jitter. What remains is fluctuations that represents drift.

[0038] Thus, in preferred embodiments, the disclosed systems and methods may include a remote device that measures buffer depth fluctuations, applies a low pass filter to those fluctuations, and uses the filtered results to calculate the bitrate difference between the nominal configured bitrate and the actual bitrate of the video stream and derive the fractional frequency offset between its own clock and the PCR clock of the incoming MPEG stream.

[0039] As already noted, network jitter is removed by using a ‘dejitter’ buffer 116 shown in FIG. 3. This dejitter buffer 116 is preferably filled initially to its mid-point as the MPTS stream delivery starts. Dejitter is usually accomplished using a low-pass filter that averages delays over a sufficiently-long interval, hence the dejitter buffer 116 is preferably sized large enough to absorb the fluctuations in the buffer depth caused by jitter on the ingress stream without underflowing or overflowing.

[0040] Frequency differences between the ingress PCR and the local RPD clock (i.e. the egress rate) will manifest as a drift on the de-jitter buffer depth after low-pass filtering. This will produce the drift rate of the queue depth caused by the frequency offset. This drift rate is directly proportional to the offset between frequencies of the ingress PCR and that of the local clock of the remote device. Specifically, ingress frequency Fi is directly proportional to the ingress bitrate Bi

F.sub.iαB.sub.i

and the output frequency Fo is directly proportional to the egress bitrate Bo

F.sub.0αB.sub.0

where the differential between the ingress and egress frequencies is expressed in terms of a dimensionless parts-per-billion (PPM) frequency offset.

[00001]$\frac{F_1-F_0}{F_0}\times {10}^9=\Delta \mathrm{ppb}.$

[0041] The rate of change of the buffer depth is also proportional to the bitrate difference dB/dt. Therefore,

[00002]$\begin{array}{cc}\frac{dB}{\mathrm{dt}}=\frac{\Delta \mathrm{ppb}}{{10}^9}\mathrm{Bi}.& \left(\mathrm{Eqn}.1\right)\end{array}$

[0042] Knowing the fractional frequency offset is not sufficient due to the cumulative effect of the frequency drift on the phase drift. Accordingly, in preferred embodiments, the RPD will measure the Fractional Frequency Offset (FFO) rapidly (e.g., every few seconds) and perform an integral function on all the FFO measurements to estimate the total phase drift. It should be noted that the FFO value can be positive or negative.

Phase Drift=∫.sub.0.sup.t(FFO)dt   (Eqn. 2)

Once the estimated phase drift crosses a predefined threshold, the RPD can send out a notification that its holdover is out of specification.

[0043] FIG. 4 shows an exemplary method 150 that implements the foregoing procedure. The method 150 is preferably implemented in, or upon data recovered from, a remote device in a distributed access architecture. For example, in one embodiment, the method 150 may be implemented in a processing device housed within an RPD 104 such as is shown in FIG. 3. In alternative embodiments, some or all of the steps shown in FIG. 4 may be implemented in a server based on data collected from a remote device, such as the RPD 104 of FIG. 3.

[0044] At step 152 a fractional frequency offset (FFO) value is determined. At step 154 the determined value is added to an accumulator, i.e., a function that accumulates prior FFO values. At step 156 it is determined whether the accumulated value exceeds a threshold. Those of ordinary skill in the art will appreciate that appropriate values for the threshold will change depending on, for example, the accuracy of hardware such as an oscillator in a remote device such as RPD 104. If the threshold has been exceeded, then at step 158 a notification is sent. If the accumulated value determined at step 156 does not exceed the appropriate threshold, the method returns to step 152 and another FFO value is determined, added to an accumulator at step 154 and so forth.

[0045] FIG. 5 shows one preferred system for outputting FFO values. FIG. 5 shows an embodiment having the processing device 114 of FIG. 3, along with its dejitter buffer 116. A Buffer Depth Measurement Unit 132 receives data from the dejitter buffer 116 comprising a series of measurements representing a time series of values of the depth of the dejitter buffer 116 i.e., how full the dejitter buffer 116 is. The output of Buffer Depth Measurement Unit 132 is then preferably provided to a low pass filter 134 configured to filter out the high-frequency variations in buffer depth due to network jitter. The output of the low pass filter 134 then is provided to unit 136 that computes a sequence of FFO values used in the method of FIG. 4. The sequence of FFO values are calculated as the rate of change (positive or negative) of the filtered output of the low pass filter 134 as previously described.

[0046] It will be appreciated that the invention is not restricted to the particular embodiment that has been described, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims, as interpreted in accordance with principles of prevailing law, including the doctrine of equivalents or any other principle that enlarges the enforceable scope of a claim beyond its literal scope. Unless the context indicates otherwise, a reference in a claim to the number of instances of an element, be it a reference to one instance or more than one instance, requires at least the stated number of instances of the element but is not intended to exclude from the scope of the claim a structure or method having more instances of that element than stated. The word “comprise” or a derivative thereof, when used in a claim, is used in a nonexclusive sense that is not intended to exclude the presence of other elements or steps in a claimed structure or method.