MEMORY DEVICES SUPPORTING READ/MODIFY/WRITE MEMORY OPERATIONS INVOLVING BOTH VOLATILE MEMORY AND NONVOLATILE MEMORY

Abstract

Exemplary apparatus includes a nonvolatile memory, a volatile memory separate from the nonvolatile memory, and a controller configured to access the volatile memory and the nonvolatile memory. Exemplary volatile memory is configured to function as a read/write cache. The controller may be configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory. Exemplary devices may have a host interface and may include a data connection configured to perform double data rate data transfer. Exemplary volatile memory may support byte-granularity memory read operations, and the density of the volatile memory may be substantially less than the density of the nonvolatile memory.

Claims

1. An apparatus comprising: a nonvolatile memory; a volatile memory separate from the nonvolatile memory, wherein the volatile memory is configured to function as a read/write cache; and a controller configured to access the volatile memory and the nonvolatile memory, the controller configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory, wherein the device has a host interface and the device further comprises a data connection configured to perform double data rate data transfer; wherein the volatile memory supports byte-granularity memory read operations; and wherein the density of the volatile memory is substantially less than the density of the nonvolatile memory.

2. A device comprising: a nonvolatile memory; a volatile memory separate from the nonvolatile memory, wherein the volatile memory is configured to function as a cache; and a controller configured to access the volatile memory and the nonvolatile memory, the controller configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory.

3. The device of claim 2, wherein the device has a host interface and the device further comprises a data connection configured to perform double data rate data transfer.

4. The device of claim 2, wherein the volatile memory supports byte-granularity memory read operations.

5. The device of claim 2, further comprising an address decoder and an energy storage device.

6. The device of claim 5, wherein the address decoder is distinct from the controller.

7. The device of claim 2, wherein the cache is used as a static random access memory for more than one page of memory of the nonvolatile memory.

8. The device of claim 2, wherein the controller includes an address generator.

9. The device of claim 2, wherein the controller includes read/write combination control logic.

10. The device of claim 2, wherein the controller includes an audio interface.

11. The device of claim 2, wherein the controller includes a video interface.

12. The device of claim 2, wherein the density of the volatile memory is substantially less than the density of the nonvolatile memory.

13. The device of claim 2, wherein the density of the volatile memory is less than 10% of the density of the nonvolatile memory.

14. The device of claim 2, wherein the volatile memory includes a register that is used in connection with the read/modify/write memory operation.

15. The device of claim 2, wherein the nonvolatile memory operates in parallel with and concurrently with respect to the volatile memory.

16. An apparatus comprising: a nonvolatile memory; a volatile memory separate from the nonvolatile memory, wherein the volatile memory is configured to function as a read/write cache; and a controller configured to access the volatile memory and the nonvolatile memory, the controller configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory, wherein the device has a host interface and the device further comprises a data connection configured to perform double data rate data transfer; wherein the volatile memory supports byte-granularity memory read operations; wherein the density of the volatile memory is substantially less than the density of the nonvolatile memory; and wherein the nonvolatile memory is configured to operate in parallel with and concurrently with respect to the volatile memory.

17. The device of claim 16, wherein the cache is used as a static random access memory for more than one page of memory of the nonvolatile memory.

18. The device of claim 16, wherein the controller includes read/write combination control logic.

19. The device of claim 16, wherein the density of the volatile memory is less than 10% of the density of the nonvolatile memory.

20. The device of claim 16, wherein the controller is configured to perform a read page as volatile memory command and to perform a write page as volatile memory command.

21. The device of claim 16, wherein the controller is configured to perform a read byte level command and to perform a write byte level command.

22. The device of claim 16, wherein the controller is configured to perform a command to read a page in the volatile memory of a particular block of the nonvolatile memory.

23. The device of claim 16, wherein the controller is configured to perform load/store operations with respect to the volatile memory and an assigned block of the nonvolatile memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

[0008] FIG. 1 is a diagram showing a nonvolatile memory system with features as described for the present invention.

[0009] FIG. 2 shows an exemplary NAND memory integrated circuit as one element of the NVMS (nonvolatile memory system).

[0010] FIG. 3 shows various components of a controller for the nonvolatile memory system (NVMS) of this invention.

[0011] FIG. 4 shows a novel implementation of block erase per this invention.

[0012] FIG. 5 shows a flash memory controller with block erase feature.

[0013] FIG. 6 shows a current NAND flash chip architecture by Samsung.

[0014] FIG. 7 shows a pin out for a 1 Gb Samsung flash memory.

[0015] FIG. 8 shows some operational features of the above Samsung flash memory.

[0016] FIG. 9 shows how the invention of this patent distinguishes itself from today's nonvolatile memory.

[0017] FIG. 10 shows improved features of this invention compared to currently available (commercial) multichip NVMS solutions.

[0018] FIG. 11 shows how the “random access memory” of this invention can be implemented in dual port access for enhanced performance.

[0019] FIG. 12 shows a high level architecture of the NVMS of this invention which comprises both nonvolatile and volatile memory.

DETAILED DESCRIPTION

[0020] Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout, the various views and embodiments of nonvolatile memory systems with embedded fast read and write memories are illustrated and described, and other possible embodiments are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations based on the following examples of possible embodiments.

[0021] Each NAND flash memory commercially available (in various pin outs/densities) today has a 512 B-1 KB-2 KByte page in a 64 Kb to 128K Byte block (a block contains at least one sector), 64 rows worth of data, 1 page/sector. To write one page takes about 200 μs. There are about 1,024 sectors in a 1 Gbit flash (NAND). So each NAND flash chip has 1 Mb SRAM (1 k pages). The invention requires each page to have “bit-to-bit” NVM back up (nonvolatile SRAM). So a page can be copied directly to the NVM as needed. This additional row can be in the sector itself. Address/control logic to accommodate this page can be easily done in the sector, if needed.

[0022] Page invention—Modify page as shown in Samsung K9F1G08R0A (1 Gbit NANDflash). In the Samsung device, Page is approximately 2 KByte+64 bits (for some kind of Ecc) in each 128 KByte block. There are 1K blocks, each of 128 KBytes (inclusive of Page). The Page has no direct identity (namely, it is not a register or RAM with independent random address and command executions)—it is temporary storage buffer to help execute read/write to nonvolatile array. Since each block (sector) is addressable, one can have a “Tag address bit”—if enabled it can activate “page addressing.”

[0023] Control Page-Nonvolatile array communication with a ‘Switch’ where volatile and nonvolatile memory can be accessed (unlike current art)—then page 2 Kbytes can be used as independent RAM for other useful purposes. One preferred embodiment—Select any of the currently unused blocks and use that/those pages as a modified SRAM; access that SRAM by currently used NC pins and rename them. Even with “concurrent Read/Write”, “write cache buffering” and other features, most blocks among the (1,024 or more) many in a NAND flash chip are unused while one or two blocks are being accessed (read, write, erase). The associated “page buffers” are also unused and wasted. In this preferred embodiment, a page of the currently unused block's page (2K Bytes×1K blocks is 2 MBytes of SRAM per chip—with a little overhead circuitry it can be 2 MBytes of SRAM with multiple port access as well) can be read and written (random page access, random access within a page, serial access from a page etc.). There are plenty of NC pins available in commercially available NAND flash ICs (one example is provided in FIG. 7)—we can configure NC pins to be used as Address, DATA, Command, Control in a combination. In parallel, the NAND flash can concurrently operate.

[0024] The concepts of SRAM mode by using available pages can also be implemented in Samsung's one NAND™ flash (for example), NOR flash or even Serial EEPROM flash—The exact implementation, page/latch size, command set may vary. The concepts of SRAM mode by using available pages can also be implemented in traditional NOR flash, as well, with slight modifications (e.g., one row equivalent page in every block or sector, on chip cache, boot code, data buffers). The concepts of SRAM mode can also be implemented in other nonvolatile memory devices (and their controllers) e.g., FeRAM, MRAM, Phase change RAM/memory, CNT RAM, NROM (Saifun) and similar ones. All these concepts can configure the multiple functions of the device or combination there of by (1) control/command signals, (2) programmable registers, (3) mode registers, (4) command register, etc-they can reside in part or in whole in controller, memory, special control, command, interface chip or even CPU.

[0025] It should be made clear that the “pages” and “buffers” mentioned in these pages titled “NVMS” do not necessarily have to be (1) static latches (6 transistor latches) or (2) traditional SRAM's. They can be DRAM's as is known widely in the industry. They can be MRAM, FeRAM (ferroelectric) or other similar concepts (molecular RAM etc). The implementation of a nonvolatile memory system may contain these configurable NVMS chips as described here (one or more). Configurable NVMS can be combined with commodity NOR/NAND/One NAND, flash chips, controllers, PSRAM's, DRAM's, or other similar functions to offer a total “system-in-package” (SIP) or “system-on-chip” (SOC).

[0026] In order to conserve operating power, the unselected, yet available pages can be in a “stand by” mode—namely, reduced Vcc (power supply voltage), until the access to that page is required. Such a, ‘cycle look ahead’, can be built into the memory chip, or provided by controller (on chip or off chip). A battery back up for the SRAM part of the device can be a very attractive option for a very large density total nonvolatile static random access memory (NVSRAM) that can go into a broad range of applications in computer, consumer, communications etc. Maxim supplies NVSRAM's-no flash IC in NVSRAM. A “power triggered switch-off/on” (Similar to what Simtek's NVSRAM's do) is also possible, thus eliminating the “battery option”.

[0027] Commands/Instructions are given as follows, in a preferred embodiment, which vary between NAND, One NAND, NOR, serial flash etc. Traditional flash: Read page in flash, Erase block in flash, Program page in flash, Etc. New commands with these inventions: Read page as SRAM/RAM, Write page as SRAM/RAM, Read/Modify/W Write page as SRAM/RAM, Read byte out of a page, etc; Write byte out of a page etc. Nibble mode/Serial access/double data rate are all possible.

[0028] The “address boundary” for a commercial NAND flash (especially in burst mode access e.g., burst READ) is different than a “2K byte” NAND flash page. The address boundary does/should not deter by using the inventions mentioned here for a superior READ (intelligent caching) or WRITE performance. Most flash systems are weighted to MOSTLY READ and FEW ERASE/PROGRAM (WRITE) due to the obvious endurance limitations (write/erase cycles limit). Hence, any performance in READ—Speed, and available Storage space—is always beneficial to a stand alone die and/or card, module, subsystem, system. To write to a page or pseudo page, WRITE command and immediately PROGRAM SUSPEND to invalidate writing into NVM. The data should be in page/pseudo page. This is one example.

[0029] As described in earlier pages, the page latches are available for reading. The pages can be read a byte (8 bits) or 2 bytes (16 bits) at a time. The whole page 2K bytes, can be sequentially accessed in 20-25 ns/byte. The subject invention uses the pages as a content addressable memory (CAM) and the NVM core as the stored data. The match lines (as used in CAM's—refer to U.S. Pat. Nos. 6,310,880 and 6,597,596 which use a DRAM storage) can be connected to the pages. The addresses in each block can be sequentially read, until the MATCH is found.