Method for electrochemically etching a semiconductor structure

Abstract

A method for etching a semiconductor structure (110) is provided, the semiconductor structure comprising a sub-surface quantum structure (30) of a first III-V semiconductor material,beneath a surface layer (31) of a second III-V semiconductor material having a charge carrier density of less than 5×10.sup.17 cm.sup.−3. The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte (130), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure (30) to form a plurality of nanostructures, while the surface layer (31) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.

Claims

1. A method for porosifying a semiconductor structure comprising a sub-surface quantum structure of a first III-V semiconductor material, beneath a surface layer of a second III-V semiconductor material having a charge carrier density of less than 5×10.sup.17 cm.sup.−3, the method comprising the steps of: exposing the surface layer to an electrolyte; and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically porosify the sub-surface quantum structure to form a plurality of nanostructures by electrochemical etching through the surface layer, while the surface layer is not porosified.

2. The method according to claim 1, in which the sub-surface quantum structure comprises a quantum well, or a quantum wire, or a quantum dot, and/or in which the plurality of nanostructures are three-dimensional nanostructures.

3. The method according to claim 1, in which the sub-surface quantum structure has one or more dimensions of less than or equal to 0.25 nm, or 0.5 nm, or 1 nm, or 2 nm, or 3 nm, or 5 nm, or 8 nm, or 10 nm, or 12 nm, and/or in which the sub-surface quantum structure has a minimum lateral dimension which is at least 5 times, or 10 times, or 50 times, or 100 times greater than a thickness of the sub-surface quantum structure.

4. The method according to claim 1, in which the semiconductor structure additionally comprises a further sub-surface structure of a third III-V semiconductor material having a charge carrier density of greater than 1×10.sup.17 cm.sup.−3.

5. The method according to claim 1, in which the sub-surface quantum structure of the first III-V semiconductor material has an electronic bandgap which is narrower than an electronic bandgap of semiconductor material adjacent to it in the semiconductor structure.

6. The method according to claim 1, in which one or more of the first III-V semiconductor material or the second III-V semiconductor material comprise III-nitride semiconductor materials.

7. The method according to claim 1, in which the sub-surface quantum structure has a charge carrier density greater than 1×10.sup.17 cm.sup.−3, or greater than 5×10.sup.17 cm.sup.−3, or in which the sub-surface quantum structure is undoped.

8. The method according to claim 1, in which both the surface layer and the sub-surface quantum structure have a threading dislocation density of at least 1×10.sup.4 cm.sup.−2, 1×10.sup.5 cm.sup.−2, 1×10.sup.6 cm.sup.−2, 1×10.sup.7 cm.sup.−2, or 1×10.sup.8 cm.sup.−2 and/or less than 1×10.sup.9 cm.sup.−2 or 1×10.sup.10 cm.sup.−2.

9. The method according to claim 1, in which a thickness of the surface layer is at least 40 nm, or 50 nm, or 100 nm, or 500 nm, and/or less than 1 μm, or 5 μm, or 10 μm.

10. The method according to claim 1, in which an outer surface of the surface layer has a minimum lateral dimension of at least 300 μm, or at least 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm, and/or in which the sub-surface quantum structure has a minimum lateral dimension of at least 300 μm, or at least 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 centimetres.

11. The method according to claim 1, in which the sub-surface quantum structure of the semiconductor structure comprises a plurality of sub-surface quantum structures formed from the first III-V semiconductor material.

12. The method according to claim 1, in which the semiconductor structure is provided as a wafer with a diameter of 1 inch (2.54 cm), or 2 inches (5.08 cm), or 6 inches (15.24 cm), or 8 inches (20.36 cm).

13. The method according to claim 1, in which the semiconductor structure is not pre-patterned with trenches, or in which the semiconductor structure is not pre-patterned with trenches separated by less than 1 cm, or 5 mm, or 1 mm, or 600 μm, or 400 μm, or 200 μm.

14. The method according to claim 1, in which the surface layer is not coated with an electrically insulating layer or other protective layer during the electrochemical etching, and/or in which the semiconductor structure is not illuminated by light having energy exceeding an electronic bandgap energy of the sub-surface quantum structure material during the electrochemical etching, or in which the semiconductor structure is not illuminated by a light source with a bandwidth of less than 20 nm, or less than 10 nm, or less than 5 nm during the electrochemical etching.

15. The method according to claim 1, in which the semiconductor structure is an LED structure, comprising a layer of p-type III-V semiconductor material arranged between the surface layer and the sub-surface quantum structure, and a layer of n-type III-V semiconductor material arranged beneath the sub-surface quantum structure.

16. A method for making an LED according to the method of claim 1, in which the semiconductor structure is an LED semiconductor structure.

17. The method according to claim 4, in which the sub-surface quantum structure is arranged between the surface layer and the further sub-surface structure of the third III-V material.

18. The method according to claim 4, in which the further sub-surface structure of the third III-V semiconductor material is a second sub-surface quantum structure.

19. The method according to claim 4, in which the charge carrier density of the third III-V semiconductor material is at least 5 times, or 10 times, or 100 times, or 1000 times, or 10,000 times, or 100,000 times, or 1,000,000 times higher than the charge carrier density in the surface layer.

20. The method according to claim 6, in which the III-nitride semiconductor materials are selected from the list consisting of: GaN, InN, AlGaN, InGaN, InAlN and AlInGaN.

21. The method according to claim 11, in which the semiconductor structure comprises a multiple quantum well (MQW) comprising a plurality of sub-surface quantum well layers arranged in a stack, and separated by intermediate barrier layers of III-V semiconductor material, in which an electronic bandgap of the plurality of sub-surface quantum wells is smaller than a bandgap of the intermediate barrier layers.

22. The method according to claim 21, in which the plurality of sub-surface quantum wells is sequentially porosified from the surface layer down.

23. The method according to claim 22, further comprising controlling a porosity of a selected sub-surface quantum well by controlling a potential difference between the electrolyte and the selected sub-surface quantum well during the electrochemical etching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Specific embodiments of the invention will now be described with reference to the figures, in which:

(2) FIG. 1 shows a scanning TEM micrograph taken from Wang et al (slides), Sandia National Laboratories;

(3) FIG. 2 shows a schematic illustration of the experimental setup for electrochemical etching;

(4) FIG. 3A shows a schematic illustration of a multi-layer semiconductor structure according to an aspect of the present invention;

(5) FIG. 3B shows a cross-sectional scanning electron microscopy (SEM) image of the multi-layer semiconductor structure of FIG. 3A, after etching;

(6) FIG. 3C shows the measured photoluminescence (PL) spectra of the semiconductor structure of FIG. 3A, before and after etching;

(7) FIG. 4 shows a cross-sectional transmission electron microscopy (TEM) image of an etched multi-layer semiconductor structure according to a preferred embodiment of the present invention;

(8) FIG. 5 shows a cross-sectional transmission electron microscopy (TEM) image of a nanostructured layer formed by etching a quantum well according to the present invention;

(9) FIG. 6A shows a cross-sectional scanning electron microscopy (SEM) image of an etched multi-layer semiconductor structure according to a preferred embodiment of the present invention;

(10) FIG. 6B shows the measured cathodoluminescence (CL) spectra of the semiconductor structure of FIG. 6A, before and after etching;

(11) FIG. 7 shows the measured photoluminescence (PL) spectra of a seven identical semiconductor structures etched at different voltages according to the present invention;

(12) FIG. 8A shows an AFM image of the top surface of an unetched semiconductor structure;

(13) FIG. 8B shows an AFM image of the top surface of the structure of FIG. 8A, after etching at 6 V according to the present invention;

(14) FIG. 9A shows a schematic illustration of an LED structure to be etched according to an aspect of the present invention;

(15) FIG. 9B shows a cross-sectional scanning electron microscopy (SEM) image of the LED structure of FIG. 9A, after etching according to the method of the present invention.

DETAILED DESCRIPTION

(16) FIG. 1 shows a scanning TEM micrograph taken from Wang et al (slides), Sandia National Laboratories, showing an etched sample 2. The sample 2 comprises an InGaN quantum well 4 formed as a layer beneath a GaN “cap” layer 6. The sample 2 has been etched using Sandia's “quantum-size-controlled-photoelectrochemical (QSC-PEC)” etching technique. As can be clearly seen in the Figure, the QSC-PEC etching process has damaged the GaN cap layer, creating holes 8 through the entire thickness of the cap layer, so that the etched quantum well layer 4 is exposed. This seems to be the result of undesirable “vertical” etching discussed in publications relating to Sandia's technique.

(17) The damage Sandia's QSC-PEC technique causes to the GaN cap layer is highly undesirable, as etched quantum structures may be relatively unstable in air. Having the etched layer exposed to the outside environment through holes in the cap layer may therefore cause the etched layer to deteriorate. A further disadvantage of this damage to the cap layer is that it may make overgrowth of further semiconductor material difficult or impossible. Any material that is overgrown on such a broken surface layer would be of poor quality, and may not be suitable for a range of applications.

(18) FIG. 2 shows a schematic of an electrochemical (EC) experimental setup usable in the method of the present invention. As shown in FIG. 2, the experimental setup consists of a two-electrode electrochemical cell 100, with a sample 110 connected as an anode and a platinum foil 120 connected as a cathode. The platinum cathode, and at least a portion of the surface layer of the sample, are exposed to an electrolyte 130 by immersion in the electrolyte. A constant current DC power supply 140 is connected between the anode and the cathode, and an ammeter 150 is used to monitor and record the etching current flowing through the circuit.

(19) Unless otherwise stated, the EC etching experiments described herein were conducted at room temperature with a semiconductor structure as the anode and a platinum foil as the counter electrode (cathode). Oxalic acid with a concentration of 0.25 M was used as the electrolyte. The etching process was carried out in a constant voltage mode controlled by a Keithley 2400 source meter. After etching, samples were rinsed with deionized water and blow dried in N2.

(20) As discussed above in the summary of invention, the skilled person will appreciate that the term “undoped” is relatively imprecise in semiconductor technology. Practically speaking, all semiconductor material contains inherent impurities which can be thought of as “dopant” atoms. Different methods of semiconductor growth may produce different levels of impurity, and thus different inherent charge carrier concentrations.

(21) Thus, it is possible that semiconductor materials referred to in the prior art as “undoped” may have high impurity levels, such that they have a natural charge carrier density of above 1×10.sup.17 cm.sup.−3 arising from impurities alone.

(22) In appreciation of this, the inventors of the present invention prefer to use the term “non-intentionally-doped” (NID) to refer to semiconductor material that has been made without intentional doping. The impurity levels of semiconductor materials naturally depend on factors including the method by which they are formed, the environment in which they are formed, and the purity of the reactants used to form the semiconductor materials.

(23) In the present application, the term “non-intentionally-doped” (NID) should be understood to refer to semiconductor materials deliberately grown to be as pure as possible, which have been measured to have a charge carrier density of between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3.

(24) Semiconductor materials which have been intentionally doped with n-type dopants to obtain a charge carrier density greater than 5×10.sup.17 cm.sup.−3, may be referred to as “n” or “n+” semiconductor material. In the description below, “n” designates lightly-doped n-type material with a charge carrier density of approximately 1×10.sup.18 cm.sup.−3, while “n+” designates n-type doped material with a charge carrier density greater than or equal to approximately 1×10.sup.19 cm.sup.−3.

(25) FIG. 3A shows a schematic diagram of an epitaxial non-polar sample structure, which comprises five InGaN quantum wells 30 positioned between two distributed Bragg reflectors (DBRs).

(26) Each of the two DBRs is a “two-pair” DBR consisting of four alternating layers of non-intentionally-doped GaN (NID-GaN) and heavily doped n-type GaN (n+-GaN) layers. The NID-GaN layers have a charge carrier density of less than 1×10.sup.17 cm.sup.−3, while the n+-GaN layers have a nominal silicon doping concentration of 2.3×10.sup.19 cm.sup.−3. Each of the alternating NID-GaN/n+-GaN layers has a thickness of approximately 71 nm and 53 nm, respectively.

(27) The sample comprises an uppermost surface layer 31 of NID-GaN. A first two-pair DBR 32 is positioned beneath the surface layer and above a 100 nm-thick layer of NID-GaN 33 which covers the uppermost of five InGaN quantum wells 30. Each quantum well 30 is a layer of NID-InGaN with a thickness of 3 nm, sandwiched between barrier layers of NID-GaN with a thickness of 7 nm. A second 100 nm-thick layer of NID-GaN 35 is positioned between the bottom-most of the five InGaN quantum wells 30 and a second two-pair DBR 34. Below the second two-pair DBR there is a layer of lightly doped n-type GaN (n-GaN). The n-GaN layer has a charge carrier density of approximately 1×10.sup.18 cm.sup.−3. The n-GaN layer has a thickness of 2 μm and is present for uniform distribution of the anodization bias across the sample. The n+GaN layer in the DBR stack and the n-GaN layer may function to donate charge carriers to the NID-quantum wells to allow etching of the quantum wells. Below the n-GaN layer there is a base layer of NID-GaN arranged on a sapphire substrate.

(28) The sample was grown by metal-organic vapour phase epitaxy (MOVPE) in a 6×2 in. Thomas Swan close-coupled showerhead reactor on r-plane sapphire substrates using trimethylgallium and ammonia as precursors, hydrogen as a carrier gas and silane for n-type doping. Firstly, a 4 μm thick c-plane GaN pseudosubstrate (not shown) was grown with a nominal dislocation density of ˜4×10.sup.8 cm.sup.−2. After the growth of another 500 nm undoped GaN layer (not shown), the rest of the layered structure was epitaxially grown on the pseudosubstrate.

(29) The sample of FIG. 3A was electrically contacted by soldering an indium wire to the edge of the sample, so that the indium wire contacts the edges of the quantum wells, the n-GaN layer, and the n+-GaN layers to be etched. A portion of the sample, of approximately 1 cm×1 cm in size, was then immersed in the electrolyte. Using the experimental setup shown in FIG. 2, an EC etching process was carried out on the sample in a constant voltage mode, with a DC bias of 6 V, and controlled by monitoring and recording the etching current signal at room temperature. The sample was not illuminated with narrowband light.

(30) The EC porosification process begins from the top down, with the oxidation of the alternating n+-GaN layers of the upper DBR 32 by localised injection of holes upon the application of a positive anodic bias, and localised dissolution of such oxide layer in the acid-based electrolyte will result in the formation of a mesoporous structure.

(31) The porosification of the alternating n+-GaN layers, but not the NID-layers, creates a contrast in refractive index between alternating layers, such that the etched structure acts as a DBR.

(32) Once all of the n+-GaN layers in the upper DBR 32 have been etched and transformed into mesoporous GaN layers, the EC porosification proceeds down the structure to etch the InGaN quantum wells. Although the quantum wells themselves are not doped, and therefore have a low inherent charge carrier density, the quantum wells act as an energy minimum which traps charge carriers from other parts of the semiconductor structure. In the structure of FIG. 3A, the quantum wells may capture charge carriers from the n+-GaN layers of the lower DBR 34, or from the underlayer of n-GaN.

(33) The quantum wells are therefore sequentially etched from the uppermost quantum well downwards. During etching, pores form throughout the quantum well layers, and InGaN material is removed from the layer. What remains consists of a network of connected nanostructures of InGaN. Due to the removal of InGaN material, the nanostructures are very small, with their maximum dimensions typically on the order of a few nanometres, which is on the order of the de Broglie wavelength for the charge carriers in the InGaN.

(34) This reduction in size means that charge carriers within the InGaN nanostructures experience quantum confinement in all three dimensions.

(35) The barrier layers of NID-GaN separating the quantum wells are not etched, as they are not sufficiently conductive to etch, and they are not energy minima capable of trapping charge carriers from elsewhere.

(36) After the five quantum wells have been etched into nanostructures, the etching proceeds downwards to porosify the n+-GaN layers of the lower DBR 34.

(37) The end of the anodisation process is reached when the etching current drops to the base line level, indicating that all the n+-GaN layers, and the quantum wells, have been etched. This may typically be after approximately 30 minutes for a semiconductor structure of this size.

(38) The cross-sectional scanning electron microscopy (SEM) image in FIG. 3B shows the morphology of the etched structure 300. The cross-section of FIG. 3B was taken from an edge cleaved post-etching, far away from the original sample edges. This confirms that the porosification process proceeded extremely uniformly across the entire sample area that was immersed in the etching solution. FIG. 3B further shows that the NID-GaN layers stay almost intact during the EC etching, and are not themselves porosified. Only the n+-GaN layers and the quantum well layers are selectively etched and transformed into porous layers.

(39) The 1 cm×1 cm sample is far larger than samples porosified by horizontal etching in the prior art, as horizontal etching would be unable to penetrate horizontally into the centre of such a large sample without regular trenches in the sample surface. Furthermore, the etching time of 30 minutes would be insufficient for horizontal etching to proceed far into the bulk material of the sample. Thus the porous cross-section of FIG. 3B, taken far from the sample edges, is evidence that the quantum wells, and the n+-GaN layers, have been etched through the surface layer of NID-GaN, and not horizontally from the sample edges.

(40) The semiconductor structure of FIGS. 3A and 3B exhibits photoluminescence both before and after etching. FIG. 3C shows the measured photoluminescence (PL) spectra of the semiconductor structure of FIG. 3A, before and after etching.

(41) The pre-etching spectrum 38 demonstrates the PL behaviour of the non-porous multiple-quantum-well (MQW) structure.

(42) The post-etching spectrum 40 demonstrates the PL behaviour of the five nanostructured layers. The intensity of the spectra have been normalised to negate the effect of the DBRs in the etched structure.

(43) Comparing the PL spectra before and after etching shows that the etching of the quantum wells into nanostructured layers leads to an 11 nm-shift in the PL spectrum of the semiconductor structure towards shorter wavelengths. This is referred to as a “blue-shift”.

(44) This “blue-shift” of the photoluminescence spectrum may be the result of the increased quantum confinement experienced by charge carriers in the nanostructured layers compared to the 2-D quantum well. Etching to form nanostructures may also cause strain relaxation in the nanostructured layer, which may advantageously increase the electron-hole overlap and reduce the electron-hole recombination time. The same decrease in internal electric field which increases the electron-hole overlap may also cause a blue shift.

(45) This blue shift may be particularly advantageous for the manufacture of short-wavelength light sources, for example UV-LEDs.

(46) FIG. 4 shows a cross-sectional transmission electron microscopy (TEM) image of an etched multi-layer semiconductor structure 400 according to a preferred embodiment of the present invention. The semiconductor structure of FIG. 4 has a NID-GaN surface layer 42 above an etched upper DBR 44. Three 3 nm-thick NID-InGaN nanostructured layers 46, separated by 7 nm-thick barrier layers of NID-GaN, are positioned one-above-another beneath the upper DBR 44 and above an etched lower DBR 48. The lower DBR 48 is formed from a greater number of porous/non-porous layers than the upper DBR 44, which may advantageously improve light extraction out of the upper surface 42 of the structure 400.

(47) The etched semiconductor structure 400 of FIG. 4 is formed by the etching method described above in relation to FIG. 3A. Prior to etching, the nanostructured layers 46 were 3 nm-thick quantum wells of NID-InGaN, and the upper and lower DBRs were alternating layers of non-porous NID-GaN and n+-GaN.

(48) The etching method of the present invention thus advantageously allows the n+-GaN layers of the DBRs to be porosified in the same step as etching nanostructures in the quantum well layers.

(49) FIG. 5 shows a cross-sectional transmission electron microscopy (TEM) image of a single nanostructured layer 50 of NID-InGaN sandwiched between barrier layers 52 of NID-GaN. The nanostructured layer 50 has been formed by etching an NID-InGaN quantum well according to the method of the present invention, as described above.

(50) FIG. 5 shows a plurality of nanopores distributed through the nanostructured layer 50. The pores are well-defined, and have been created selectively in the quantum well layer during etching. No pores have been created in the NID-GaN barrier layers.

(51) As discussed above, the creation of pores in the quantum well layer creates nanostructures which exhibit quantum confinement in three dimensions, rather than the one-dimensional confinement exhibited by the un-etched quantum well. This can provide advantages including improving the recombination efficiency of light emission from the quantum layer, and results in a blue-shift of the emission spectrum.

(52) As with the samples shown in cross-section in other Figures, the cross-section TEM image of FIG. 5 was taken distant from any edge of the sample. Given the timescale of the etching process, the nanostructures could not have been created by the “lateral” etching pathways of the prior art. There is also no damage to the layers above the nanostructured layer 50, as exhibited by the unwanted “vertical” etching pathways in other prior art techniques. The nanostructured layer 50 seen in FIG. 5 can thus only have been created by the through-surface etching discussed above.

(53) FIG. 6A shows a cross-sectional transmission electron microscopy (TEM) image of an etched multi-layer semiconductor structure according to another preferred embodiment of the present invention.

(54) The semiconductor structure shown in FIG. 6A was formed by etching a stack of 30 NID-GaN quantum wells (2 nm-thick), separated by barrier layers of NID-AlGaN (5 nm thick). The quantum wells are positioned beneath a surface layer 60 of NID-GaN and above a 500 nm-thick layer of NID-GaN. A further sub-surface layer of n-GaN (not shown) is positioned underneath the NID-GaN, in order to donate charge carriers to the quantum wells and to spread current during etching.

(55) Similarly to the InGaN quantum well embodiments described above, and using the same etching technique, the GaN quantum wells have been etched to form 30 nanostructured layers 62 of NID-GaN buried in the semiconductor structure.

(56) FIG. 6B shows the measured cathodoluminescence (CL) spectra of the semiconductor structure of FIG. 6A, before and after etching. Results from four positions from each sample are shown in FIG. 6B.

(57) The pre-etching spectra 64 demonstrate the CL behaviour of the non-porous multiple-quantum-well (MQW) GaN/AIGaN structures.

(58) The post-etching spectra 66 demonstrate the CL behaviour of the 30 nanostructured layers.

(59) Comparing the CL spectra before and after etching shows that the etching of the GaN quantum wells into nanostructured layers leads to a 2 nm-shift in the CL spectrum of the semiconductor structure towards shorter wavelengths. This is referred to as a “blue-shift”.

(60) As the blue shift exhibited by etching GaN quantum wells pushes the emission spectrum even further into the UV, this may be highly advantageous in the manufacture of UV-LEDs.

(61) FIG. 7 shows the measured photoluminescence (PL) spectra of a range of semiconductor structures etched at different voltages according to the present invention. Seven identical semiconductor structures were formed with the same sample structure described above in relation to FIGS. 3A and 3B. The samples comprise five InGaN quantum wells between upper and lower two-pair DBRs.

(62) Six of the structures were then etched for 30 minutes at different etching voltages of 4V, 6V, 8V, 10V, 12V and 14V, respectively, so that the quantum well layers in the structures were etched to form layers of nanostructures.

(63) The PL spectra of the six etched samples, and the one un-etched sample, were then measured, the results of which are shown in FIG. 7. As can be seen in FIG. 7, all of the etched samples exhibited a blue shift in emission spectrum compared to the un-etched, non-porous, sample. The greatest blue shift, of 22 nm, was exhibited by the sample etched at 4 V, with blue shifts gradually decreasing with a higher etching voltage.

(64) FIG. 8A shows an AFM image of the top surface of an unetched semiconductor structure;

(65) FIG. 8B shows an AFM image of the top surface of the structure of FIG. 8A, after etching at 6V according to the present invention;

(66) To evaluate possible etching damage of a top surface layer of NID-GaN, atomic force microscopy (AFM) images were taken of a surface layer before and after etching. These AFM images are shown in FIGS. 8A and 8B, respectively. Apart from some dirt/small particles present in the porous region that may be related to the EC etching products, contaminants in the etching chemicals and/or sample cleaning, no changes to the surface morphology were observed and the root mean square roughness (R.sub.Rms) of the top GaN surface is similar in both the etched and unetched samples, at around 1 nm measured over a 5 μm×5 μm area. The root mean square roughness (R.sub.RMS) of the top GaN surface is similar in the unetched sample was measured by AFM to be 0.9972 nm over a 5 μm×5 μm area, while the root mean square roughness (R.sub.RMS) of the top GaN surface is similar in the etched sample was measured by AFM to be 1.095 nm over a 5 μm×5 μm area It appears therefore that the sub-surface EC porosification does not degrade the surface of the GaN surface layer, and the R.sub.Rms of the post-etching sample is sufficiently low for further semiconductor overgrowth.

(67) FIG. 9A shows a schematic illustration of an LED structure 900 to be etched according to an aspect of the present invention.

(68) While alternative LED structures comprising p-type and n-type AIGaN or InGaN (indicated by brackets on FIG. 9A) could be etched by the method of the present invention, the structure 900 will be described below with layers of p-type GaN and n-type GaN.

(69) The LED structure 900 comprises a 350 nm-thick layer of p-type GaN semiconductor material 910, with a charge carrier density of approximately 2×10.sup.17 cm.sup.−3. This p-type GaN layer forms the surface layer of the structure. Five 3 nm-thick NID-InGaN quantum wells 920 are formed as a stack of continuous layers separated by 7 nm-thick NID-GaN barrier layers. A 500 nm-thick layer 930 of n+-GaN, with a charge carrier density of approximately 5×10.sup.18 cm.sup.−3, is arranged beneath the quantum well stack. A sub-surface layer 940 of 250 nm thick NID-GaN is arranged beneath the n+-GaN and above a 500 nm-thick layer 950 of n-GaN with a charge carrier density of 1×10.sup.18 cm.sup.−3.

(70) The sub-surface layers of n-type GaN may advantageously act as “conductive”, or “current spreading” layers during etching. Charge carriers from the n-type GaN may be trapped by the quantum wells to increase their charge carrier density so that the NID-InGaN quantum wells are etched to form nanostructures.

(71) Instead of layers of p-type GaN, n+-GaN, and n-GaN, alternative III-nitride materials with appropriate charge carrier densities may be used. The quantum wells may also be formed from materials, preferably III-nitride materials, other than InGaN. Further layers of III-V material, preferably III-nitride material, may also be present in the structure.

(72) The LED structure of FIG. 9A can be electrochemically etched by the method described above, by contacting the surface layer with electrolyte and applying a potential difference of 8 V between the quantum wells and the electrolyte. A potential difference of 8 V is also applied between the conductive n-GaN layer and the electrolyte.

(73) The surface layer, the p-type layer and the barrier layers are sufficiently conductive to allow etching of the quantum wells to take place through these layers, but these layers do not etch themselves. The etch therefore “bypasses” these layers, and selectively etches the quantum well layers.

(74) The etching current is monitored, and when the quantum wells are fully etched, etching is stopped before the n+-GaN and conductive n-GaN layers below the quantum wells are etched.

(75) This method advantageously allows an LED structure to be grown and then etched in a single etching step, so that the quantum well layers are etched to form nanostructures, or quantum dots, without affecting the rest of the structure. This can be done even though the quantum well layers to be etched are buried in the LED structure between layers of p-type and n-type semiconductor material.

(76) As discussed above, the etching of nanostructures in the quantum well layers creates a blue shift in the emission spectrum of the LED, which may be highly desirable for the manufacture of low-wavelength LEDs.

(77) FIG. 9B shows a cross-sectional scanning electron microscopy (SEM) image of the LED structure of FIG. 9A, after etching according to the method of the present invention. FIG. 9B shows that the quantum well layers of the semiconductor structure have been selectively etched without porosifying the pGaN, n+GaN, and the nGaN layers of the structure, and without any damage to the other parts of the LED structure.

(78) The etching method of the present invention may thus be used to etch nanostructures in the quantum wells of pre-formed LED semiconductor structures. Importantly, the through-surface etching technique of the present invention allows sub-surface quantum structures to be etched without etching, or otherwise damaging, the other parts of the structure.