ELECTRONIC SYSTEM FOR GENERATING MULTIPLE POWER SUPPLY OUTPUT VOLTAGES WITH ONE REGULATION LOOP

Abstract

Provided is a an electronic system (1) comprising a plurality of sub blocks (21, 22, . . . ), a differential amplifier (3), a voltage regulation loop comprising a first transistor (40) and a variable resistor (5), and a plurality of additional transistors (41, 42, . . . ). The input reference voltage (VRF) and the variable resistor are configured such that a first sub block (21) is supplied with its required power supply output voltage (VDD1) by the transistor to which it is connected. The amplifier is configured to output on each of its outputs a power supply reference voltage (VG1, VG2 . . . ) such that each sub block (22, . . . ) other than the first sub block is supplied with its required power supply output voltage (VDD2 . . . ) by the transistor to which it is connected.

Claims

1. An electronic system (1) comprising: a plurality of sub blocks (21, 22, . . . ), each one being required to be supplied with a different power supply output voltage (VDD1, VDD2, . . . ), a differential amplifier (3) having a plurality of outputs, an input reference voltage (VRF) being applied to a first input of the amplifier, a voltage regulation loop with a transistor feedback connected to a first output of the amplifier and to a second input of the amplifier, said loop comprising a first transistor (40) and a variable resistor (5), a plurality of additional transistors (41, 42, . . . . ), each output of the amplifier being connected to a gate or base of one of said additional transistors and the drain, source, emitter or collector of each additional transistor being connected to one of said sub-blocks, wherein: Ithe input reference voltage (VRF) and the variable resistor are configured such that a first sub block (21) is supplied with its required power supply output voltage (VDD1) by the transistor it is connected to, and said amplifier is configured to output on each of its outputs a power supply reference voltage (VG1, VG2 . . . ) such that each sub block (22, . . . ) other than the first sub block is supplied with its required power supply output voltage (VDD2 . . . ) by the transistor it is connected to.

2. The electronic system of claim 1, wherein a last stage of said amplifier (3) comprises at least one component configured such that when a potential at one of its terminals is set to a first power supply reference voltage (VG1), a second power supply reference voltage (VG2) is generated at the other terminal of said component.

3. The electronic system of claim 2, wherein said at least one component is among a resistance, a diode, a MOS transistor, or a switched capacitor.

4. The electronic system according to claim 3, wherein said sub blocks are among a flash memory (22), a digital circuit (21), an analog circuit, or an input/output interface.

5. The electronic system according to claim 4, wherein said first sub block (21) is a digital circuit to be supplied with a first power supply output voltage (VDD1) equal to 1.2 V, a second sub block (22) is a flash memory to be supplied with a second power supply output voltage (VDD2) equal to 1.5 V and said at least one component is a resistance set to a value equal to 300 mV divided by the current flowing through it.

6. The electronic system of claim 1 is embedded on a System-On-Chip (SOC).

7. The electronic system of claim 1 is embedded in a smartcard chip of a smartcard.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following description and the annexed drawings set forth in detail certain illustrative aspects and are indicative of but a few of the various ways in which the principles of the embodiments may be employed. Other advantages and novel features will become apparent from the following detailed description when considered in conjunction with the drawings and the disclosed embodiments are intended to include all such aspects and their equivalents.

[0025] FIG. 1 is a schematic illustration of an existing power supply architecture using a capacitor-less regulation loop with NMOS feedback.

[0026] FIG. 2 is a schematic illustration of a power supply architecture generating two power supply output voltages for two sub-blocks.

[0027] FIG. 3 is a schematic illustration of an electronic system according to the present invention using MOS transistors;

[0028] FIG. 4 is a schematic illustration of an electronic system according to the present invention using bipolar transistors;

[0029] FIG. 5 is a schematic illustration of an amplifier architecture based on a PMOS transistor differential pair according to an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0030] According to a first aspect, as shown on FIG. 3, the invention relates to an electronic system 1, comprising a plurality of sub blocks 21, 22 . . . each sub block being required to be supplied with a different power supply output voltage VDD1, VDD2 . . . . Such sub-blocks may for example be a flash memory which should be supplied with a 1.5 V voltage, a digital circuit which should be supplied with a 1.2 V voltage, an analog circuit, an input/output interface . . . .

[0031] Such an electronic system may be embedded in a portable electronic device. It may for example be included in a smartcard chip or included in a System-On-Chip (SOC).

[0032] In order to generate the voltages to be supplied to the sub-blocks, the system 1 also includes a differential amplifier 3. This amplifier has a specific design with a plurality of outputs. An input reference voltage VRF is applied to a first input of the amplifier. In the example show on FIG. 3, the input reference voltage VRF is applied to the positive input of the amplifier.

[0033] In order to make the amplifier output constant voltages equal to desired values, the system comprises a capacitor less voltage regulation loop with a transistor feedback. This loop is connected on one end to a second input of the amplifier. In the example of FIG. 3, it is connected to the negative input of the amplifier. In FIG. 3, all the transistors used in the electronic system, including the one for feedback, are MOS transistor. FIG. 4 gives another example in which all the transistors used in the system are bipolar transistors. In the rest of the application, description will refer to FIG. 3 and the transistors used in the system will be referred to as being MOS transistors but any other kind of transistor, such as bipolar transistors, may be used instead, with the same effect.

[0034] The voltage at the second input of the amplifier is noted VFB. The loop is connected on the other end to a first output of the amplifier, outputting a power supply reference voltage VG1. This loop includes a first MOS transistor 40 and a variable resistor 5. In the example shown on FIG. 3, this transistor is a NMOS transistor. The threshold voltage of the first transistor is noted VTH (In the case of bipolar transistors, the transistor is characterized by its base-emitter voltage VBE instead of a threshold voltage VTH). The architecture of this regulation loop is the same as the one presented on FIG. 1. The first output of the amplifier is connected to the gate of the first transistor 40 (or to its base in the case of bipolar transistors). The source of the first transistor (or its emitter terminal in case of bipolar transistor) is connected to one end terminal of the variable resistor and the middle terminal of the variable resistor is connected to the second input of the amplifier.

[0035] The voltage at the source of the first transistor is noted VDD_VFB, the resistance between the source of the first transistor and the second input of the amplifier is noted R.sub.up, the resistance between the second input of the amplifier and the ground is noted Rdown. In such a configuration, when the amplifier is supposed to be ideal (VRF=VFB), VDD_VFB and VG1 verify the following equation:

VDD_VFB=VRF*(R.sub.up+R.sub.down)/R.sub.down=VG1−VTH

[0036] Finally, in order to supply various power supply output voltages to the sub-blocks of the system, the system includes a plurality of additional MOS transistors 41, 42 . . . . Each output of the amplifier is connected to the gate of one of these additional MOS transistors and the drain or source of each additional transistor is connected to one of the sub-blocks of the system in order to supply it with its required voltage.

[0037] In the example of FIG. 3, the system includes two sub-blocks and two additional NMOS transistors. The gate of the first additional transistor is connected to the first output of the amplifier, which is at voltage VG1, and its source supplies a voltage VDD1 to the first sub-block. The gate of the second additional transistor is connected to a second output of the amplifier, which is at voltage VG2, and its source supplies a voltage VDD2 to the second sub-block.

[0038] The first transistor 40 has a grid width W and a grid length L. The first additional transistor 41 has a grid width W1 and a grid length L1. Let's introduce scaling factor m1 defined by the relation: W1/L1=m1*W/L. If the currents flowing out of the sources of the first transistor and of the first additional transistor are respectively named IFB and IDD1, IFB is proportional to W/L*(VG1-VDD_FB-VTH).sup.2 and IDD1 to W1/L1*(VG1-VDD1-VTH).sup.2. For a given value of IDD1 drained by the first sub-block, the ratio W1/L1 of the first additional transistor may be set such that IFB*L/W=IDD1*L1/W1, ie m1=IDD1/IFB, with IFB equal to VDD_FB/(R.sub.up+R.sub.down). In such a configuration, the power supply output voltage VDD1 supplied to the first sub-block by the first additional MOS transistor 41 connected to the first output of the amplifier is almost equal to the voltage VDD_VFB at the source of the first transistor of the regulation loop, which also has its gate connected to the first output of the amplifier, i.e. VDD1=VDD_VFB.

[0039] Consequently, in order to supply the first sub-block with its required power supply output voltage VDD1, the input reference voltage VRF and the variable resistor are configured such that a first sub block is supplied with its required power supply output voltage VDD1 by the MOS transistor it is connected to. Said differently, VRF and R.sub.up/(R.sub.up+R.sub.down) are set such that:

[0040] VRF *(R.sub.up+R.sub.down)/R.sub.down=VDD1 Which leads to VG1=VDD1+VTH

[0041] Such equations do not take into account voltage fluctuations or offsets due to design imperfections such that the fact that the amplifier is not ideal, variations of the input reference voltage VRF . . . . In order to take into account such imperfections, VDD1 and VG1 may be accurately set by performing a trimming process.

[0042] In addition, for each additional transistor i, the voltage VDDi at its terminal connected to the sub-block it supplies and the power supply reference voltage VGi supplied by the output of the amplifier to which its gate is connected verify the following equation: VGi=VDDi+VTHi with VTHi the threshold voltage of the transistor. As described here above for the first additional transistor, the ratio grid width/grid length (Wi/Li=mi*W/L) of each additional transistor may be set to have the desired current flowing out of the source of the transistor towards its sub-block.

[0043] In order to supply every sub-blocks with their required power supply output voltage, the amplifier is configured to output on each of its outputs a different power supply reference voltage VG1, VG2 . . . such that each sub block other than the first sub block is supplied with its required power supply output voltage (VDD2 . . . ) by the MOS transistor it is connected to. Said differently, the amplifier is configured to output on its output i a voltage VGi such that VGi=VDDi+VTHi which ensures that the sub-block supplied by the ith additional transistor connected to this output will be supplied with its required power supply output voltage VDDi.

[0044] In order to generate a plurality of power supply reference voltages, additional components which generate a voltage offset may be included in the amplifier. More precisely, the last stage of the amplifier may comprise at least one component configured such that when the potential at one of its terminals is set to a first power supply reference voltage VG1, a second power supply reference voltage VG2 . . . is generated at the other terminal of said component.

[0045] Such a component may for example be a resistance, a diode, a MOS transistor, switched capacitors . . . .

[0046] An example of such an architecture of the amplifier is given on FIG. 5. In such an example, the amplifier architecture is based on a PMOS transistor differential pair. It generates a first power supply reference voltage VG1 at the drain of its output transistor NOUT. A resistor Roffset is inserted between the transistor NOUT and the current source Iref. It generates a voltage offset Voff which leads to a voltage VG2=VG1+Voff at its terminal connected to the current source Iref.

[0047] In such an example, when such an amplifier is used in the configuration of FIG. 3, the first sub block is a digital circuit to be supplied with a first power supply output voltage VDD1 equal to 1.2 V, the second sub block is a flash memory to be supplied with a second power supply output voltage VDD2 equal to 1.5 V. In such a case, the offset to be generated between VG1 and VG2 is 300 mV and the component is a resistance set to a value equal to 300 mV divided by the current flowing through it. When the current Iref is set to 1 μA, the resistance is set to 300 k Ohms.

[0048] When VDDi is lower than VDD1, a negative offset is needed. In such a case the component to be added to the amplifier may be inserted between the first output of the amplifier and the output transistor NOUT.

[0049] As a result, the system according to the invention enables to generate as many power supply output voltages as required by the sub-blocks of the system to be powered up, with only one amplifier and one regulation loop. Silicon area and power consumption are reduced. Only one trimming process is required to set precisely all the power supply output voltages to their required values.