Ring oscillator with resonance circuits

Abstract

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A.sub.1-A.sub.4), connected in a ring and has a first and a second supply terminal (s.sub.1, s.sub.2). Each amplifier circuit (A.sub.1-A.sub.4) comprises an input transistor (M.sub.1) having its gate connected to the input (in) of the amplifier circuit, its drain connected to an internal node (x) of the amplifier circuit, and its source connected to the first supply terminal (si). Furthermore, each amplifier circuit (A.sub.1-A.sub.4) comprises a first resonance circuit (R.sub.1) comprising a first inductor (L.sub.s) and a first capacitor (C.sub.s), wherein the first inductor (L.sub.s) is connected between the internal node (x) and the output (out) of the amplifier circuit, and the first capacitor (C.sub.s) is connected between the output (out) of the amplifier circuit and one of the first and the second supply terminals (s.sub.1, s.sub.2). Moreover, each amplifier circuit (A.sub.1-A.sub.4) comprises a second resonance circuit (R.sub.2) comprising a second inductor (L.sub.p) and a second capacitor (C.sub.p), wherein the second inductor (L.sub.p) and the second capacitor (C.sub.p) are connected in parallel between the internal node (x) and the second supply terminal (s.sub.2).

Claims

1. An oscillator circuit comprising N amplifier circuits (A.sub.1-A.sub.N), in the following numbered 1 to N, wherein for each j∈{1,2, . . . , N−1}, an output (out) of amplifier circuit j (A.sub.j) is connected to an input (in) of the amplifier circuit j+1 (A.sub.j+1), the output of the amplifier circuit N (A.sub.N) is connected to the input of the amplifier circuit 1 (A.sub.1); a first and a second supply terminal (s.sub.1, s.sub.2) configured to receive a supply voltage between the first and the second supply terminal (s.sub.1, s.sub.2); and each of the N amplifier circuits (A.sub.1-A.sub.N) comprising: an input transistor (M.sub.1) having its gate connected to the input (in) of the amplifier circuit, its drain connected to an internal node (x) of the amplifier circuit, and its source connected to the first supply terminal (s.sub.1); a first resonance circuit (R.sub.1) comprising a first inductor (L.sub.S) and a first capacitor (C.sub.S), wherein the first inductor (L.sub.S) is connected between the internal node (x) and the output (out) of the amplifier circuit, and the first capacitor (C.sub.S) is connected between the output (out) of the amplifier circuit and one of the first and the second supply terminals (s.sub.1, s.sub.2); and a second resonance circuit (R.sub.2) comprising a second inductor (L.sub.P) and a second capacitor (C.sub.P), wherein the second inductor (L.sub.P) and the second capacitor (C.sub.P) are connected in parallel between the internal node (x) and the second supply terminal (s.sub.2).

2. The oscillator circuit of claim 1, wherein N=4.

3. The oscillator circuit of claim 2, comprising a first transistor (M.sub.P1) having its gate connected to the output (out) of amplifier circuit 3 (A.sub.3), its source connected to the first supply terminal (s.sub.1), and its drain connected the drain of the input transistor (M.sub.1) of amplifier circuit 1 (A.sub.1); a second transistor (M.sub.P2) having its gate connected to the output (out) of amplifier circuit 4 (A.sub.4), its source connected to the first supply terminal (s.sub.1), and its drain connected the drain of the input transistor (M.sub.1) of amplifier circuit 2 (A.sub.2); a third transistor (M.sub.P3) having its gate connected to the output (out) of amplifier circuit 1 (A.sub.1), its source connected to the first supply terminal (s.sub.1), and its drain connected the drain of the input transistor (M.sub.1) of amplifier circuit 3 (A.sub.3); and a fourth transistor (M.sub.P4) having its gate connected to the output (out) of amplifier circuit 2 (A.sub.2), its source connected to the first supply terminal (s.sub.1), and its drain connected the drain of the input transistor (M.sub.1) of amplifier circuit 4 (A.sub.4).

4. The oscillator circuit of claim 2, wherein each amplifier circuit (A.sub.1-A.sub.4) comprises a further transistor (M.sub.2) connecting the source of the input transistor (M.sub.1) of the same amplifier circuit (A.sub.1-A.sub.4) to the first supply terminal (s.sub.1), wherein the drain of the further transistor (M.sub.2) is connected to the source of the input transistor (M.sub.1) of the same amplifier circuit (A.sub.1-A.sub.4) and the source of the further transistor (M.sub.2) is connected to the first supply terminal (s.sub.1), and wherein the gate of the further transistor (M.sub.2) of amplifier circuit 1 (A.sub.1) is connected to the output of the amplifier circuit 3 (A.sub.3); the gate of the further transistor (M.sub.2) of amplifier circuit 2 (A.sub.2) is connected to the output of the amplifier circuit 4 (A.sub.4); the gate of the further transistor (M.sub.2) of amplifier circuit 3 (A.sub.3) is connected to the output of the amplifier circuit 1 (A.sub.1); and the gate of the further transistor (M.sub.2) of amplifier circuit 4 (A.sub.4) is connected to the output of the amplifier circuit 2 (A.sub.2).

5. The oscillator circuit of claim 1, wherein each of the N amplifier circuits (A.sub.1-A.sub.N) comprises an attenuator circuit (ATT.sub.in) connecting the gate of the input transistor (M.sub.1) to the input (in) of the amplifier circuit (A.sub.j).

6. The oscillator circuit of claim 1, wherein each of the N amplifier circuits (A.sub.1-A.sub.N) comprises a cascode transistor (M.sub.casc) connecting the drain of the input transistor (M.sub.1) to the internal node (x).

7. The oscillator circuit of claim 1, wherein the first resonance circuit (R.sub.1) is configured to have a first resonance frequency f.sub.0 and the second resonance circuit (R.sub.2) is configured to have a second resonance frequency f.sub.P≥2f.sub.0.

8. The oscillator circuit of claim 7, wherein f.sub.P is an integer multiple of f.sub.0.

9. The oscillator circuit of claim 1, wherein the oscillator circuit is a voltage-controlled oscillator circuit.

10. The oscillator circuit of claim 1, wherein the oscillator circuit is a digitally-controlled oscillator circuit.

11. A frequency synthesizer circuit comprising the oscillator circuit of claim 1.

12. The frequency synthesizer circuit of claim 11, wherein the frequency synthesizer circuit is a phase-locked loop circuit.

13. An integrated circuit comprising the oscillator circuit of claim 1.

14. An electronic apparatus comprising the oscillator circuit of claim 1.

15. The electronic apparatus of claim 14, wherein the electronic apparatus is a communication apparatus.

16. The electronic apparatus of claim 15, wherein the communication apparatus is a wireless communication device for a cellular communications system.

17. The electronic apparatus of claim 15, wherein the communication apparatus is a base station for a cellular communications system.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram of a quadrature oscillator.

(2) FIGS. 2-7 show schematic circuit diagrams of embodiments of the present disclosure.

(3) FIG. 8 illustrates a communication environment.

(4) FIG. 9 illustrates a transceiver circuit.

(5) FIG. 10 illustrates an integrated circuit.

DETAILED DESCRIPTION

(6) It should be emphasized that the term “comprises/comprising” when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

(7) FIG. 2 is a schematic circuit diagram of an oscillator circuit 15 according to an embodiment of the present disclosure. It comprises N amplifier circuits A.sub.1-A.sub.4. In embodiments shown in this disclosure, N=4. However, other values of N may be used in other embodiments, such as integer multiples of 4. In the following description, the amplifier circuits are numbered 1 to N. In the drawings, amplifier circuit j (or “the j:th amplifier circuit”) is provided with the reference sign A.sub.j. The amplifier circuits are connected in a ring, wherein for each j∈{1,2, . . . , N−1}, an output out of the j:th amplifier circuit A.sub.j is connected to an input in of the (j+1):th amplifier circuit A.sub.j+1. The output of the N:th amplifier circuit A.sub.N is connected to the input of the 1:st amplifier circuit A.sub.1. Furthermore, the oscillator circuit 15 comprises a first supply terminal s.sub.1 and a second supply terminal s.sub.2 configured to receive a supply voltage between the first supply terminal s.sub.1 and the second supply terminal s.sub.2.

(8) Reference signs are shown in the drawings for the 1:st amplifier circuit A.sub.1. The same reference signs apply for the other amplifier circuits A.sub.2-A.sub.4, as would be readily understood by the skilled person. Each of the N amplifier circuits A.sub.1-A.sub.4 comprises an input transistor M.sub.1 having its gate connected to the input in of the amplifier circuit, its drain connected to an internal node marked x, and its source connected to the first supply terminal s.sub.1. In the drawings, the input transistor M1 is an NMOS transistor, and the second supply terminal s.sub.2 is connected to an electrical potential (labeled V.sub.DD) which is higher than the electrical potential (or “ground”, shown in the drawings with a ground symbol) that the first supply terminal s.sub.1 is connected to. However, in other embodiments, the input transistor M1 may be a PMOS transistor, in which case the first supply terminal s.sub.1 would be connected to the higher electrical potential and the second supply terminal s.sub.2 would be connected to the lower electrical potential. Said supply voltage is the difference between the higher and the lower electrical potential. Furthermore, other types of transistors may be used as well, such as bipolar transistors or other types of field-effect transistors.

(9) Each of the amplifier circuits A.sub.1-A.sub.4 comprises a first resonance circuit R.sub.1 comprising a first inductor L.sub.S and a first capacitor C.sub.S. The first inductor L.sub.S is connected between the internal node x and the output out of the amplifier circuit. The first capacitor C.sub.S is connected between the output out of the amplifier circuit and one of the first and the second supply terminals s.sub.1, s.sub.2. In the drawings, the first capacitor C.sub.S is connected to the first supply terminal s.sub.1, but in other embodiments it may be connected to the second supply terminal s.sub.2 instead.

(10) Furthermore, each of the amplifier circuits A.sub.1-A.sub.4 comprises a second resonance circuit R.sub.2 comprising a second inductor L.sub.P and a second capacitor C.sub.P. The second inductor L.sub.P and the second capacitor C.sub.P are connected in parallel between the internal node x and the second supply terminal s.sub.2.

(11) When CMOS inverters are used in an oscillator as in FIG. 1, a relatively high supply voltage is needed in order to start the oscillator. By including the second resonance circuit R.sub.2 instead of a transistor, the required supply voltage can be reduced in embodiments of the present disclosure compared with the oscillator in FIG. 1. Simulations indicate that supply voltages only slightly higher than the threshold voltage of the input transistor M.sub.1 is sufficient in some applications. Furthermore, since the CMOS inverter has both a PMOS transistor and an NMOS transistor driven by its input, a relatively high parasitic capacitance is obtained. With the amplifier circuits used in embodiments of the present disclosure, the use of complementary transistors (i.e. both NMOS and PMOS) is not necessary, whereby parasitic capacitance can be reduced compared with the oscillator in FIG. 1. The parasitics are lower if an NMOS transistor is used as the input transistor M.sub.1 compared with if a PMOS transistor is used as the input transistor M.sub.1, and NMOS transistors are generally faster than PMOS transistors, so using an NMOS transistor as the input transistor M.sub.1 is advantageous for obtaining high oscillation frequencies. Furthermore, the inclusion of the second resonance circuit R.sub.2 instead of a transistor provides more degrees of freedom to control the impedance of the harmonics, and to shape the drain waveform for high efficiency and low phase noise, in embodiments of the present disclosure compared with the oscillator in FIG. 1.

(12) FIG. 3 is a schematic circuit diagram of another embodiment of the oscillator circuit 15. In addition to the circuitry shown in FIG. 2, it comprises transistors M.sub.P1, M.sub.P2, M.sub.P3, and M.sub.P4. In FIG. 3, the transistors M.sub.P1, M.sub.P2, M.sub.P3, and M.sub.P4 are NMOS transistors. In embodiments where the input transistor M1 in each amplifier circuit A.sub.1-A.sub.4 is a PMOS transistor, transistors M.sub.P1, M.sub.P2, M.sub.P3, and M.sub.P4 may be implemented as PMOS transistors.

(13) Transistor M.sub.P1 has its gate connected to the output out of the 3rd amplifier circuit A.sub.3, its source connected to the first supply terminal s.sub.1, and its drain connected the drain of the input transistor M.sub.1 of the 1:st amplifier circuit A.sub.1.

(14) Transistor M.sub.P2 has its gate connected to the output out of the 4:th amplifier circuit A.sub.4, its source connected to the first supply terminal s.sub.1, and its drain connected the drain of the input transistor M.sub.1 of the 2:nd amplifier circuit A.sub.2.

(15) Transistor M.sub.P3 has its gate connected to the output out of the 1:st amplifier circuit A.sub.1, its source connected to the first supply terminal s.sub.1, and its drain connected the drain of the input transistor M.sub.1 of the 3rd amplifier circuit A.sub.3.

(16) The transistor M.sub.P4 has its gate connected to the output out of the 2:nd amplifier circuit A.sub.2, its source connected to the first supply terminal s.sub.1, and its drain connected the drain of the input transistor M.sub.1 of the 4:th amplifier circuit 4 A.sub.4.

(17) The additional transistors M.sub.P1, M.sub.P2, M.sub.P3, and M.sub.P4 in FIG. 3 provides suppression of non-quadrature oscillation modes providing a more robust quadrature oscillator. Four stage oscillators can, in theory, produce two or four phases. In FIG. 3, signals are injected using the parallel additional transistors M.sub.P1, M.sub.P2, M.sub.P3, and M.sub.P4 to ensure quadrature phase relation and prevent other modes of oscillation such as having only two phases in the oscillator instead of four. In FIG. 4 we inject the signals using series devices which results in still high figure of merit and reduced power consumption. The purpose is the same to force the oscillator to produce four phases with 90 degrees separation.

(18) FIG. 4 is a schematic circuit diagram of another embodiment of the oscillator circuit 15. In addition to the circuitry shown in FIG. 2, each amplifier circuit A.sub.1-A.sub.4 comprises a further transistor M.sub.2 connecting the source of the input transistor M.sub.1 of the same amplifier circuit A.sub.1-A.sub.4 to the first supply terminal s.sub.1. The drain of the further transistor M.sub.2 is connected to the source of the input transistor M.sub.1 of the same amplifier circuit A.sub.1-A.sub.4. The source of the further transistor M.sub.2 is connected to the first supply terminal s.sub.1. The gate of the further transistor M.sub.2 of the 1:st amplifier circuit A.sub.1 is connected to the output of the 3:rd amplifier circuit A.sub.3. The gate of the further transistor M.sub.2 of the 2:nd amplifier circuit A.sub.2 is connected to the output of the 4:th amplifier circuit A.sub.4. The gate of the further transistor M.sub.2 of the 3:rd amplifier circuit A.sub.3 is connected to the output of the 1:st amplifier circuit A.sub.1. The gate of the further transistor M.sub.2 of the 4:th amplifier circuit A.sub.4 is connected to the output of the 2:nd amplifier circuit A.sub.2. The further transistor M.sub.2 in each amplifier circuit A.sub.1-A.sub.4 in FIG. 4 provides suppression of non-quadrature oscillation modes. The function is similar to that described above in the context of FIG. 3, but in FIG. 4, the signals are instead injected using the series-connected further transistor M.sub.2.

(19) FIG. 5 illustrates how inductors may be implemented pairwise as transformers for the embodiment illustrated in FIG. 2 to save chip area. For simplicity, the capacitors are not shown in FIG. 5. First of all, since the signal currents in each pair of inductors placed together as a transformer are 180° out of phase, the mutual inductance between the inductors in the pair increases the effective inductance of each inductor in the pair. This allows the physical size of the inductors to be reduced. Furthermore, the inductors may be implemented with an interleaved layout on the chip surface, which further helps to save space.

(20) FIG. 6 is a schematic circuit diagram of another embodiment of the oscillator circuit 15. In FIG. 6, each of the amplifier circuits A.sub.1-A.sub.4 comprises an attenuator circuit ATT.sub.in connecting the gate of the input transistor M.sub.1 to the input in of the amplifier circuit. In FIG. 6, only amplifier circuit A.sub.1 is shown. The other amplifier circuits A.sub.2-A.sub.4 are implemented in the same way. The attenuator circuit ATT.sub.in may e.g. be implemented as a capacitive voltage divider. The attenuator circuit ATT.sub.in allows the supply voltage to be increased without damaging the input transistor M.sub.1. By increasing the supply voltage, an improved (reduced) phase noise can be obtained.

(21) FIG. 7 is a schematic circuit diagram of another embodiment of the oscillator circuit 15. In FIG. 6, each of the amplifier circuits A.sub.1-A.sub.4 comprises a cascode transistor M.sub.casc connecting the drain of the input transistor M.sub.1 to the internal node x. The cascode transistor M.sub.casc is of the same type as the input transistor M.sub.casc. The source of the cascode transistor M.sub.casc is connected to the drain of the input transistor M.sub.1. The drain of the cascode transistor M.sub.casc is connected to the internal node x. The gate of the cascode transistor M.sub.casc is biased with a voltage V.sub.casc. In FIG. 7, only amplifier circuit A.sub.1 is shown. The other amplifier circuits A.sub.2-A.sub.4 are implemented in the same way. The inclusion of the cascode transistor M.sub.casc increases the voltage swing that the oscillator circuit 15 can handle.

(22) In some embodiments of the oscillator circuit 15, the first resonance circuit R.sub.1 is tuned or otherwise configured to have a first resonance frequency f.sub.0. The first resonance frequency f.sub.0 is typically equal to or relatively close to the oscillation frequency of the oscillator 15.

(23) In some embodiments of the oscillator circuit 15, the second resonance circuit R.sub.2 is also tuned or otherwise configured to have the same resonance frequency f.sub.0. This facilitates keeping the amount of fundamental frequency current drawn by the second resonance circuit R.sub.2 relatively low. However, the inventors have realized that higher DC to RF conversion efficiency and oscillator phase noise figure of merit (FoM) can be achieved by a more suitable harmonic termination. This is achieved by a relatively low drain voltage and current waveform overlap, similar to a class-E power amplifier.

(24) The embodiment of the oscillator circuit 15 shown in FIG. 3 has been simulated with the second resonance circuit R.sub.2 tuned to a resonance frequency f.sub.P. In a first simulation, f.sub.P=f.sub.0. It was observed that the resulting drain current is rich in harmonics due to a class C bias regime, but more importantly a considerable current is conducted when the drain voltage level is high. This results in a relatively poor DC-RF conversion efficiency. Moreover, the conduction at zero crossings is a major source of unwanted phase noise.

(25) In subsequent simulations, f.sub.P=nf.sub.0, where n=2,3,4,5,6. That is, the second resonance circuit R.sub.2 was tuned to one of the harmonics of f.sub.0. This results in class-E like operation. In such a regime the efficiency is boosted (compared with f.sub.P=f.sub.0), and the phase noise is improved thanks to the reduced current conduction in the voltage zero-crossings. For instance, the simulations showed that, when the tank is tuned to the second harmonic (i.e. n=2), the phase noise at 100 MHz offset from a 3 GHz carrier and the FoM could be improved by more than 7 dB compared with when f.sub.P=f.sub.0. Similar results were obtained for values of n≥3. The quantitative results of course depend on the particular component models and frequencies used in the simulations. However, qualitatively, the results hold for other component models and frequencies as well. The transistor models used in the simulations were from a low-power 22 nm CMOS process, and the inductors used in the simulations had a Q value of about 10 at 3 GHz. Component parameters used in the simulations are indicated in the table below

(26) TABLE-US-00001 Parameter Value W/L (Width/Length) of M.sub.1 200 μm/18 nm W/L of M.sub.2 100 μm/18 nm L.sub.S 1 nH C.sub.S 2 pF L.sub.P swept from 1 nH to 166 pH C.sub.P swept from 2 pF to 333 fF V.sub.DD 200 mV

(27) According to some embodiments, in view of the above, the second resonance circuit R.sub.2 is configured to have a second resonance frequency f.sub.P≥2f.sub.0. In particular, in some embodiments, f.sub.P is an integer multiple of f.sub.0.

(28) According to some embodiments, the oscillator circuit 15 is a voltage-controlled oscillator (VCO) circuit. For instance, each amplifier circuit A.sub.1-A.sub.4 may comprise a first voltage-controlled capacitor, such as a varactor, (not shown) connected in parallel with the capacitor C.sub.S for controlling the oscillation frequency by controlling the resonance frequency of the resonance circuit R.sub.1. The first voltage-controlled capacitor may be controlled via a control voltage. Each amplifier circuit A.sub.1-A.sub.4 may further comprise a second voltage-controlled capacitor, such as a varactor, (not shown) connected in parallel with the capacitor C.sub.P for tuning the resonance frequency of the resonance circuit R.sub.2. The second voltage-controlled capacitor may be controlled via a control voltage, such as the same control voltage that controls the first voltage-controlled capacitor.

(29) According to some embodiments, the oscillator circuit 15 is a digitally-controlled oscillator (VCO) circuit. For instance, each amplifier circuit A.sub.1-A.sub.4 may comprise a first digitally controlled capacitor connected in parallel with the capacitor C.sub.S for controlling the oscillation frequency by controlling the resonance frequency of the resonance circuit R.sub.1. Each amplifier circuit A.sub.1-A.sub.4 may further comprise a second digitally controlled capacitor (not shown) connected in parallel with the capacitor C.sub.P for tuning the resonance frequency of the resonance circuit R.sub.2.

(30) FIG. 8 illustrates a communication environment wherein embodiments of the present invention may be employed. A wireless communication device 1, or wireless device 1 for short, of a cellular communications system is in wireless communication with a radio base station 2 of the cellular communications system. The wireless device 1 may be what is generally referred to as a user equipment (UE). The wireless devices 1 is depicted in FIG. 8 as a mobile phone, but may be any kind of device with cellular communication capabilities, such as a tablet or laptop computer, machine-type communication (MTC) device, or similar. Furthermore, a cellular communications system is used as an example in this disclosure. However, embodiments of the present disclosure may be applicable in other types of systems as well, such as but not limited to WiFi systems.

(31) The radio base station 2 and wireless device 1 are examples of what in this disclosure is generically referred to as communication apparatuses. Embodiments are described below in the context of a communication apparatus in the form of the radio base station 2 or wireless device 1. However, other types of communication apparatuses can be considered as well, such as a WiFi access point or WiFi enabled device.

(32) FIG. 9 is a block diagram of an embodiment of a transceiver circuit 10, which can be comprised in a communication apparatus, such as the radio base station 2 or the wireless device 1. In the embodiment illustrated in FIG. 9, the transceiver circuit 10 comprises the oscillator circuit 15. As illustrated in FIG. 9, the oscillator circuit 15 may be comprised in a frequency synthesizer, such as a phase-locked loop (PLL) 17.

(33) Furthermore, in the embodiment illustrated in FIG. 9, the transceiver circuit 10 comprises a transmitter circuit 20 and a receiver circuit 30, which may utilize the oscillating signal generated by the oscillator circuit 15 as local oscillator signals. For instance, the local oscillator signals may be utilized for driving one or more mixer circuits in the transmitter circuit 20 and/or the receiver circuit 30. In FIG. 9, the transmitter circuit 20 and the receiver circuit 30 are illustrated as connected to the same antenna 35. However, this is only an example. In some embodiments, separate transmit and receive antennas may be used.

(34) Embodiments of the oscillator circuit 15 are suitable for integration on an integrated circuit. This is schematically illustrated in FIG. 10, showing an integrated circuit 100 comprising the oscillator circuit 15.

(35) The disclosure above refers to specific embodiments. However, other embodiments than the above described are possible within the scope of the invention. For example, the oscillator circuit 15 may be used in other types of electronic apparatuses than communication apparatuses. The different features and steps of the embodiments may be combined in other combinations than those described.