Submodule topology circuit for modular multilevel converter and method for controlling same

Abstract

The present disclosure relates to a submodule topology circuit for a modular multilevel converter and a method for controlling same. The submodule topology comprises an inlet port and an outlet port, at least two half-bridge submodules, a plurality of first switching devices, a plurality of thyristors and a plurality of diodes, wherein the at least two half-bridges are connected in series and are provided between the inlet port and the outlet port, and each of the half-bridge submodules is provided with an input port, a first output port and a second output port.

Claims

1. A submodule topology circuit for a modular multilevel converter, comprising an inlet port, an outlet port, at least two half-bridge submodules, a plurality of first switching devices, a plurality of thyristors and a plurality of diodes; wherein the at least two half-bridge submodules are connected in series and are provided between the inlet port and the outlet port, and each of the half-bridge submodules is provided with an input port, a first output port and a second output port; among two adjacent half-bridge submodules, one corresponding first switching device of the plurality of first switching devices is provided between the second output port of a front half-bridge submodule and the input port of a rear half-bridge submodule, a head-end first switching device of the plurality of first switching devices is provided between the input port of a first half-bridge submodule of the at least two half-bridge submodules and the inlet port; among the two adjacent half-bridge submodules, one corresponding thyristor of the plurality of thyristors is provided between the second output port of the front half-bridge submodule and the first output port of the rear half-bridge submodule, a head-end thyristor of the plurality of thyristors is provided between the first output port of the first half-bridge submodule and the inlet port; the second output port of a last half-bridge submodule of the at least two half-bridge submodules is connected to a tail-end thyristor of the plurality of thyristors and a tail-end first switching device of the plurality of switching devices, wherein the tail-end thyristor and the tail-end first switching device are connected in parallel; among the two adjacent half-bridge submodules of the at least two half-bridge submodules, one corresponding diode of the plurality of diodes is provided between the first output port of the front half-bridge submodule and the second output port of the rear half-bridge submodule; a head-end diode of the plurality of diodes is provided between the inlet port and the second output port of the first half-bridge submodule of the at least two half-bridge submodules, a tail-end diode of the plurality of diodes is provided between the outlet port and the first output port of the last half-bridge submodule of the at least two half-bridge submodules.

2. The topology circuit according to claim 1, wherein each half-bridge submodule is composed of two second switching devices and one capacitor; an emitter of a first second switching device is connected to a collector of a second switching device to form the input port of each half-bridge submodule; a collector of the first second switching device is connected to an anode of the capacitor to form the first output port of each half-bridge submodule; an emitter of the second switching device is connected to a cathode of the capacitor to form the second output port of each half-bridge submodule.

3. The topology circuit according to claim 1, wherein the at least two half-bridge submodules are H.sub.1, H.sub.2 . . . H.sub.N arranged in such sequence, N being a number of the at least two half-bridge submodules; the plurality of first switching devices are Q.sub.1, Q.sub.2 . . . Q.sub.N+1 arranged in such sequence, a number of the plurality of first switching devices is N+1, the head-end first switching device is Q.sub.1, and the tail-end first switching device is Q.sub.N+1; the plurality of thyristors are VT.sub.1, VT.sub.2 . . . VT.sub.N+1 arranged in such sequence, a number of the plurality of thyristors is N+1, the head-end thyristor is VT.sub.1, and the tail-end thyristor is VT.sub.N+1; the plurality of diodes are D1, D.sub.2, D.sub.3 . . . D.sub.N+1 arranged in such sequence, a number of the plurality of diodes is N+1, the head-end diode is D.sub.1, and the tail-end diode is DN.sub.N+1; wherein, N≥2.

4. The topology circuit according to claim 3, wherein an emitter of the head-end first switching device is connected to the inlet port; and a collector of the head-end first switching device is connected to the input port of the first half-bridge submodule of the at least two half-bridge submodules; an emitter of J.sub.th first switching device is connected to a second output port of J-1.sub.th half-bridge submodule, and a collector of J.sub.th first switching device is connected to an input port of J.sub.th half-bridge submodule; an emitter of the tail-end first switching device is connected to a second output port of N.sub.th half-bridge submodule, and a collector of the tail-end first switching device is connected to the outlet port; J is 2, 3 . . . N, N≥2.

5. The topology circuit according to claim 3, wherein an anode of the head-end thyristor of the plurality of thyristors is connected to the inlet port, and a cathode of the head-end thyristor is connected to the first output port of the first half-bridge submodule; an anode of J.sub.th thyristor is connected to the second output port of J-1.sub.th half-bridge submodule, and a cathode of J.sub.th thyristor is connected to the first output port of J.sub.th half-bridge submodule; an anode of the tail-end thyristor is connected to the second output port of N.sub.th half-bridge submodule, and a cathode of the tail-end thyristor is connected to the outlet port; J is 2, 3 . . . N, N≥2.

6. The topology circuit according to claim 3, wherein a cathode of the head-end diode is connected to the inlet port, and an anode of the head-end diode is connected to the second output port of the first half-bridge submodule; a cathode of J.sub.th diode is connected to the first output port of J-1.sub.th half-bridge submodule, and an anode of J.sub.th diode is connected to the second output port of J.sub.th half-bridge submodule; a cathode of the tail-end diode is connected to the first output port of N.sub.th half-bridge submodule, and an anode of the tail-end diode is connected to the outlet port; J is 2, 3 . . . N, N≥2.

7. The topology circuit according to claim 1, wherein the plurality of first switching devices are insulated gate bipolar transistors or metal-oxide semiconductor field effect transistors.

8. The topology circuit according to claim 2, wherein the second switching devices are insulated gate bipolar transistors or metal-oxide semiconductor field effect transistors.

9. A method of controlling a submodule topology circuit for a modular multilevel converter, for controlling the submodule topology circuit for the modular multilevel converter of claim 1, the method comprising: when the modular multilevel converter is in normal operation, setting an initial state: blocking a gate trigger signal of the plurality of thyristors, and triggering the plurality of first switching devices to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state; detecting a fault signal, and when a short-circuit fault on DC side of the modular multilevel converter is detected, blocking a trigger signal of the second switching devices in each of the at least two half-bridge submodules, and blocking a trigger signal of the plurality of first switching devices; detecting a direction of the short-circuit fault current on the DC side, when the direction of the short-circuit fault current on the DC side is forward, triggering the plurality of thyristors to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port and flows through the plurality of thyristors and the capacitors in the at least two half-bridge submodules, and detecting a value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0; and when the direction of the short-circuit fault current on the DC side is reverse, blocking a trigger signal of the plurality of thyristors in such a manner that the short-circuit fault current on the DC side enters from the outlet port and flows through the plurality of diodes and the capacitor in each of the at least two half-bridge submodules; and detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

10. A method of controlling a submodule topology circuit for a modular multilevel converter, for controlling the submodule topology circuit for the modular multilevel converter of claim 2, the method comprising: when the modular multilevel converter is in normal operation, setting an initial state: blocking a gate trigger signal of the plurality of thyristors, and triggering the plurality of first switching devices to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state; detecting a fault signal, and when a short-circuit fault on DC side of the modular multilevel converter is detected, blocking a trigger signal of the second switching devices in each of the at least two half-bridge submodules, and blocking a trigger signal of the plurality of first switching devices; detecting a direction of the short-circuit fault current on the DC side, when the direction of the short-circuit fault current on the DC side is forward, triggering the plurality of thyristors to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port and flows through the plurality of thyristors and the capacitors in the at least two half-bridge submodules, and detecting a value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0; and when the direction of the short-circuit fault current on the DC side is reverse, blocking a trigger signal of the plurality of thyristors in such a manner that the short-circuit fault current on the DC side enters from the outlet port and flows through the plurality of diodes and the capacitor in each of the at least two half-bridge submodules; and detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

11. A method of controlling a submodule topology circuit for a modular multilevel converter, for controlling the submodule topology circuit for the modular multilevel converter of claim 3, the method comprising: when the modular multilevel converter is in normal operation, setting an initial state: blocking a gate trigger signal of the plurality of thyristors, and triggering the plurality of first switching devices to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state; detecting a fault signal, and when a short-circuit fault on DC side of the modular multilevel converter is detected, blocking a trigger signal of the second switching devices in each of the at least two half-bridge submodules, and blocking a trigger signal of the plurality of first switching devices; detecting a direction of the short-circuit fault current on the DC side, when the direction of the short-circuit fault current on the DC side is forward, triggering the plurality of thyristors to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port and flows through the plurality of thyristors and the capacitors in the at least two half-bridge submodules, and detecting a value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0; and when the direction of the short-circuit fault current on the DC side is reverse, blocking a trigger signal of the plurality of thyristors in such a manner that the short-circuit fault current on the DC side enters from the outlet port and flows through the plurality of diodes and the capacitor in each of the at least two half-bridge submodules; and detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

12. A method of controlling a submodule topology circuit for a modular multilevel converter, for controlling the submodule topology circuit for the modular multilevel converter of claim 4, the method comprising: when the modular multilevel converter is in normal operation, setting an initial state: blocking a gate trigger signal of the plurality of thyristors, and triggering the plurality of first switching devices to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state; detecting a fault signal, and when a short-circuit fault on DC side of the modular multilevel converter is detected, blocking a trigger signal of the second switching devices in each of the at least two half-bridge submodules, and blocking a trigger signal of the plurality of first switching devices; detecting a direction of the short-circuit fault current on the DC side, when the direction of the short-circuit fault current on the DC side is forward, triggering the plurality of thyristors to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port and flows through the plurality of thyristors and the capacitors in the at least two half-bridge submodules, and detecting a value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0; and when the direction of the short-circuit fault current on the DC side is reverse, blocking a trigger signal of the plurality of thyristors in such a manner that the short-circuit fault current on the DC side enters from the outlet port and flows through the plurality of diodes and the capacitor in each of the at least two half-bridge submodules; and detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

13. A method of controlling a submodule topology circuit for a modular multilevel converter, for controlling the submodule topology circuit for the modular multilevel converter of claim 5, the method comprising: when the modular multilevel converter is in normal operation, setting an initial state: blocking a gate trigger signal of the plurality of thyristors, and triggering the plurality of first switching devices to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state; detecting a fault signal, and when a short-circuit fault on DC side of the modular multilevel converter is detected, blocking a trigger signal of the second switching devices in each of the at least two half-bridge submodules, and blocking a trigger signal of the plurality of first switching devices; detecting a direction of the short-circuit fault current on the DC side, when the direction of the short-circuit fault current on the DC side is forward, triggering the plurality of thyristors to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port and flows through the plurality of thyristors and the capacitors in the at least two half-bridge submodules, and detecting a value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0; and when the direction of the short-circuit fault current on the DC side is reverse, blocking a trigger signal of the plurality of thyristors in such a manner that the short-circuit fault current on the DC side enters from the outlet port and flows through the plurality of diodes and the capacitor in each of the at least two half-bridge submodules; and detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

14. A method of controlling a submodule topology circuit for a modular multilevel converter, for controlling the submodule topology circuit for the modular multilevel converter of claim 6, the method comprising: when the modular multilevel converter is in normal operation, setting an initial state: blocking a gate trigger signal of the plurality of thyristors, and triggering the plurality of first switching devices to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state; detecting a fault signal, and when a short-circuit fault on DC side of the modular multilevel converter is detected, blocking a trigger signal of the second switching devices in each of the at least two half-bridge submodules, and blocking a trigger signal of the plurality of first switching devices; detecting a direction of the short-circuit fault current on the DC side, when the direction of the short-circuit fault current on the DC side is forward, triggering the plurality of thyristors to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port and flows through the plurality of thyristors and the capacitors in the at least two half-bridge submodules, and detecting a value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0; and when the direction of the short-circuit fault current on the DC side is reverse, blocking a trigger signal of the plurality of thyristors in such a manner that the short-circuit fault current on the DC side enters from the outlet port and flows through the plurality of diodes and the capacitor in each of the at least two half-bridge submodules; and detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

15. A method of controlling a submodule topology circuit for a modular multilevel converter, for controlling the submodule topology circuit for the modular multilevel converter of claim 7, the method comprising: when the modular multilevel converter is in normal operation, setting an initial state: blocking a gate trigger signal of the plurality of thyristors, and triggering the plurality of first switching devices to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state; detecting a fault signal, and when a short-circuit fault on DC side of the modular multilevel converter is detected, blocking a trigger signal of the second switching devices in each of the at least two half-bridge submodules, and blocking a trigger signal of the plurality of first switching devices; detecting a direction of the short-circuit fault current on the DC side, when the direction of the short-circuit fault current on the DC side is forward, triggering the plurality of thyristors to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port and flows through the plurality of thyristors and the capacitors in the at least two half-bridge submodules, and detecting a value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0; and when the direction of the short-circuit fault current on the DC side is reverse, blocking a trigger signal of the plurality of thyristors in such a manner that the short-circuit fault current on the DC side enters from the outlet port and flows through the plurality of diodes and the capacitor in each of the at least two half-bridge submodules; and detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

16. A method of controlling a submodule topology circuit for a modular multilevel converter, for controlling the submodule topology circuit for the modular multilevel converter of claim 8, the method comprising: when the modular multilevel converter is in normal operation, setting an initial state: blocking a gate trigger signal of the plurality of thyristors, and triggering the plurality of first switching devices to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state; detecting a fault signal, and when a short-circuit fault on DC side of the modular multilevel converter is detected, blocking a trigger signal of the second switching devices in each of the at least two half-bridge submodules, and blocking a trigger signal of the plurality of first switching devices; detecting a direction of the short-circuit fault current on the DC side, when the direction of the short-circuit fault current on the DC side is forward, triggering the plurality of thyristors to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port and flows through the plurality of thyristors and the capacitors in the at least two half-bridge submodules, and detecting a value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0; and when the direction of the short-circuit fault current on the DC side is reverse, blocking a trigger signal of the plurality of thyristors in such a manner that the short-circuit fault current on the DC side enters from the outlet port and flows through the plurality of diodes and the capacitor in each of the at least two half-bridge submodules; and detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic circuit diagram according to an embodiment of the present disclosure.

(2) FIG. 2 is a schematic diagram of a half-bridge submodule according to an embodiment of the present disclosure.

(3) FIG. 3 is a schematic diagram according to an embodiment of the present disclosure, in which the fault current is forward.

(4) FIG. 4 is a schematic diagram according to an embodiment of the present disclosure, in which the fault current is reverse.

(5) FIG. 5 is a control flow chart according to an embodiment of the present disclosure;

(6) In the figures, H.sub.1, H.sub.2 . . . H.sub.N are half-bridge submodules,

(7) C.sub.SM1, C.sub.SM2 . . . C.sub.SMN are the capacitors in the half-bridge submodules,

(8) G.sub.11, G.sub.12, G.sub.21, G.sub.22 . . . G.sub.N1, G.sub.N2 are the second switching devices in the half-bridge submodules,

(9) Q.sub.1, Q.sub.2 . . . Q.sub.N, Q.sub.N+1 are the first switching devices,

(10) VT.sub.1, VT.sub.2 . . . VT.sub.N, VT.sub.N+1 are thyristors,

(11) D.sub.1, D.sub.2, D.sub.3 . . . D.sub.N, D.sub.N+1 are diodes,

(12) X is the inlet port, Y is the outlet port;

(13) The directions of arrows in FIGS. 3 and 4 indicate the direction of short-circuit fault current on the DC side.

DETAILED DESCRIPTION OF THE INVENTION

(14) As shown in FIG. 1, the MMC submodule topology circuit according to an embodiment of the present disclosure comprises an inlet port X, an outlet port Y, at least two half-bridge submodules, a plurality of first switching devices, a plurality of thyristors, and a plurality of diodes; wherein the at least two half-bridge submodules are connected in series and are provided between the inlet port X and the outlet port Y, and each of the half-bridge submodules is provided with an input port, a first output port and a second output port.

(15) Among two adjacent half-bridge submodules, one corresponding first switching device of the plurality of first switching devices is provided between the second output port of the front half-bridge submodule and the input port of the rear half-bridge submodule, a head-end first switching device of the plurality of first switching devices is provided between the input port of the first one of the at least two half-bridge submodules and the inlet port X.

(16) Among two adjacent half-bridge submodules, one corresponding thyristor of the plurality of thyristors is provided between the second output port of the front half-bridge submodule and the first output port of the rear half-bridge submodule, a head-end thyristor of the plurality of thyristors is provided between the first output port of the first half-bridge submodule and the inlet port X.

(17) The second output port of the last half-bridge submodule of the at least two half-bridge submodules is connected to a tail-end thyristor of the plurality of thyristors and a tail-end first switching device of the plurality of switching devices, wherein the tail-end thyristor and the tail-end first switching device are connected in parallel;

(18) Among the two adjacent half-bridge submodules of the at least two half-bridge submodules, one corresponding diode of the plurality of diodes is provided between the first output port of the front half-bridge submodule and the second output port of the rear half-bridge submodule.

(19) A head-end diode of the plurality of diodes is provided between the inlet port X and the second output port of the first half-bridge submodule of the at least two half-bridge submodules, a tail-end diode of the plurality of diodes is provided between the outlet port Y and the first output port of the last half-bridge submodule of the at least two half-bridge submodules.

(20) In an embodiment, as shown in FIG. 2, each half-bridge submodule is composed of two second switching devices and a capacitor; wherein the emitter of the first second switching device G.sub.J1 is connected to the collector of the second switching device G.sub.J2 to form the input port of each half-bridge submodule.

(21) The collector of the first second switching device G.sub.J1 is connected to the anode of the capacitor C.sub.SMJ to form the first output port of each half-bridge submodule.

(22) The emitter of the second switching device G.sub.J2 is connected to the cathode of the capacitor C.sub.SMJ to form the second output port of each half-bridge submodule.

(23) J may be 1˜N, N≥2.

(24) In an embodiment, a number of the at least two half-bridge submodules is N, and the at least two half-bridge submodules are H.sub.1, H.sub.2 . . . H.sub.N in such sequence.

(25) The number of the plurality of first switching devices is N+1, and the plurality of first switching devices are Q.sub.1, Q.sub.2 . . . Q.sub.N+1 in such sequence. The head-end first switching device is Q.sub.1, and the tail-end first switching device is Q.sub.N+1.

(26) The number of the plurality of thyristors is N+1, and the plurality of thyristors are VT.sub.1, VT.sub.2 . . . VT.sub.N+1 in such sequence. The head-end thyristor is VT.sub.1, and the tail-end thyristor is VT.sub.N+1.

(27) The number of the plurality of diodes is N+1, and the plurality of diodes are D.sub.1, D.sub.2, D.sub.3 . . . D.sub.N+1 in such sequence. The head-end diode is D.sub.1, and the tail-end diode is D.sub.N+1.

(28) Herein, N≥2.

(29) In an embodiment, the emitter of the head-end first switching device Q.sub.1 is connected to the inlet port X; and the collector of the head-end first switching device Q.sub.1 is connected to the input port of the first half-bridge submodule H.sub.1.

(30) The emitter of the J.sub.th switching device Q.sub.J is connected to the second output port of the J-1.sub.th half-bridge submodule H.sub.J−1, and the collector of the J.sub.th switching device Q.sub.J is connected to the input port of the J.sub.th half-bridge submodule H.sub.J.

(31) The emitter of the tail-end first switching device Q.sub.N+1 is connected to the second output port of the N.sub.th half-bridge submodule H.sub.N, and the collector of the tail-end first switching device Q.sub.N+1 is connected to the outlet port Y.

(32) J may be 2, 3 . . . N, N≥2.

(33) In an embodiment, the anode of the head-end thyristor VT.sub.1 of the plurality of thyristors is connected to the inlet port X, and the cathode of the head-end thyristor VT.sub.1 is connected to the first output port of the first half-bridge submodule H.sub.1.

(34) The anode of the J.sub.th thyristor VT.sub.J is connected to the second output port of the J-1.sub.th half-bridge submodule H.sub.J−1, and the cathode of the J.sub.th thyristor VT.sub.J is connected to the first output port of the J.sub.th half-bridge submodule H.sub.J.

(35) The anode of the tail-end thyristor VT.sub.n+1 is connected to the second output port of the N.sub.th half-bridge submodule H.sub.N, and the cathode of the tail-end thyristor VT.sub.n+1 is connected to the outlet port Y.

(36) J may be 2, 3 . . . N, N≥2.

(37) In an embodiment, the cathode of the head-end diode D.sub.1 is connected to the inlet port X, and the anode of the head-end diode D.sub.1 is connected to the second output port of the first half-bridge submodule H.sub.1.

(38) The cathode of the J.sub.th diode D.sub.J is connected to the first output port of the J-1.sub.th half-bridge submodule H.sub.J−1, and the anode of the J.sub.th diode D.sub.J is connected to the second output port of the J.sub.th half-bridge submodule H.sub.J.

(39) The cathode of the tail-end diode D.sub.N+1 is connected to the first output port of the N.sub.th half-bridge submodule, and the anode of the tail-end diode D.sub.N+1 is connected to the outlet port Y.

(40) J may be 2, 3 . . . N, N≥2.

(41) In an embodiment, the plurality of first switching devices may be insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBT) or metal-oxide semiconductor field effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET).

(42) In an embodiment, the second switching devices may be IGBT or MOSFET.

(43) The present disclosure further provides a method of controlling MMC submodule topology circuit, as shown in FIG. 5, comprising steps (1) to (4).

(44) In step (1), when the MMC is in normal operation, setting an initial state; blocking the gate trigger signal of the plurality of thyristors VT.sub.1, VT.sub.2 . . . VT.sub.N, VT.sub.N+1, and triggering the plurality of first switching devices Q.sub.1, Q.sub.2 . . . Q.sub.N, Q.sub.N+1 to enter a conducting state and two second switching devices in each of the at least two half-bridge submodules to enter a complementary conduction state.

(45) In step (2), detecting a fault signal, and when a short-circuit fault on the DC side of the MMC is detected, blocking the trigger signal of the second switching devices in all the half-bridge submodules, and blocking the trigger signal of the plurality of first switching devices Q.sub.1, Q.sub.2 . . . Q.sub.N, Q.sub.N+1; detecting the direction of the short circuit fault current on the DC side. If the direction of the fault current is forward, perform step (3); if the direction of the fault current is reverse, perform step (4).

(46) In step (3), triggering all the thyristors VT.sub.1, VT.sub.2 . . . VT.sub.N, VT.sub.N+1 to enter a conducting state, in which the short-circuit current on the DC side enters from the inlet port X and then flows through all the thyristors and the capacitors in all the half-bridge submodules, thereby effectively suppressing the short-circuit fault current on the DC side and avoiding the large current flowing through the switching device, as shown in FIG. 3. Further, detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

(47) In step (4), blocking the trigger signals of all the thyristors VT.sub.1, VT.sub.2 . . . VT.sub.N, VT.sub.N+1. In such case, all the thyristors are in the blocking state; the short-circuit fault current on the DC side enters from the outlet port Y and then flows through all the diodes and the capacitor in all the half-bridge submodules, thereby effectively suppressing the short-circuit fault current on the DC side, and avoiding the large current flowing through the switching device as shown in FIG. 4. Further, detecting the value of the short-circuit fault current on the DC side until the value of the short-circuit fault current on the DC side becomes 0.

(48) In the event of a fault during the operation according to the present disclosure, no matter the fault current is forward or reverse, a large fault current can be prevented from flowing through the switching devices or diodes connected in inverse parallel, and the damage to the switching devices that is caused by the fault current can be avoided. All switching devices, thyristors and diodes have the same withstand voltage, i.e., the voltage of capacitor of the submodule, thus, the submodule topology has a high degree of modularity and is easier to configure. It has a certain cascade logic relationship, and is more convenient to achieve modularity. In the event of the fault, regardless of whether the fault current is forward or reverse, all the capacitors in the submodules will be put into the MMC bridge arm in series to suppress the fault current. Therefore, the MMC submodule topology has a strong Fault current suppression capability.