METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Abstract

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.

Claims

1. A method for fabricating semiconductor device, comprising: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.

2. The method of claim 1, further comprising: forming a bottom electrode on the substrate; forming the MTJ stack on the bottom electrode; forming a stop layer on the MTJ stack; forming the top electrode on the stop layer; and
forming a hard mask on the top electrode.

3. The method of claim 2, wherein the first patterning process comprises removing the hard mask and the top electrode along the first direction.

4. The method of claim 3, wherein the second patterning process comprises: performing a first etching process to remove the hard mask and the top electrode along the second direction; and performing a second etching process to remove the etch stop layer, the MTJ stack, and the bottom electrode to form MTJs.

5. The method of claim 1, wherein the first direction is orthogonal to the second direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIGS. 1-4 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0008] FIG. 5 illustrates a structural view of MTJs or top electrodes fabricated according to FIGS. 1-4 according to an embodiment of the present invention.

[0009] FIG. 6 illustrates a structural view of MTJs or top electrodes fabricated according to FIGS. 1-4 according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0010] Referring to FIG. 1, FIG. 1 illustrates a method for fabricating a semiconductor device, or more specifically a MRAM device according to an embodiment of the present invention, in which the bottom portion of FIG. 1 illustrates a top view for fabricating the MRAM device, the top left portion of FIG. 1 illustrates a cross-section view for fabricating the MRAM device along the sectional line AA′, and the top right portion of FIG. 1 illustrates a cross-section view for fabricating the MRAM device along the sectional line BB′. As shown in FIG. 1, a substrate 12 made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si-Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MTJ region 14 and a logic region (not shown) are defined on the substrate 12.

[0011] Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer could also be formed on top of the substrate 12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate 12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer could be formed on the substrate 12 to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

[0012] Next, metal interconnect structure 16 is formed on the ILD layer on the MTJ region 14 and the logic region to electrically connect the aforementioned contact plugs, in which the metal interconnect structure 16 includes an inter-metal dielectric (IMD) layer 18 and metal interconnections 20 embedded in the IMD layer 18. In this embodiment, each of the metal interconnections 20 from the metal interconnect structure 16 preferably includes a via conductor, and each of the metal interconnections 20 could be interconnected within the IMD layer 18 according to a single damascene process or dual damascene process. For instance, each of the metal interconnections 20 could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the IMD layer 18 is preferably made of silicon oxide or ultra low-k (ULK) dielectric material and the metal interconnections 20 are preferably made of tungsten, but not limited thereto.

[0013] Next, a bottom electrode 22 is formed on the surface of the IMD layer 18, a MTJ stack 24 made of a pinned layer, a barrier layer, and a free layer are formed on the bottom electrode 22, and a top electrode 28 and a hard mask 30 are formed on the MTJ stack thereafter. It should be noted that since none of the above layers are patterned at this stage, the top view of the hard mask 30 shown on bottom portion of FIG. 1 is still un-patterned while the cross-section shown on the top left portion taken along the sectional line AA′ and the cross-section shown on the top right portion taken along the sectional line BB′ preferably share identical structures at this stage.

[0014] In this embodiment, the bottom electrode 22 and the top electrode 28 are preferably made of conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or combination thereof. The pinned layer could be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer could be made of insulating material including but not limited to for example oxides such as aluminum oxide (A1O.sub.x) or magnesium oxide (MgO). The free layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer could be altered freely depending on the influence of outside magnetic field. Preferably, the stop layer 26 could be made of any material having etching selectivity with the top electrode 28 such as silicon oxide or silicon nitride and the hard mask 30 is preferably made of silicon nitride.

[0015] Next, as shown in FIG. 2, a first patterning process is conducted along a first direction (such as Y-direction) to remove part of the hard mask 30 and part of the top electrode 28 and stop on the stop layer 26. Specifically, the first patterning process conducted at this stage preferably involves using a patterned mask (not shown) such as a patterned resist as mask to remove part of the hard mask 30 and part of the top electrode 28 along the Y-direction to form a patterned hard mask 30, a patterned top electrode 28, and one or more recesses 32 between the patterned hard mask 30, as shown in the cross-section view taken along the sectional line AA′ on top left portion of FIG. 2. As shown in the top view on the bottom portion of FIG. 2, the patterned hard mask 30 on the topmost level at this stage is preferably formed extending along the Y-direction in the shape of rectangular columns while the stop layer 26, the MTJ stack 24, and the bottom electrode 22 are not removed or still remained un-patterned at this stage.

[0016] Next, as shown in FIG. 3, a second patterning process is conducted along a second direction (such as X-direction) orthogonal to the first direction to remove part of the hard mask 30 and part of the top electrode 28 once more and stop on the stop layer 26. Specifically, the second patterning process conducted at this stage preferably involves using another patterned mask (not shown) such as a patterned resist as mask to remove part of the hard mask 30 and part of the top electrode 28 along the X-direction with a first etching process for forming a re-patterned hard mask 30, a re-patterned top electrode 28, and recess or recesses 34 between the re-patterned hard mask 30, as shown in the cross-section view taken along the sectional line BB′ on top right portion of FIG. 3. As shown in the top view on the bottom portion of FIG. 3, the re-patterned hard mask 30 on the topmost level at this stage is preferably transformed or altered from rectangular or columnar strips to a plurality of squares while the stop layer 26, the MTJ stack 24, and the bottom electrode 22 are still not removed and remained un-patterned at this stage.

[0017] Next, as shown in FIG. 4, the second patterning process is continued by removing part of the remaining MTJ stack 24. Specifically, the remaining second patterning process conducted at this stage preferably involves carrying out a second etching process by directly using the patterned hard mask 30 as mask to remove the stop layer 26, MTJ stack 24, bottom electrode 22, and even part of the IMD layer 18 not covered by the hard mask 30 for forming a plurality of MTJs 36, 38, 40 on the substrate 12. Next, one or more IMD layers (not shown) could be formed on and surround the MTJs 36, 38, 40, and metal interconnections are formed in the IMD layers to electrically connect each of the top electrodes 28. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0018] Referring to FIG. 5, the top portions of FIG. 5 illustrates structural views of the MTJs 36, 38, 40 fabricated according to FIGS. 1-4 according to an embodiment of the present invention and the bottom portion of FIG. 5 illustrates a top view of the MTJs 36, 38, 40 or top electrodes 28 of the semiconductor device. As shown in FIG. 5, the semiconductor device includes at least a MTJ such as MTJs 36, 38, 40 disposed on the substrate 12, an IMD layer 18 disposed on the substrate 12 to surround the MTJs 36, 38, 40, and a top electrode 28 disposed on each of the MTJs 36, 38, 40, in which a top view of each of the MTJs 36, 38, 40 or the top electrodes 28 includes at least one corner and the at least one corner is less than 90 degrees.

[0019] Viewing from a more detailed perspective, the top view of each of the top electrodes 28 could include a quadrilateral having four corners 58, 60, 62, 64, in which at least one corner 58 from the four corners could be less than 90 degrees, each of at least two corners 58, 60 could be less than 90 degrees, each of at least three corners 58, 60, 62 could be less than 90 degrees, or each of the four corners 58, 60, 62, 64 could be less than 90 degrees. Preferably, the quadrilateral includes a first side 42 and a second side 44 extending along a first direction such as Y-direction, a third side 46 connecting the first side 42 and the second side 44, and a fourth side 48 connecting the first side 42 and the second side 44, in which each of the third side 46 and the fourth side 48 includes a curve or more specifically a concave curve.

[0020] Referring to FIG. 6, the top portions of FIG. 6 illustrates structural views of the MTJs 36, 38, 40 fabricated according to FIGS. 1-4 according to an embodiment of the present invention and the bottom portion of FIG. 6 illustrates a top view of the MTJs 36, 38, 40 or top electrodes 28 of the semiconductor device. As shown in FIG. 6, the semiconductor device includes at least a MTJ such as MTJs 36, 38, 40 disposed on the substrate 12, an IMD layer 18 disposed on the substrate 12 to surround the MTJs 36, 38, 40, and a top electrode 28 disposed on each of the MTJs 36, 38, 40, in which a top view of each of the MTJs 36, 38, 40 or the top electrodes 28 includes at least one corner and the at least one corner is less than 90 degrees.

[0021] In this embodiment, the top view of each of the top electrodes 28 could include a hexagon having at least four corners 66, 68, 70, 72, in which at least one corner 66 from the four corners could be less than 90 degrees, each of at least two corners 66, 68 could be less than 90 degrees, each of at least three corners 66, 68, 70 could be less than 90 degrees, or each of the four corners 66, 68, 70, 72 could be less than 90 degrees. Preferably, the hexagon includes a first side 50 and a second side 52 extending along a first direction such as Y-direction, a third side 54 connecting the first side 50 and the second side 52, and a fourth side 56 connecting the first side 50 and the second side 52, in which each of the third side 54 and the fourth side 56 includes a V-shape.

[0022] Overall, the present invention preferably employs a double patterning and double etching (2P2E) approach to pattern the MTJ stack into a plurality of MTJs, in which the double patterning and double etching process could be accomplished by first conducting a first patterning process along a first direction to remove part of the top electrode, conducting a first stage etching process of the second patterning process along a second direction to remove part of the hard mask and part of the top electrode, and then conducting a second stage etching process of the second patterning process to remove part of the MTJ stack and part of the bottom electrode to form a plurality of MTJs. By using the aforementioned 2P2E approach to form the MTJs it would not only be desirable to obtain the top view outlines shown in FIGS. 5-6, but also obtain better control for critical dimension of the device as well as achieving better shrinkage.

[0023] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.