FBAR Filter with Trap Rich Layer

Abstract

An acoustic resonator forms a component of an FBAR filter that includes a trap-rich layer to avoid parasitic conduction by degrading carrier lifetimes of a free charge carriers. The acoustic resonator has a first electrode, a second electrode disposed parallel to the first planar portion and a piezoelectric layer disposed between and contacting both the first and second planar electrodes. A silicon-based a support layer is bonded to the second electrode and includes a trap region. The acoustic resonator may be manufactured by (a) depositing the trap region on the support layer; (b) oxidizing a surface of the trap region; (c) depositing a bonding layer on the oxidized surface of the trap region; (d) bonding a first electrode to the bonding layer; (e) contacting a first side of a piezoelectric layer to the electrode; and (f) contacting a second side of the piezoelectric layer a second electrode.

Claims

1. An acoustic resonator, comprising: a first electrode having a first planar portion; a second electrode having a second planar portion disposed parallel to the first planar portion; a piezoelectric layer disposed between and contacting both the first planar portion and the second planar portion; and a support layer bonded to the second electrode, the support layer having a trap-rich layer that degrades a carrier lifetimes of a free charge carrier.

2. The acoustic resonator of claim 1 wherein the trap-rich layer is selected from the group consisting of amorphous silicon and polycrystalline silicon.

3. The acoustic resonator of claim 2 wherein the trap-rich layer has a thickness of from 500 nanometers (nm) and 800 nm.

4. The acoustic resonator of claim 3 wherein a silicon dioxide insulating layer is interposed between the trap-rich layer and both the first electrode and the second electrode.

5. A method for the manufacture of an acoustic resonator, comprising the steps of: a) depositing a trap-rich layer on a first side of a first substrate; b) oxidizing a surface of the trap-rich layer, the trap-rich layer effective to degrade a carrier lifetime of a free charge carrier; c) depositing a first bonding layer on the oxidized surface of the trap-rich layer; d) bonding a first side of a first electrode having a first planar portion to the first bonding layer; e) contacting a first side of a piezoelectric layer to the first planar portion; and contacting a second side of the piezoelectric layer to a first planar portion of a second electrode.

6. The method of claim 5 wherein the first substrate is selected to be a silicon handle wafer and the trap-rich layer is selected to be either amorphous silicon on polycrystalline silicon.

7. The method of claim 6 wherein the silicon handle wafer is selected to have a resistivity exceeding 3000 ohm*cm.

8. The method of claim 7 wherein the trap-rich layer is deposited to a thickness of between 500 nm and 800 nm.

9. The method of claim 8 wherein oxidizing of the trap-rich layer includes partially oxidizing the surface of the trap region by one or more of thermal oxidation, mechanical polishing and thermal stress releasing to thereby form a silicon oxide insulating layer.

10. The method of claim 7 wherein an oxide layer on an opposing second side of the silicon handle wafer is removed by one or more grinding, chemical etch, plasma dry etching.

11. The method of claim 5 wherein step (d)—bonding further includes: supporting the piezoelectric layer and the first electrode on a second substrate with the piezoelectric layer adjacent the second support and an opposing second side of the first electrode adjacent the piezoelectric layer; depositing a second bonding layer on the first side of the first electrode; and fusing the first bonding layer to the second bonding layer.

12. The method of claim 11 including selecting the first bonding layer and the second bonding layer to be gold or a gold—indium alloy.

13. The method of claim 12 wherein the first bonding layer and the second bonding layer are deposited by a technique selected from group of e-beam evaporation coating, sputtering and molecular beam epitaxy.

14. The method of claim 13 including depositing an adhesion layer between one or both of the first bonding layer and the first electrode and the second bonding layer and the oxidized surface of the trap-rich layer.

15. The method of claim 14 including selecting the adhesion layer to be titanium or a titanium-tungsten alloy.

16. The method of claim 13 including selecting the second substrate to be sapphire.

17. An organic based wafer level package that includes an acoustic resonator, comprising: the acoustic resonator having: a first electrode having a first planar portion; a second electrode having a second planar portion disposed parallel to the first planar portion; a piezoelectric layer disposed between and contacting both the first planar portion and the second planar portion; and a support layer bonded to the second electrode, the support layer having a trap-rich layer that degrades a carrier lifetimes of a free charge carrier an organic wall contacting the first side of the piezoelectric layer with a first wall via extending through the organic wall and contacting the first electrode and a second wall via extending through the organic wall and contacting the second electrode; an organic roof having first and second opposing sides with the first side bonded to the organic wall with a first roof via aligned with the first wall via and a second roof via aligned with the second wall via, wherein a combination of the organic wall, the organic roof and the first planar portion define a first acoustic gap; a silicon handle contacting the second side of the piezoelectric layer; and a silicon wafer cap bonded to the silicon handle, wherein a combination of the silicon handle, the silicon wafer cap and the second planar portion define a second acoustic gap.

18. The acoustic resonator of claim 17 wherein the trap-rich layer is selected from the group consisting of amorphous silicon and polycrystalline silicon.

19. The acoustic resonator of claim 18 wherein the trap-rich layer has a thickness of from 500 nanometers (nm) and 800 nm.

20. The acoustic resonator of claim 19 wherein a silicon dioxide insulating layer is interposed between the trap-rich layer and both the first electrode and the second electrode.

21. A method for the manufacture of an organic based wafer level package, comprising the steps of: providing an acoustic resonator having a first electrode with a first planar portion, a second electrode with a second planar portion disposed parallel to the first planar portion, a piezoelectric layer disposed between and contacting both the first planar portion and the second planar portion and a support layer bonded to the second electrode, the support layer having a trap-rich layer that degrades a carrier lifetimes of a free charge carrier; and encapsulating the one or more acoustic resonators in an organic wafer level package.

22. The method of claim 21 wherein the encapsulating step includes: bonding an organic wall to the acoustic resonator; bonding an organic roof to the organic wall such that a combination of the organic wall and the organic roof define a first acoustic gap adjacent the second electrode; bonding a silicon handle to the acoustic resonator; and bonding a silicon wafer cap to the silicon handle such that a combination of the silicon handle and the silicon wafer cap define a second acoustic gap adjacent the first electrode.

23. The method of claim 22 including extending a first electrically conductive via through both the organic wall and the organic roof to electrically interconnect the second electrode to external devices and circuitry and extending a second electrically conductive via through both the organic wall and the organic roof to electrically interconnect the first electrode to external devices and circuitry.

24. The method of claim 23 including selecting the first substrate to be a silicon handle wafer and the trap-rich layer is selected to be either amorphous silicon on polycrystalline silicon.

25. The method of claim 24 wherein the silicon handle wafer is selected to have a resistivity exceeding 3000 ohm*cm.

26. The method of claim 25 wherein the trap-rich layer is deposited to a thickness of between 500 nm and 800 nm.

27. The method of claim 26 wherein oxidizing of the trap-rich layer includes partially oxidizing the surface of the trap region by one or more of thermal oxidation, mechanical polishing and thermal stress releasing to thereby form a silicon oxide insulating layer.

28. The method of claim 23 wherein step (d)—bonding further includes: supporting the piezoelectric layer and the first electrode on a second substrate with the piezoelectric layer adjacent the second support and an opposing second side of the first electrode adjacent the piezoelectric layer; depositing a second bonding layer on the first side of the first electrode; and fusing the first bonding layer to the second bonding layer.

29. The method of claim 28 including selecting the first bonding layer and the second bonding layer to be gold or a gold—indium alloy.

30. The method of claim 29 wherein the first bonding layer and the second bonding layer are deposited by a technique selected from group of e-beam evaporation coating, sputtering and molecular beam epitaxy.

31. The method of claim 30 including depositing an adhesion layer between one or both of the first bonding layer and the first electrode and the second bonding layer and the oxidized surface of the trap-rich layer.

32. The method of claim 31 including selecting the adhesion layer to be titanium or a titanium-tungsten alloy.

33. The method of claim 30 including selecting the second substrate to be sapphire.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 illustrates an FBAR filter with parasitic surface conduction as known from the prior art.

[0010] FIG. 2 illustrates an FBAR filter with a trap-rich layer to avoid parasitic surface conduction.

[0011] FIG. 3 is a flow chart representation of the process steps to manufacture an FBAR filter with a trap-rich layer.

[0012] FIG. 4 is a cross-sectional representation of a high resistivity silicon substrate, also referred to as a handle wafer.

[0013] FIG. 5 is a cross-sectional representation of a trap-rich layer deposited on the handle wafer.

[0014] FIG. 6 is a cross sectional representation illustrating a buried oxide layer formed in a surface of the trap-rich layer.

[0015] FIG. 7 is a cross sectional representation illustrating a gold bonding layer formed on a surface of the buried oxide layer.

[0016] FIG. 8 illustrates in cross sectional representation an active stack bonded to the handle wafer.

[0017] FIG. 9 shows the FBAR filter during an interim assembly step where a sapphire support layer has been removed.

[0018] FIG. 10 illustrates the interim assembly step following removal of a gallium nitride layer.

[0019] FIG. 11 illustrates trimming a piezoelectric layer to achieve desired filter properties.

[0020] FIG. 12 illustrates back end of the line (BEOL) processing to provide electrical interconnection to the piezoelectric layer.

[0021] FIG. 13 illustrates BEOL processing to provide an acoustic gap below the piezoelectric layer.

[0022] FIG. 14 illustrates further BEOL processing to remove remaining passivation layer and gold bonding layer from the acoustic gap.

[0023] FIG. 15 illustrates cap bonding to seal the acoustic gap.

[0024] FIG. 16 is a photomicrograph showing the surface roughness of the buried oxide layer when the trap-rich layer is amorphous silicon.

[0025] FIG. 17 is a photomicrograph showing the surface roughness of the buried oxide layer when the trap-rich layer is polycrystalline silicon.

[0026] FIG. 18 illustrates an organic based wafer level package encapsulating the FBAR filter.

DETAILED DESCRIPTION

[0027] FIG. 1 illustrates an FBAR filter 100 known from the prior art. This prior art FBAR filter 100 is at risk for parasitic surface conduction. In this FBAR filter 100, a high resistivity silicon forms a substrate layer 101. An inversion or accumulation region 110 develops because charge carriers are affected by the signal voltage in an active resonator structure 103. An inversion region is a conducting channel 104 that connects two n-type regions at a source and a drain allowing a free flow of electron charges. An accumulation region blocks the flow of electron charges through the conducting channel such that they accumulate on a surface adjacent the channel 104. The degree to which charge carriers in the region 110 are displaced is directly altered by signals in the active structure 103. As a result, the capacitance of an SiO.sub.2 buried oxide (BOX) layer 102 between the substrate layer 101 and the active resonator structure 103 depends on the electric field emanating from the active resonator structure 103.

[0028] This capacitance results in nonlinearity and added insertion losses of the FBAR filter 100 and a concomitant loss of signal purity. In addition, an electric field can invert this interface on the side of the substrate layer 101 creating the conducting channel 104 within the region 110 where charges can move easily in a lateral direction, L, despite the substrate layer 101 being highly resistive. This effect can then lead to signal-degrading cross talk in RF communication circuits and the Q factor of the FBAR filter 100 will be degraded.

[0029] FIG. 2 illustrates an FBAR filter 120 with a trap-rich layer to avoid parasitic surface conduction. A high resistivity silicon substrate has a resistivity in excess of 3000 ohm*cm. To prevent the charging side effect between the high resistivity silicon substrate 101 and the SiO.sub.2 buried oxide (BOX) layer 102, a trap-rich layer 112, such as amorphous silicon (a-Si) or polycrystal silicon (poly-Si), is formed within the region 110. This trap-rich layer 112 has a thickness of between 500 nanometers (nm) and 800 nm. The trap-rich layer 112 freezes the access of charge carriers attracted at the Si surface 114. The parasitic surface conduction is effectively combated because the trap-rich layer significantly degrades the carrier lifetimes of free charge carriers in the region 110. Since the charge carriers cannot travel far before being trapped, the effective resistivity of the substrate 101 is preserved and the capacitance is not as dependent upon the signals in the active resonator structure 103. Thus, the Quality Factor (Q) of FBAR filter 120 is improved.

[0030] FIG. 3 is a flow chart representation of one embodiment of process steps to manufacture an FBAR filter with a trap-rich layer. As shown in FIG. 4, a first process step is preparation of the high resistivity silicon substrate 101, also referred to as a handle wafer. The substrate is a silicon wafer with an exemplary diameter of 150 millimeters+/−0.2 mm and a thickness of 1000 micrometers+/−15 μm. The silicon may be doped to be either P or N type with a crystal orientation of <1-0-0>+/−0.05°. The direction along with orientation is <1-1-0>. Other exemplary properties are a resistivity in excess of 5000 ohm-centimeter, a total thickness variation of less than 5 μm, a warp of less than 50 μm and a bow of less than 50 μm.

[0031] Referencing FIGS. 3 and 5, a trap-rich layer 112 is deposited on the handle wafer 101. The trap-rich layer 112 may be amorphous silicon or polycrystalline silicon deposited by a process such as low pressure chemical vapor deposition (LPCVD) such that the compressive stress of the deposited layer is between −200 megapascal and −400 MPa. An exemplary thickness for the trap-rich layer is 650 nanometers +/−50 nm.

[0032] Referencing FIGS. 3 and 6, the buried oxide SiO.sub.2 layer 102 is formed in a surface 116 of the trap-rich layer 112. The oxide is formed to a thickness of 400 nanometers+/−40 nanometers such that the unoxidized portion of the trap-rich layer is 330 nm+/−30 nm. As the photomicrographs at FIGS. 16 and 17 illustrate, the surface roughness of the oxide (Ra) when the trap-rich layer is amorphous silicon is less than 2.8 nm as measured by atomic force measurement of a surface area of 10 μm by 10 μm. The surface roughness of the oxide (Ra) when the trap-rich layer is polycrystalline silicon is less than 9.0 nm as measured by atomic force measurement of a surface area of 10 μm by 10 μm. Both photomicrographs are at a magnification of 20,000 times.

[0033] Referencing FIGS. 3 and 7, a gold bonding layer 118(b) is formed on a surface 124 of the buried oxide SiO.sub.2 layer 102. Typically, the gold bonding layer has a thickness of between 50 nanometers (nm) and 500 nm and is deposited by a physical vapor deposition (PVD) process such as e-beam evaporation or sputtering. To enhance adhesion of the gold bonding layer 118(b), a thin adhesion layer, such as titanium for example, with a nominal thickness ranging from 10 nm to 50 nm may be deposited on the surface 124 prior to deposition of the gold bonding layer 118(b).

[0034] Referring back to FIG. 3, in parallel with the silicon handle assembly, an active stack 126 is formed. The active stack 126 includes a sapphire layer wafer with a gallium nitride layer deposited on the wafer. A piezoelectric layer, such as aluminum nitride or scandium doped aluminum nitride, is deposited on the GaN layer. To provide electrical conductivity to the piezoelectric layer and to enhance bonding to the silicon handle assembly, an electrically conductive layer is formed 136 on the piezoelectric layer.

[0035] A gold bonding layer 118(a) is formed on a surface of the electrically conductive layer 136. Typically, the gold bonding layer has a thickness of between 50 nm and 500 nm and is deposited by a PVD process such as e-beam evaporation or sputtering. To enhance adhesion of the gold bonding layer 118(a), a thin adhesion layer, such as a titanium layer, with a nominal thickness ranging from 10 nm to 50 nm may be deposited on the surface of electrically conductive layer 136 prior to deposition of the gold bonding layer 118(a). The gold bonding layer 118(a) on the wafer stack 126 on sapphire support substrate 130 is then bonded to the gold layer 118(b) of the wafer handle stack 128.

[0036] FIG. 8 illustrates in cross sectional representation the active stack 126 bonded to a handle wafer assembly 128. Sapphire support layer 130 supports GaN layer 132 that supports a piezoelectric layer 134. Typically, the piezoelectric layer is formed from single crystal aluminum nitride or single crystal scandium doped aluminum nitride having an exemplary thickness of from 200 nm to 1,000 nm. An electrically conductive layer 136, typically molybdenum, is bonded to the piezoelectric layer 134. The electrically conductive layer 136 may be formed from other metals, such as tungsten or ruthenium. Alloys that are predominantly (by weight) one of molybdenum, tungsten and ruthenium may also be utilized.

[0037] Referring back to FIG. 3, after the active stack 126 is bonded to the wafer handle assembly 128, the sapphire support layer 130 is removed as described in flow step 140. De-attaching of the sapphire support layer is by a process such as laser lift-off or grinding and resulting in the structure shown in FIG. 9.

[0038] Referencing FIGS. 3 and 10, the gallium nitride layer is removed as in flow step 142, such as by inductively coupled plasma (ICP) presenting a clean surface 144 of piezoelectric layer 134. Referencing FIGS. 3 and 11, the piezoelectric layer 134 is then trimmed to a length, width and thickness that provides desired filter properties. Generally, the tolerance in each dimension is on the order of +/−3 nm.

[0039] FIGS. 3 and 12-14 illustrate BEOL processing 148. FIG. 12 illustrate BEOL processing to provide electrical interconnection to the trimmed piezoelectric layer 134. A passivation layer 156, is deposited on select portions of the top surface of the wafer handle stack 128 and sides and select portions of the top of the piezoelectric layer 134 in preparation for deposition of second electrode material 150. The passivation layer is 156 is preferably an SiO.sub.2 layer selectively deposited over most surfaces except a central portion 158 of the piezoelectric layer 134. To minimize damage to surfaces of the piezoelectric layer 134, the SiO.sub.2 layer 156 is applied by a low temperature plasma deposition process to an exemplary thickness of 2.5 micrometers+/−0.1 micrometer. The stress applied to the surface is preferably less than 50 MPa (Megapascals). Utilizing low temperature plasma deposition also eliminates photoresist/polymer residue contamination of the surfaces.

[0040] The second electrode material 150 is typically molybdenum, although other metals such as tungsten or ruthenium may also be utilized. Alloys that are predominantly (by weight) one of molybdenum, tungsten and ruthenium may also be utilized. An exemplary thickness for the second electrode material is 200 nm. The second electrode material is deposited by a process such as low temperature (150° C.) sputtering or other PVD process for a high quality deposit characterized by a high density, low stress (less than 100 MPa) and a sheet resistance of Rs=below 0.5+/−0.05 ohm/square.

[0041] A portion of the passivation layer 156 is etched so that a portion of the first electrode material 136 is exposed enabling contact with the second electrode material 150 in a contact region 154 that is electrically isolated from the top surface 152 of the piezoelectric layer 134, thereby providing electrical interconnection to a bottom surface 160 of the piezoelectric layer. A gold bonding layer 161 will provide electrical interconnection to external devices.

[0042] FIG. 13 illustrates back end of the line processing to provide an acoustic gap 162 below the piezoelectric layer 134. A top surface sacrificial layer 164 is typically regular quality, not piezoelectric, aluminum nitride and deposited to a thickness of 100 nm+/−10 nm. A temporary silicon handle 166 is bonded to the top surface sacrificial layer 164 and provides rigidity. This rigidity enables a deep silicon etch (DSE) of about 4000 angstroms through the high resistance silicon substrate 101 and the trap-rich layer 112.

[0043] FIG. 14 illustrates further BEOL processing that remove remaining passivation layer 102 and gold bonding layer 118(b) from the acoustic gap 162. A chemical etch, such as diluted hydrofluoric acid (HF), removes remaining passivation layer 102 while a solution such as KI/I2 removes the gold bonding layer 118(a) from beneath the central portion 158.

[0044] Referencing FIGS. 3 and 15, cap bonding 168 process seals the acoustic gap 162. A silicon cap 170 is bonded to the silicon handle such as with an organic adhesive 172. The rigidity provided by the silicon cap 170 enable removal of the top surface sacrificial layer and temporary silicon handle (reference numerals 164, 166 in FIG. 13).

[0045] The acoustic resonator is typically packaged to provide electrical interconnection to external devices or circuit boards and to provide environmental protection. One suitable package is formed from polymer resin as described in United States Patent Application Publication No. US 2021/0028766 A1, titled “Packages with Organic Back Ends for Electronic Components,” by Hurwitz et al. The disclosure of US 2021/0028766 A1 is incorporated by reference herein in its entirety.

[0046] FIG. 18 illustrates an organic based wafer level package 80 encapsulating a piezoelectric layer 20 that maybe a component of an FBAR filter. An organic wall 82, formed from a polymer such as a photosensitive material for permanent structure formation, contains vias coated with an under bump metallization 84 (UBM) formed from an electrically conductive material such as nickel or copper. The UBM 84 provides an electrical interconnection to the first and second electrode layers of the FBAR filter. An organic roof layer 86 has an expanded via coated with a continuation of the UBM 84. Solder bump 88, such as a tin/silver alloy, fills the remainder of the via and extends beyond a surface 90 of the organic roof layer 86 for attachment and electrical interconnection to a device or a circuit board.