Abstract
A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.
Claims
1. An integrated circuit transistor device, comprising: a semiconductor substrate including: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer, said first epitaxial layer having a first thickness and doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer, said second epitaxial layer having a second thickness and doped with the first type dopant to provide a second resistivity; and a third epitaxial layer on the second epitaxial layer, said third epitaxial layer having a third thickness and doped with the first type dopant to provide a third resistivity; wherein the third resistivity is higher than the second resistivity; wherein the second resistivity is higher than the first resistivity; a first doped region buried in the third epitaxial layer of the semiconductor substrate providing a transistor body; a second doped region in the semiconductor substrate providing a transistor source, wherein the second doped region is adjacent the first doped region; a trench extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer; a transistor polysource region within the trench, said transistor polysource region insulated from the semiconductor substrate by a first insulating layer; and a transistor polygate region within the trench, said transistor polygate region insulated from the semiconductor substrate by a second insulating layer.
2. The integrated circuit transistor device of claim 1, wherein the transistor polygate region comprises: a polyoxide region over the transistor polysource region; a first gate lobe on a first side of the polyoxide region; and a second gate lobe on a second side of the polyoxide region opposite said first side.
3. The integrated circuit transistor device of claim 1, wherein the second epitaxial layer has a second dopant concentration, wherein the third epitaxial layer has a third dopant concentration, and wherein the second dopant concentration is greater than the third dopant concentration.
4. The integrated circuit transistor device of claim 3, wherein the third dopant concentration has a gradient increasing as a function of depth in the third epitaxial layer.
5. The integrated circuit transistor device of claim 3, wherein the second dopant concentration is substantially constant as a function of depth in the second epitaxial layer.
6. The integrated circuit transistor device of claim 1, wherein the first epitaxial layer has a first dopant concentration, wherein the second epitaxial layer has a second dopant concentration, and wherein the third dopant concentration is greater than the second dopant concentration.
7. The integrated circuit transistor device of claim 6, wherein the first dopant concentration has a gradient increasing as a function of depth in the first epitaxial layer.
8. The integrated circuit transistor device of claim 6, wherein the second dopant concentration is substantially constant as a function of depth in the second epitaxial layer.
9. The integrated circuit transistor device of claim 1, wherein the second epitaxial layer has a second dopant concentration configured to control a substantially constant electric field level as a function of depth in the second epitaxial layer.
10. The integrated circuit transistor device of claim 1, wherein the third epitaxial layer has a third dopant concentration configured to control a maximum electric field level in the third epitaxial layer.
11. The integrated circuit transistor device of claim 1, further comprising a source-body contact to the first and second doped regions, wherein said maximum electric field is under the source-body contact.
12. A method of fabricating a semiconductor substrate including a base substrate layer surmounted by at least three epitaxial layers, comprising: in an epitaxial tool: controlling a dopant setting at a constant level; and with the constant level for the dopant setting, performing three consecutive epitaxial growth processes, wherein a different dilute level is set for each epitaxial growth process, to: form a first epitaxial layer on the base substrate layer, said first epitaxial layer having a first resistivity controlled by a corresponding first dilute level; form a second epitaxial layer on the first epitaxial layer, said second epitaxial layer having a second resistivity controlled by a corresponding second dilute level; and form a third epitaxial layer on the second epitaxial layer, said third epitaxial layer having a third resistivity controlled by a corresponding third dilute level.
13. The method of claim 12, wherein third resistivity is higher than the second resistivity, and wherein the second resistivity is higher than the first resistivity.
14. The method of claim 12, wherein the second epitaxial layer has a second dopant concentration, wherein the third epitaxial layer has a third dopant concentration, and wherein the second dopant concentration is greater than the third dopant concentration.
15. The method of claim 14, wherein the third dopant concentration has a gradient increasing as a function of depth in the third epitaxial layer.
16. The method of claim 14, wherein the second dopant concentration is substantially constant as a function of depth in the second epitaxial layer.
17. The method of claim 12, wherein the first epitaxial layer has a first dopant concentration, wherein the second epitaxial layer has a second dopant concentration, and wherein the third dopant concentration is greater than the second dopant concentration.
18. The method of claim 17, wherein the first dopant concentration has a gradient increasing as a function of depth in the first epitaxial layer.
19. The method of claim 17, wherein the second dopant concentration is substantially constant as a function of depth in the second epitaxial layer.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
[0016] FIG. 1 is a cross-section of a power metal oxide semiconductor field effect transistor (MOSFET) device;
[0017] FIGS. 2A-2C show process steps in the manufacture of the power MOSFET device of FIG. 1;
[0018] FIG. 3A illustrates a first embodiment for the substrate used in the power MOSFET device of FIG. 1;
[0019] FIG. 3B is a graph illustrating the doping profile for the n-type dopant of the substrate shown in FIG. 3A;
[0020] FIG. 3C is a cross-section of the power MOSFET device as shown in FIG. 1 using the first embodiment for the substrate shown in FIG. 3A;
[0021] FIG. 3D is a graph illustrating the electrical field in the substrate for the power MOSFET device of FIG. 3C;
[0022] FIG. 4A illustrates a second embodiment for the substrate used in the power MOSFET device of FIG. 1;
[0023] FIG. 4B is a graph illustrating the doping profile for the n-type dopant of the substrate shown in FIG. 4A;
[0024] FIG. 4C is a cross-section of the power MOSFET device as shown in FIG. 1 using the second embodiment for the substrate shown in FIG. 4A;
[0025] FIG. 4D is a graph illustrating the electrical field in the substrate for the power MOSFET device of FIG. 4C;
[0026] FIG. 5A illustrates a comparison of static performance of the power MOSFET devices of FIGS. 3C and 4C in terms of BVDSS breakdown;
[0027] FIG. 5B illustrates a comparison of static performance of the power MOSFET devices of FIGS. 3C and 4C in terms of Rdson; and
[0028] FIGS. 6A, 6B and 6C illustrate parameters and results for the epitaxial growth process to fabricate the second embodiment of the substrate shown in FIG. 4A.
DETAILED DESCRIPTION
[0029] For the discussion herein, it will be noted that the term “longitudinal” refers to a first direction for example extending along the length of the trench and the term “lateral” refers to a second direction for example extending along the width of the trench. The longitudinal and lateral directions are perpendicular to each other and extend parallel to an upper surface of the semiconductor substrate.
[0030] Reference and use herein of “substantially equal to” or “about” or similar terminology thereto in terms of a given quantity means a range around the given quantity plus/minus 5% (for example, “substantially equal to” or “about” 10 means a range of 9.5 to 10.5).
[0031] Reference is now made to FIG. 3A which illustrates a first embodiment for the substrate 52 used in the power MOSFET device 50 of FIG. 1. The substrate 52 with a back side 56 includes a base substrate layer 52a. A first epitaxial layer 52b overlies the base substrate layer 52a at interface 100. A second epitaxial layer 52c overlies the first epitaxial layer 52b at interface 102. FIG. 3A further shows: the body region 64 within the second epitaxial layer 52c that is doped with a p-type dopant and buried in the substrate 52 at a depth offset from (i.e., below) the front side 54 and the source region 66 doped with an n-type dopant that is provided at the front side 54 of the substrate 52 adjacent the body region 64.
[0032] FIG. 3B is a graph illustrating the doping profile for the n-type dopant for the base substrate layer 52a, first epitaxial layer 52b and second epitaxial layer 52c. The base substrate layer 52a is heavily doped with an n-type dopant (for example, with a generally constant doping concentration in excess of about 1×10.sup.19 at/cm.sup.3). The first epitaxial layer 52b is also doped with an n-type dopant (for example, with a lower doping concentration between about 5×10.sup.16 at/cm.sup.3 and about 1×10.sup.19 at/cm.sup.3). In a preferred implementation, the first epitaxial layer 52b exhibits a doping gradient where the doping concentration increases as a function of depth (i.e., increasing in concentration the closer to the interface 100 with the base substrate layer 52a). The second epitaxial layer 52c is also doped with an n-type dopant (for example, with a light doping concentration that is less than or equal to about 5×10.sup.16 at/cm). In a preferred implementation, the second epitaxial layer 52b exhibits a generally constant doping concentration as a function of depth from the interface 104 with the body region 64 to interface 102 with the first epitaxial layer 52b.
[0033] As an example, base substrate layer 52a may have a thickness in the range of about 1-2 μm, first epitaxial layer 52b may have a thickness in the range of about 2.5-4 μm, and second epitaxial layer 52c may have a thickness in the range of about 6-8 μm. It will, of course, be understood that the foregoing thicknesses are provided as examples only, and the circuit designer may choose the appropriate layer thicknesses based on the circuit application.
[0034] Reference is now made to FIG. 3C illustrating a cross-section of a single cell of the power MOSFET device 50 as shown in FIG. 1 using the first embodiment for the substrate 52 shown in FIG. 3A. The first epitaxial layer 52b interfaces with the base substrate layer 52a and is a lower layer of low resistivity (for example, about 0.11 ohm*cm) due to the gradient doping concentration. The second epitaxial layer 52c forms the entire drift region of the MOSFET device 50 and is an upper layer of higher resistivity (for example, about 0.36 ohm*cm) and greater thickness (about 6.75 μm versus about 3.0 μm) than the first epitaxial layer 52b.
[0035] FIG. 3D shows a graph illustrating the electrical field in the substrate 52 for the power MOSFET device of FIG. 3C at the cut line 130 (which bisects the source-body contact 80) in connection with a simulation of device operation at the voltage at which the reverse-biased body-drift diode breaks down (i.e., the BVDSS breakdown condition). There are two peaks 134 in the electric field: one under the body-source contact 80 and another at the bottom of the trench 58. The highest electric field is under the body-source contact 80 associated with the first peak 134. There is a trough 136 in the electric field between the two peaks 134 in the second epitaxial layer 52c drift region. This shape of the electric field is not optimized (for example, it does not have a trapezoidal profile exhibiting a substantially constant electric field over the depth of the trench and in particular along the depth of the polysource 62a) and this has an adverse effect on power conduction loss (drain-to-source resistance in the on state (Rdson)) for the power MOSFET device of FIG. 3C.
[0036] Reference is now made to FIG. 4A which illustrates a second embodiment for the substrate 52 used in the power MOSFET device 50 of FIG. 1. The substrate 52 has a back face 56 and includes a base substrate layer 52a. A first epitaxial layer 52b overlies the base substrate layer 52a at interface 110. A second epitaxial layer 52c overlies the first epitaxial layer 52b at interface 112. A third epitaxial layer 52d overlies the first epitaxial layer 52b at interface 114. FIG. 4A further shows: the body region 64 within the third epitaxial layer 52d that is doped with a p-type dopant and buried in the substrate 52 at a depth offset from (i.e., below) the front side 54 and the source region 66 doped with an n-type dopant that is provided at the front side 54 of the substrate 52 adjacent the body region 64.
[0037] FIG. 4B is a graph illustrating the doping profile for the n-type dopant for the base substrate layer 52a, first epitaxial layer 52b, second epitaxial layer 52c and third epitaxial layer 52d. FIG. 4B also shows in a dash-dot line, for comparison purposes, the doping profile for the dual epi substrate configuration as shown in FIG. 3B. The base substrate layer 52a is heavily doped with an n-type dopant (for example, with a generally constant doping concentration in excess of about 1×10.sup.19 at/cm.sup.3). The first epitaxial layer 52b is also doped with an n-type dopant (for example, with a lower doping concentration between about 5×10.sup.16 at/cm.sup.3 and about 1×10.sup.19 at/cm.sup.3). In a preferred implementation, the first epitaxial layer 52b exhibits a doping gradient where the doping concentration increases as a function of depth (i.e., increasing in concentration the closer to the interface 110 with the base substrate layer 52a). In particular, the gradient of the doping concentration in a first part 120 of the first epitaxial layer 52b is generally constant followed by a second part 122 where the doping concentration gradually increases. The second epitaxial layer 52c is also doped with an n-type dopant (for example, with a light doping concentration that is less than about 1×10.sup.17 at/cm). In a preferred implementation, the second epitaxial layer 52c exhibits a generally constant doping concentration as a function of depth between interface 114 and interface 112. The third epitaxial layer 52d is also doped with an n-type dopant (for example, with a light doping concentration that is less than or equal to about 5×10.sup.16 at/cm). In a preferred implementation, the third epitaxial layer 52d exhibits a doping gradient where the doping concentration increases as a function of depth from the interface 116 with the body region 64 to interface 114. In particular, the gradient of the doping concentration in a first part 121 of the third epitaxial layer 52d exhibits a hump with a drop off that is followed by a second part 123 where the doping concentration gradually increases.
[0038] As an example, base substrate layer 52a may have a thickness in the range of about 1-2 μm, first epitaxial layer 52b may have a thickness in the range of about 2.5-4 μm, second epitaxial layer 52c may have a thickness in the range of about 3.5-6 μm, and the third epitaxial layer 52d may have a thickness in the range of about 2-4 μm. It will, of course, be understood that the foregoing thicknesses are provided as examples only, and the circuit designer may choose the appropriate layer thicknesses based on the circuit application.
[0039] Reference is now made to FIG. 4C illustrating a cross-section of the power MOSFET device 50 as shown in FIG. 1 using the second embodiment for the substrate 52 shown in FIG. 4A. The first epitaxial layer 52b interfaces with the base substrate layer 52a and is a lower layer of low resistivity (for example, about 0.12 ohm*cm) due to the gradient doping concentration. The drift region is formed by the second and third epitaxial layers 52c and 52d. The second epitaxial layer 52c is an intermediate layer of slightly higher resistivity (for example, about 0.19 ohm*cm) and greater thickness (about 4.1 μm versus about 3.0 μm) than the first epitaxial layer 52b. The second epitaxial layer 52c is responsible for elevating the electric field in the drift region to provide for a generally trapezoidal field shape. The third epitaxial layer 52d is an upper layer of higher resistivity (for example, about 0.52 ohm*cm) and less thickness (about 3.3 μm versus about 4.1 μm) than the second epitaxial layer 52c. The thickness and dopant concentration (see FIG. 4B) in the third epitaxial layer 52d are crucial in limiting the peak electric field beneath the source-body contact 80.
[0040] FIG. 4D shows a graph illustrating the electrical field in the substrate 52 for the power MOSFET device of FIG. 4C at the cut line 130 (which bisects the source-body contact 80) in connection with a simulation of device operation at the voltage at which the reverse-biased body-drift diode breaks down (i.e., the BVDSS breakdown condition). FIG. 4D also shows in a dash-dot line, for comparison purposes, the electric field for the dual epi substrate configuration as shown in FIG. 3D. The peak 134 in the electric field under the body-source contact 80 for the multiple epi substrate configuration of FIG. 4A is present and has a similar magnitude to the peak 134 for the dual epi substrate configuration. The positive effect of the second epitaxial layer 52c in elevating the electric field in the drift region to present a more trapezoidal profile 138 along the depth of the trench and its polysource 62a is clear (compare to the profile with trough 136). There is accordingly an improved performance in terms of power conduction loss (drain-to-source resistance in the on state (Rdson)).
[0041] The use of the multiple epi substrate configuration of FIG. 4A for a power MOSFET device like that shown in FIGS. 1 and 4C provides for improved static performance in terms of both of BVDSS breakdown and Rdson. See, FIG. 5A (illustrating a comparison of BVDSS breakdown static performance of the power MOSFET devices of FIGS. 3C and 4C at 250 μA with a more than 6% improvement in BVDSS when using the multiple epi substrate compared to the dual epi substrate) and FIG. 5B (illustrating a comparison of Rdson static performance of the power MOSFET devices of FIGS. 3C and 4C at 10 V and 11 A with a more than 7% reduction in Rdson when using the multiple epi substrate compared to the dual epi substrate).
[0042] The formation of the multiple epi substrate of FIG. 4A utilizes a conventional epitaxial tool well known to those skilled in the art, however there are unique aspects of the process recipe to achieve the desired structure. The recipe for the epitaxial growth of three consecutive layers (52b, 52c, 52d) utilizes a same dopant setting for each layer. To obtain a different resistivity for each layer, the dilute flow is modulated. FIG. 6A illustrates setting of the dopant level for the epitaxial tool to remain constant during the epitaxial growth of the first, second and third epitaxial layers 52b, 52c and 52d (for example, at a level of between bout 150-200 sccm. FIG. 6B, however, illustrates modulation of the setting for the dilute level in the epitaxial tool for the deposition each epitaxial layer (the dilute having a first, lower, level (for example, at a level of between about 500-1000 sccm) when epitaxially growing the first epitaxial layer 52b, having a second, intermediate, level (for example, at a level of between about 1000-1500 sccm) when epitaxially growing the second epitaxial layer 52c, and having a third, higher, level (for example, at a level of between about 3000-4000 sccm) when epitaxially growing the third epitaxial layer 52d). The changing of the dilute level, while keeping the dopant level constant, results in each epitaxial layer 52b, 52c and 52d having a different resistivity as shown in FIG. 6C.
[0043] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.
