RF POWER AMPLIFIER WITH COMPENSATED CURRENT AND GAIN FROM TURN-ON TO END OF LONG BURST

Abstract

Radio frequency (RF) power amplifier architectures and circuits providing compensated current and gain from turn-on to end of long signal burst intervals to counteract amplifier transistor thermal rise due to self-heating at turn-on. The RF receiver circuit may be implemented as one of a single chip device or as part of an integrated system of components for use in mobile communication systems.

Claims

1. A radio frequency (RF) power amplifier architecture and circuits for adjusting amplifier output gain during a signal burst interval, comprising: an amplifier transistor controlling and providing gain to an output current flowing between a voltage supply coupled to the transistor's output terminal and ground; a first circuit comprising a mirror current circuit providing a bias voltage at a first terminal which is coupled through a resistor to the input terminal of the amplifier transistor; and a second circuit connected to the mirror current circuit at the first terminal providing a signal to modify the bias voltage following a turn-on portion of the signal burst interval, wherein the combined circuits reduce amplifier gain following the turn-on portion of the signal burst interval to compensate for an increase in amplifier gain due to thermal self-heating in the amplifier transistor following the turn-on event and thereby provide uniform gain throughout the signal burst interval.

2. The RF power amplifier architecture and circuits of claim 1, wherein the action of the second circuit causes the amplifier gain to slowly rise to a design target value over a time interval characterized by a time constant.

3. The RF power amplifier architecture and circuits of claim 1, wherein the second circuit comprises a resistor-capacitor network.

4. The RF power amplifier architecture and circuits of claim 2, wherein the second circuit comprises a resistor-capacitor network.

5. The RF power amplifier architecture and circuits of claim 1, wherein the second circuit comprises a capacitor with one electrode connected to the first terminal and a resistor connected between a second electrode of the capacitor and ground.

6. The RF power amplifier architecture and circuits of claim 1, wherein the second circuit comprises a resistor-capacitor network placed inside the mirror current circuit.

7. The RF power amplifier architecture and circuits of claim 1, additionally comprising a third circuit to turn off the amplifier circuit at the end of the burst signal interval.

8. The RF power amplifier architecture and circuits of claim 3, additionally comprising a third circuit to turn off the amplifier circuit at the end of the burst signal interval by providing a discharge capability to the resistor-capacitor network.

9. The RF power amplifier architecture and circuits of claim 1, wherein the second circuit comprises an operational amplifier and is placed inside the mirror current circuit.

10. The RF power amplifier architecture and circuits of claim 1, wherein the amplifier architecture and circuits is an integrated circuit.

11. The RF power amplifier architecture and circuits of claim 4, wherein the amplifier architecture and circuits is an integrated circuit and the capacitor in the resistor-capacitor network may be an external capacitor when the required capacitance value is too large to be integrated.

12. The RF power amplifier architecture and circuits of claim 5, additionally comprising a third circuit to turn off the amplifier circuit at the end of the burst signal interval by providing a discharge switch between the first terminal and ground.

13. The RF power amplifier architecture and circuits of claim 1, wherein the amplifier transistor is one of a bipolar transistor or a CMOS transistor.

14. The RF power amplifier architecture and circuits of claim 5, wherein the resistor-capacitor network comprises a resistor of 10k Ohms and a capacitor of 100 nF.

15. A radio frequency (RF) power amplifier architecture and circuits for adjusting amplifier output gain during a signal burst interval comprising: an MOS Cascode amplifier controlling and providing gain to an output current flowing between a voltage supply coupled to the common gate stage transistor output terminal through the common source amplifying transistor to ground; a first circuit comprising a mirror current circuit providing a bias voltage at a first terminal which is coupled through a resistor to the input terminal of the common source amplifying transistor; and a second circuit connected to the mirror current circuit at the first terminal providing a signal to modify the bias voltage following a turn-on portion of the signal burst interval, wherein the combined circuits reduce the Cascode amplifier gain following the turn-on portion of the signal burst interval to compensate for an increase in amplifier gain due to thermal self-heating in the amplifier transistor following the turn-on event and thereby provide uniform gain throughout the signal burst interval.

16. The RF power amplifier architecture and circuits of claim 15, wherein the second circuit comprises a capacitor with one electrode connected to the first terminal and a resistor connected between a second electrode of the capacitor and ground.

17. The RF power amplifier architecture and circuits of claim 15, additionally comprising a third circuit to turn off the amplifier circuit at the end of the burst signal interval by providing a switch between the gate electrode of the common gate stage transistor and ground.

18. The RF power amplifier architecture and circuits of claim 16, additionally comprising a third circuit to turn off the amplifier circuit at the end of the burst signal interval by providing a switch between the gate electrode of the common gate stage transistor and ground.

19. The RF power amplifier architecture and circuits of claim 1, wherein the combined circuits reduce amplifier gain following the turn-on portion of the signal burst to compensate for an increase in amplifier gain due to thermal heating in the amplifier transistor following the turn-on event and thereby provide uniform Error Vector Magnitude of the digital modulation throughout the signal burst interval.

20. A radio frequency (RF) power amplifier architecture and circuits for adjusting amplifier output gain during a signal burst interval, comprising: an amplifier transistor controlling and providing gain to an output current flowing between a voltage supply coupled to the transistor's output terminal and ground; and a first circuit comprising a mirror current circuit providing a bias voltage at a first terminal which is coupled through a resistor to the input terminal of the amplifier transistor; and a second circuit, comprising a resistor-capacitor network, connected between the mirror current circuit at the first terminal and ground providing a signal to modify the bias voltage following a turn-on portion of the signal burst interval; and a third circuit, comprising a switch to ground, to turn off the amplifier circuit at the end of the burst signal interval by providing a discharge capability to the resistor-capacitor network, wherein the combined circuits reduce amplifier gain following the turn-on portion of the signal burst interval to compensate for an increase in amplifier gain due to thermal self-heating in the amplifier transistor following the turn-on event and thereby provide uniform gain and uniform Error Vector Magnitude of the digital modulation throughout the signal burst interval.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings illustrate the present invention:

[0013] FIG. 1 is a diagram illustrating the circuit blocks found in a typical RF transceiver architecture;

[0014] FIG. 2 is an electrical schematic diagram illustrating a Regular Amplifier according to the prior art;

[0015] FIG. 3 is an illustration of the transient current and gain of a Regular Amplifier according to the prior art;

[0016] FIG. 4 is an electrical schematic diagram illustrating a Regular Amplifier according to an embodiment of the invention;

[0017] FIG. 5 is an illustration of the transient current and gain of a Regular Amplifier according to an embodiment of the invention;

[0018] FIG. 6 is an electrical schematic diagram illustrating a Regular Amplifier according to another embodiment of the invention; and

[0019] FIG. 7 is an electrical schematic diagram illustrating a Regular Amplifier according to another embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0020] Various embodiments of an RF amplifier architecture including transmitter power amplifier (PA) circuits having advantages not taught by the prior art are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0021] Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The terms “coupled” and “connected”, which are utilized herein, are defined as follows. The term “connected” is used to describe a direct connection between two circuit elements, for example, by way of a metal line formed in accordance with normal integrated circuit fabrication techniques. In contrast, the term “coupled” is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two coupled elements may be directly coupled by way of a metal line, or indirectly connected by way of an intervening circuit element (e.g., a capacitor, resistor, or by way of the source/drain terminals of a transistor). The term “circuit” means either a single component or a multiplicity of components, either active or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, or data signal. Although circuit elements may be fabricated on the back side, when reference is made to certain circuit elements residing within or formed in a substrate, this is generally accepted to mean the circuits reside on the front side of the substrate.

[0022] The above-described drawing figures illustrate the invention, an RF amplifier architecture providing constant gain and improved linearity during a signal burst interval in the face of amplifier temperature increase at the turn-on instant of the interval.

[0023] FIG. 1 is a diagram illustrating the circuit blocks found in a typical RF transceiver architecture or RF front end. With a Duplexer or switch in a receive mode an RF signal is received at an antenna and picked up by a low noise amplifier LNA and sent on to receiver components such as a filter, down-mixer, IF block, and modem. With the Duplexer or switch in transmit mode the antenna receives forward power Pf from a power amplifier PA through a filter and radiates power Prad into space. Also shown in FIG. 1 are a voltage-controlled oscillator VCO and an Up-Mixer and a Down-Mixer which are used to up convert and down convert an input RF frequency to an intermediate frequency IF.

[0024] FIG. 2 is an electrical schematic diagram illustrating an example of a Regular RF Amplifier according to the prior art. The illustrated amplifier example incorporates a Bipolar transistor Tb with voltage VO applied to its base. Voltage VO is derived from a bias voltage Vbias provided by a mirror current circuit M that is coupled through a resistor RO to the base electrode. RF amplifiers that include bipolar transistors can also include a current mirror bias circuit which is a circuit designed to copy a current through one active device by controlling the current through another active device, keeping the output current constant regardless of loading. A mirror current circuit M may be employed in various embodiments of the present invention and they may be any of those known to those skilled in the art. A supply voltage at Vcc powers the transistor, and a supply current Icc is one main characteristic of the circuit along with Gain and Power. A load resistance R.sub.load is typically 50 Ohms.

[0025] FIG. 3 is an illustration of the time dependent supply current Icc, Gain and Power characteristics of the prior art Regular RF Amplifier shown in FIG. 2. Along the horizontal axis is shown the time t with trace A illustrating a signal burst interval from its off-time turn-on event to the end of the burst interval. The transistor typically heats up beginning at the turn-on event and stabilizing near the end of the burst. FIG. 3 also illustrates the amplifier supply current Icc transient characteristic with trace B wherein the Icc quickly rises at the turn-on event well above the value it settles to by the end of the burst interval. This characteristic is primarily a result of the initial self-heating within the amplifier transistor at the turn-on event.

[0026] FIG. 3 additionally illustrates the amplifier Gain and Power transient characteristic with trace C wherein the Gain and Power quickly rise at the turn-on event well above the value they settle to by the end of the burst interval. This droop characteristic is primarily a result of the initial self-heating within the amplifier transistor during the signal burst interval that follows the turn-on event.

[0027] FIG. 4 is an electrical schematic diagram illustrating an example of a Regular RF Amplifier according to a first embodiment of the invention. The illustrated amplifier example incorporates a Bipolar transistor Tb with voltage V1 applied to its base electrode. Voltage V1 is derived in part from a bias voltage Vbias provided by a mirror current circuit M that is coupled through a resistor R1 to the base electrode. A supply voltage at Vcc powers the transistor, and a supply current Icc is one main characteristic of the circuit along with Gain and Power. A load resistance R.sub.load is typically 50 Ohms. The inventive elements include the addition of an RC circuit comprising capacitor C and resistor R which are connected between ground and to Vbias at a point prior to resistor R1 which functions to delay the application of the mirror current to the base electrode of transistor Tb. Due to the delay the current at the base electrode rises slowly to its final value with an electrical time constant given by the RC circuit. The electrical time constant must be matched to the rising thermal time constant of the amplifier transistor as it heats up during a turn-on event. As illustrated in FIG. 3 the Gain and Power of the prior art amplifier quickly rise at the turn-on event well above the value they settle to by the end of the burst. Given that the transistor circuit Gain, Power and Icc rise as the transistor heats up, the invented device design sets the gain at the instant of turn-on to be equal to the gain realized following the self-heating event when the thermal transient has normalized.

[0028] The invented amplifier circuit results in a relatively constant gain over the entire burst interval and thereby provides constant EVM of the digital modulation. The time constants of the RC circuit may be on the order of 1 millisecond. So, for example, R may be approximately 10k Ohms and C may be approximately 100 nF. An alternate amplifier circuit design that may reduce the required value of capacitor C is to use an active circuit such as an Operational

[0029] Amplifier with a RC time delay.

[0030] FIG. 4 also illustrates that, since the delay introduced by the RC circuit also applies to the turn-off time, a switch transistor SW may be connected between the connection point of capacitor C and resistor R1 and ground. Switch transistor SW is activated by Voff in order to discharge capacitor C at the end of the burst interval. Voff can be supplied by any point of the circuitry associated with turning off the amplifier's current. This invented amplifier circuit is realized at low cost with low utilization of associated space on an integrated circuit and once designed for a given amplifier application requires no calibration.

[0031] FIG. 5 is an illustration of the time dependent supply current Icc, Gain and Power characteristics of the invented Regular RF Amplifier shown in FIG. 4. The figure description is similar to that of FIG. 3. Along the horizontal axis is shown the time t with trace A illustrating a signal burst interval from its off-time turn-on event to the end of the burst. But unlike FIG. 3 the amplifier supply current Icc transient characteristic B1 begins slightly lower than its eventual stable value at time T1, which is the time required to reach stable current. Also unlike FIG. 3 the amplifier supply Gain and Power transient characteristic C1 will follow the supply current profile and may be slightly higher or lower at the beginning of the burst than its value at time T1, which is the time required to reach stable current and gain. The time duration from turn-on event to time Ti may usually be less than the time duration of the burst interval. Also, unlike the prior art illustrated in FIG. 3, the amplifier supply current and thus the gain slowly reaches the target value with a time constant determined by the values of resistor R and capacitor C.

[0032] FIG. 6 is an electrical schematic diagram illustrating an example of a Regular RF Amplifier according to a second embodiment of the invention. The illustrated amplifier example incorporates a Complementary Metal Oxide Semiconductor CMOS transistor Tc with voltage V2 applied to its gate electrode in place of the Bipolar transistor Tb illustrated in FIG. 4. Voltage V2 is derived in part from a bias voltage Vbias provided by a mirror current circuit

[0033] M that is coupled through a resistor R2 to the gate electrode. As with the first embodiment the inventive elements include the addition of an RC circuit comprising capacitor C and resistor R, which are connected between ground and Vbias at a point prior to resistor R2, which functions to delay the application of the mirror current to the gate electrode of transistor Tc. A supply voltage at Vdd powers the transistor, and a supply current Idd is one main characteristic of the circuit. A load resistance Rload is typically 50 Ohms. The performance characteristics related to the second embodiment of the invention are the same as those illustrated in FIG. 5 except that supply current Icc is replaced by supply current Idd. The detailed description is not repeated as it is obvious to those skilled in the art.

[0034] FIG. 6 also illustrates that, since the delay introduced by the RC circuit also applies to the turn-off time, a switch transistor SW may be connected between the connection point of capacitor C and resistor R2 and ground. Switch transistor SW is activated by Voff in order to discharge capacitor C at the end of the burst interval. Voff can be supplied by any point of the circuitry associated with turning off the amplifier's current. This invented amplifier circuit is realized at low cost with low utilization of associated space on an integrated circuit and once designed for a given amplifier application requires no further calibration.

[0035] FIG. 7 is an electrical schematic diagram illustrating an example of a Regular RF Amplifier according to a third embodiment of the invention. The illustrated amplifier example incorporates a CMOS Cascode amplifier with the output of transistor Td, the common source amplifying transistor, fed to the common gate stage transistor Te. Voltage V3 is applied to the gate electrode of transistor Td. Voltage V3 is derived in part from a bias voltage Vbias provided by a mirror current circuit M that is coupled through a resistor R3 to the gate electrode of transistor Td. Voltage Vcasc is applied to the gate electrode of transistor Te. As with the first embodiment the inventive elements include the addition of an RC circuit comprising capacitor C and resistor R which are connected between ground and Vbias at a point prior to resistor R3 which functions to delay the application of the mirror current to the gate electrode of transistor Tc. A supply voltage at Vdd powers the transistor, and a supply current Idd is one main characteristic of the circuit. A load resistance R.sub.load is typically 50 Ohms. The incorporation of the Cascode amplifier components provides high intrinsic gain, high output impedance and large bandwidth to applications benefiting from it. The performance characteristics related to the third embodiment of the invention are the same as those illustrated in FIG. 5 except that supply current Icc is replaced by supply current Idd. The detailed description is not repeated as it is obvious to those skilled in the art. Other embodiments of the present invention are obtained by adding further CMOS transistors on top of a cascode.

[0036] FIG. 7 also illustrates that, since the delay introduced by the RC circuit also applies to the turn-off time, a switch transistor SW may be connected between the gate electrode of transistor Te and ground. Switch transistor SW is activated by Voff in order to turn off transistor Te at the end of the burst interval. Voff can be supplied by any point of the circuitry associated with turning off the amplifier's current. This invented amplifier circuit is realized at low cost with low utilization of associated space on an integrated circuit and once designed for a given amplifier application requires no calibration.

[0037] Reference throughout this specification to “one embodiment,” “an embodiment,” “one example,” or “an example” means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. Thus, the appearances of the phrases such as “in one embodiment” or “in one example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments or examples. Directional terminology such as “top”, “down”, “above”, “below” are used with reference to the orientation of the figure(s) being described. Also, the terms “have,” “include,” “contain,” and similar terms are defined to mean “comprising” unless specifically stated otherwise. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

[0038] The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example structures and materials are provided for explanation purposes and that other structures and materials may also be employed in other embodiments and examples in accordance with the teachings of the present invention. These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.