FINITE IMPULSE RESPONSE INPUT DIGITAL-TO-ANALOG CONVERTER

Abstract

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

Claims

1. A digital-to-analog converter, comprising: an integrator; an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance; and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

2. The digital-to-analog converter of claim 1, wherein each member of the plurality of parallel taps includes a pair of differential tap elements.

3. The digital-to-analog converter of claim 2, wherein: a first tap element of each member of the plurality of parallel taps is coupled between a first polarity of a digital input signal to the digital-to-analog converter and an inverting input of the integrator; and a second member of each member of the plurality of parallel taps is coupled between a second polarity of a digital input signal to the digital-to-analog converter and a non-inverting input of the integrator; and

4. The digital-to-analog converter of claim 1, wherein each member of the plurality of parallel taps has a respective signal delay, such that at least two of the respective signal delays are different.

5. The digital-to-analog converter of claim 4, wherein the respective signal delay for each member of the plurality of parallel taps is different.

6. The digital-to-analog converter of claim 4, wherein the control circuitry is further configured to selectively enable and disable particular members of the plurality of parallel taps in order to control the analog gain of the digital-to-analog converter and to combine delay characteristics of enabled members of the plurality of parallel taps in order to generate desired filter characteristics for the input network.

7. The digital-to-analog converter of claim 4, wherein the control circuitry is further configured to, when selectively enabling and disabling a particular member of the plurality of parallel taps, delay a control signal for enabling or disabling the particular member based on the respective signal delay for the particular member.

8. The digital-to-analog converter of claim 1, the control circuitry further configured to selectively enable and disable an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

9. The digital-to-analog converter of claim 8, wherein the first group and the second group are separated temporally from each other in order to facilitate matching of an input signal received by the digital-to-analog converter and an output of a component downstream of the digital-to-analog converter.

10. The digital-to-analog converter of claim 8, wherein the control circuitry is further configured to, when enabling or disabling additional members of the plurality of parallel taps to modify the analog gain, alternate between tap delays that decrease a duration between a first center of the first group and a second center of the second group and tap delays that increase the duration.

11. The digital-to-analog converter of claim 10, wherein the control circuitry is further configured to maintain the first center at approximately 25% of a pulse width of an input signal received by the digital-to-analog converter and at approximately 75% of a pulse width of the input signal.

12. A method, comprising, in a digital-to-analog converter having an integrator and an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance: selectively enabling and selectively disabling particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

13. The method of claim 12, wherein each member of the plurality of parallel taps includes a pair of differential tap elements.

14. The method of claim 13, wherein: a first tap element of each member of the plurality of parallel taps is coupled between a first polarity of a digital input signal to the digital-to-analog converter and an inverting input of the integrator; and a second member of each member of the plurality of parallel taps is coupled between a second polarity of a digital input signal to the digital-to-analog converter and a non-inverting input of the integrator; and

15. The method of claim 12, wherein each member of the plurality of parallel taps has a respective signal delay, such that at least two of the respective signal delays are different.

16. The method of claim 15, wherein the respective signal delay for each member of the plurality of parallel taps is different.

17. The method of claim 15, further comprising selectively enabling and disabling particular members of the plurality of parallel taps in order to control the analog gain of the digital-to-analog converter and to combine delay characteristics of enabled members of the plurality of parallel taps in order to generate desired filter characteristics for the input network.

18. The method of claim 15, further comprising, when selectively enabling and disabling a particular member of the plurality of parallel taps, delaying a control signal for enabling or disabling the particular member based on the respective signal delay for the particular member.

19. The method of claim 12, further comprising selectively enabling and disabling an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

20. The method of claim 19, wherein the first group and the second group are separated temporally from each other in order to facilitate matching of an input signal received by the digital-to-analog converter and an output of a component downstream of the digital-to-analog converter.

21. The method of claim 19, further comprising, when selectively enabling and disabling additional members of the plurality of parallel taps to modify the analog gain, alternating between tap delays that decrease a duration between a first center of the first group and a second center of the second group and tap delays that increase the duration.

22. The method of claim 21, further comprising maintaining the first center at approximately 25% of a pulse width of an input signal received by the digital-to-analog converter and at approximately 75% of a pulse width of the input signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

[0013] FIG. 1 illustrates an example personal audio device, in accordance with embodiments of the present disclosure;

[0014] FIG. 2 illustrates a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with embodiments of the present disclosure;

[0015] FIG. 3 illustrates an example circuit diagram of selected components of a digital-to-analog converter, in accordance with embodiments of the present disclosure;

[0016] FIG. 4 illustrates an example of generation of analog gain by delaying and summing the various delayed PWM signals through each of parallel gain taps of a digital-to-analog converter, in accordance with embodiments of the present disclosure;

[0017] FIGS. 5A and 5B illustrate examples of a filter that may be implemented by enabling two pairs of parallel gain taps of a digital-to-analog converter, in accordance with embodiments of the present disclosure;

[0018] FIGS. 6A and 6B illustrate examples of a filter that may be implemented by enabling six pairs of parallel gain taps of a digital-to-analog converter, in accordance with embodiments of the present disclosure;

[0019] FIG. 7 illustrates an example graph depicting example tap delays used when two tap pairs are enabled, in accordance with embodiments of the present disclosure;

[0020] FIG. 8 illustrates an example graph depicting example tap delays used when four tap pairs are enabled, in accordance with embodiments of the present disclosure; and

[0021] FIG. 9 illustrates an example graph depicting example tap delays used when six tap pairs are enabled, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

[0022] FIG. 1 illustrates an example personal audio device 1, in accordance with embodiments of the present disclosure. FIG. 1 depicts personal audio device 1 coupled to a headset 3 in the form of a pair of earbud speakers 8A and 8B. Headset 3 depicted in FIG. 1 is merely an example, and it is understood that personal audio device 1 may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers. A plug 4 may provide for connection of headset 3 to an electrical terminal of personal audio device 1. Personal audio device 1 may provide a display to a user and receive user input using a touch screen 2, or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal audio device 1. As also shown in FIG. 1, personal audio device 1 may include an audio integrated circuit (IC) 9 for generating an analog audio signal for transmission to headset 3 and/or another audio transducer.

[0023] FIG. 2 illustrates a block diagram of selected components of an example audio IC 9 of a personal audio device, in accordance with embodiments of the present disclosure. As shown in FIG. 2, a microcontroller core 18 may supply a digital input signal DIG_IN to a digital gain element 12 which may apply a digital gain GAIN.sub.D to digital input signal DIG_IN in order to generate modified digital input signal DIG_IN′ to digital-to-analog converter (DAC) 14. DAC 14 may convert modified digital input signal DIG_IN′ to an analog differential output signal V.sub.OUT. In some embodiments, DAC 14 may be configured to apply an analog gain GAIN.sub.A to amplify or attenuate modified digital input signal DIG_IN′ to provide differential output signal VOUT, which may operate a speaker, a headphone transducer, a line level signal output, other transducer, and/or other suitable output. Thus, together digital gain GAIN.sub.D and analog gain GAIN.sub.A, either or both of which may be programmable, may apply a desired overall gain (e.g., GAIN.sub.D.Math.GAIN.sub.A) to digital input signal DIG_IN in order to generate differential output signal VOUT. A power supply 10 may provide the power supply rail inputs of DAC 14. As shown in FIG. 2, audio IC 9 may include control circuitry 20 configured to control digital gain GAIN.sub.D and analog gain GAIN.sub.A, as described in greater detail below.

[0024] Although FIGS. 1 and 2 contemplate that audio IC 9 resides in a personal audio device, systems and methods described herein may also be applied to electrical and electronic systems and devices other than a personal audio device, including audio systems for use in a computing device larger than a personal audio device, including without limitation an automobile, a building, or other structure. Further, a DAC such as DAC 14 may be used in other applications besides audio processing and generating audio signals, including without limitation generating analog signals for other transducers, including without limitation haptic transducers.

[0025] FIG. 3 illustrates an example circuit diagram of selected components of DAC 14, in accordance with embodiments of the present disclosure. As shown in FIG. 3, DAC 14 may receive a differential modified digital input signal DIG_IN′ having a positive polarity signal DIG_IN′.sup.(+) and a negative polarity signal DIG_IN′.sup.(−), such that DIG_IN′=DIG_IN′.sup.(+)−DIG_IN′.sup.(−). In some embodiments, each of positive polarity signal DIG_IN′.sup.(+) and negative polarity signal DIG_IN′.sup.(−) may comprise PWM signals. Further, DAC 14 may include a plurality of parallel taps arranged in pairs such that one input of each tap pair receives positive polarity signal DIG_IN′.sup.(+) and the other input of such tap pair receives negative polarity signal DIG_IN′.sup.(−). Each tap may include a delay element 30 that adds a signal delay of a defined duration, a buffer 32 for buffering the delayed signal, and an input resistor 34, with a terminal of each input resistor 34 of taps receiving positive polarity signal DIG_IN′.sup.(+) coupled together at an inverting input of an integrator 38 and a terminal of each input resistor 34 of taps receiving negative polarity signal DIG_IN′.sup.(−) coupled together at a non-inverting input of integrator 38. A feedback resistor 36 may be coupled between an inverting output of and a non-inverting input of integrator 38 and another feedback resistor 36 may be coupled between a non-inverting output of and an inverting input of integrator 38. As a result, integrator 38 may generate an analog integrator output signal VINT that may be further processed by other components of DAC 14 (not explicitly shown, but may include one or more loop filters, modulators, driving output stages, etc.) to generate analog output voltage V.sub.OUT.

[0026] As seen in FIG. 3, the serial string of resistors used in traditional approaches, as described in the Background section above, may be replaced with a parallel combination of gain taps, each gain tap including parallel fixed value input resistors 34. Although not explicitly shown in FIG. 3 for purposes of clarity and exposition, each gain tap may be selectively enabled or disabled (e.g., by control circuitry 20), such that input resistance, and accordingly analog gain of DAC 14, may be programmed by enabling between 1 and N parallel taps, wherein N is the number of taps available. For example, assuming each input resistor 34 has a resistance of R.sub.I (although in some embodiments, resistances of input resistors 34 may vary significantly) and feedback resistors 36 have a resistance of R.sub.F, an analog gain GAIN.sub.A in decibels for DAC 14 may be given by:

[00001]${\mathrm{GAIN}}_A=20\log \frac{n.Math.R_F}{R_I}$

where n represents the number of the N taps that are enabled. As a specific example, further assuming N=10 total taps and R.sub.F=R.sub.I, the relationship among the number of taps n which are enabled to GAIN.sub.A may be given by the table below:

TABLE-US-00001 Taps 1 2 3 4 5 6 7 8 9 10 Gain(dB) 0 6.02 9.54 12.04 13.98 15.56 16.90 18.06 19.08 20.00

[0027] Accordingly, a desired gain may be provided by tuning feedback resistors 36 and/or the combination of enabled parallel gain taps to result in an appropriate gain for a given application. If needed, gains may further be manipulated by tuning (e.g., by control circuitry 20) digital gain GAIN.sub.D as appropriate to achieve a desired overall gain. For example, if a gain of 10 dB were desired, four taps of DAC 14 may be enabled to provide analog GAIN.sub.A of 12.04 dB and digital gain GAIN.sub.D may be tuned to apply an attenuation of 2.04 dB to result in an overall path gain of 10 dB.

[0028] In addition to generating a desired analog gain by selectively enabling and disabling the various parallel taps of DAC 14, selectively enabling and disabling the various parallel taps of DAC 14, assuming delay elements 30 are of different duration between different pairs of taps, may in effect implement a hybrid analog/digital finite impulse response (FIR) filter with desired filter characteristics (e.g., desired filter nulls) by taking advantage of the summing nodes present at the inputs of integrator 38.

[0029] FIG. 4 illustrates an example of generation of analog gain GAIN.sub.A by delaying and summing the various delayed PWM signals through each of the taps of DAC 14, in accordance with embodiments of the present disclosure. FIG. 4 depicts a modified digital analog signal DIG_IN′ with delays of durations A, B, C, and D applied by delay elements 30 of different gain taps. FIG. 4 further shows the summation of two of the delayed signals and summation of all four of the delayed signals. As seen in FIG. 4, the group delay between the two summed PWM signals are the same, and the gain is increased by two for the sum of the four delayed signals as compared to the sum of two delayed signals.

[0030] Thus, as described above, both control of gain and filter characteristics of DAC 14 may be achieved by selectively enabling and disabling parallel gain taps of DAC 14. As an example, by enabling two pairs of taps, a filter represented in the time-domain by the impulse response function of FIG. 5A and with a frequency-domain representation represented by FIG. 5B may be implemented. As another example, by enabling six pairs of taps, a filter represented in the time-domain by the impulse response function of FIG. 6A and with a frequency-domain representation represented by FIG. 6B may be implemented.

[0031] In order to minimize signal artifacts (e.g., “pops” and “clicks” that may occur in audio applications) resulting from enabling and disabling of taps of DAC 14, control circuitry 20 for enabling and disabling taps of DAC 14 may be configured to enable and disable taps at points of time in which signal artifacts may be avoided. For example, assume a tap pair delays a data symbol by a period of time t. By delaying a control signal for enabling or disabling the tap pair by time t from the start of the symbol (which may always be zero), the tap pair may too be enabled or disabled when the data associated with such tap is also zero. In an alternative implementation, a tap pair may be enabled or disabled when its input data is “1” if desired. Thus, control circuitry 20 may be configured to sequence control signals for enabling and disabling each tap pair of DAC 14 based on a delay added to modified digital input signal DIG_IN″ by such tap pair, so as to enable only when both polarities of the delayed signal as delayed by delay elements 30 are zero or “1”, as desired.

[0032] Choices for the hybrid analog/digital FIR structure described above with respect to FIG. 3 may play a role in both filtering and matching of the input waveform and output of a multiple level output stage (or other component downstream of DAC 14), as well as minimize integrated crosstalk noise, integrator dynamic range, and total harmonic distortion noise.

[0033] In accordance with embodiments of the present disclosure, as control circuitry 20 increases the number of parallel gain taps to increase gain, control circuitry 20 may enable an even number of tap pairs at a time, with half of such enabled tap pairs in a first group and half of such enabled tap pairs in a second group, wherein the first group and the second group are separated temporally from each other in order to facilitate matching of input and output waveforms. Accordingly, when enabling additional tap pairs, control circuitry 20 may enable a tap pair for each of the first group and the second group, and when disabling tap pairs, may disable a tap pair from each of the first group and the second group. Furthermore, when enabling (or disabling) additional tap pairs, control circuitry 20 may enable (or disable) tap pairs at tap locations by alternating between tap locations that decrease duration between the centers of each tap group and tap locations that increase duration between the centers of each tap group.

[0034] For example, as shown by the impulse response function of FIG. 7, when enabling two pairs of parallel taps (which may correspond to the lowest non-zero analog gain setting for DAC 14), control circuitry 20 may enable two tap pairs: one tap pair in the first group having a delay of t.sub.1 and another tap pair in the second group having a delay of t.sub.2. As shown in the impulse response function of FIG. 8, to increase analog gain by the lowest minimal amount above that shown in FIG. 7, control circuitry 20 may enable an additional two tap pairs: one tap pair having the lowest delay greater than t.sub.1 and another tap pair having the highest delay less than t.sub.2, such that the difference between the centers of the two groups slightly decreases, and the centers of the first group and the second group remain at approximately delays t.sub.1 and t.sub.2 (e.g., each center remains within the difference between delays t.sub.1 and t.sub.2 and the delays of their respective adjacent tap pairs). Moreover, as shown in the impulse response function of FIG. 9, to increase analog gain by the lowest minimal amount above that shown in FIG. 8, control circuitry 20 may enable an additional two tap pairs: one tap pair having the highest delay lower than ti and another tap pair having the lowest delay greater than t.sub.2, such that the difference between the centers of the two groups slightly increases, and the centers of the first group and the second group approximately return to delays t.sub.1 and t.sub.2, respectively.

[0035] Although the foregoing contemplates addition of two tap pairs to decrease the duration between centers of the first group and second group in FIG. 8 followed by addition of two tap pairs to increase the duration between centers of the first group and second group in FIG. 9, in some embodiments, control circuitry 20 may alternatingly enable tap pairs in the opposite order—to first increase duration between centers of the first group and second group and then to decrease duration between centers of the first group and second group.

[0036] Although the delays t.sub.1 and t.sub.2 selected by control circuitry 20 as the centers of the first group and second group, respectively, may be of any suitable delay duration, in some embodiments, control circuitry 20 may set delays t.sub.1 and t.sub.2 at 25% and 75%, respectively, of the pulse width of modified digital input signal DIG_IN′.

[0037] Further, although the foregoing contemplates the use of a differential input signal and pairs of differential gain taps, the systems and methods exemplified by FIGS. 4 through 9 and the description thereof may also be applied to an input network of a plurality of single-ended taps each having a delay, including each of the single-ended taps having a different delay.

[0038] As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

[0039] This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

[0040] Although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above.

[0041] Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale.

[0042] All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, ubstitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.

[0043] Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description.

[0044] To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.