SEMICONDUCTOR MEMORY DEVICE

Abstract

Disclosed herein is a semiconductor memory device. Provided is the semiconductor memory device includes a first device layer storing thermal energy and a second device layer being made of a material whose electrical properties are changed by the thermal energy, wherein the first device layer stores thermal energy if a voltage is applied to the second device layer. According to the present invention, since the device is composed of a material that is changed electrical characteristics by heat and a material that stores heat, it may be read as a current applied to the read voltage without applying other refresh voltage. In addition, there is no leakage current flowing through the device depending on the characteristics of the device, so additional circuit elements such as transistors and selectors are not required. The device has a fast-switching mechanism but does not cause leakage current thereby not showing resistance drift due to repetitive switching.

Claims

1. A device comprising: a first device layer storing thermal energy; and a second device layer including a material whose electrical properties are changed by the thermal energy, wherein the first device layer stores the thermal energy if a voltage is applied to the second device layer.

2. The device according to claim 1, wherein the second device layer comprises: a first layer including an electrically conductive material; a third layer including an electrically conductive material; and a second layer which is disposed between the first layer and the third layer, and whose electrical characteristics are changed by the thermal energy.

3. The device according to claim 2, wherein the conductive material of the first layer is selected from a group consisting of metallic, semiconductive, or organic materials comprising Pt, Ti, Ag, Au, Ru, TiN, W, Al, ITO, ZnO, IGZO, ITZO, NiO, SnO.sub.2, Graphene, or MoS.sub.2, wherein the conductive material of the third layer is selected from a group consisting of metallic, semiconductive, or organic materials comprising Pt, Ti, Ag, Au, Ru, TiN, W, Al, ITO, ZnO, IGZO, ITZO, NiO, SnO.sub.2, Graphene, or MoS.sub.2.

4. The device according to claim 1, wherein the second device layer comprises one or more layers whose electrical properties are changed by the thermal energy.

5. The device according to claim 2, wherein the second layer is made of a material whose resistance changes by temperature, or a material in which metal-insulator transition occurs at a specific temperature.

6. The device according to claim 5, wherein the material is a resistance change material comprising one or more selected from a group consisting of metal oxide-based, high molecular polymer-based, or low molecular compound-based material including vanadium oxide (VO.sub.x), niobium oxide (NbO.sub.x), tantalum oxide (TaO.sub.x), germanium antimony telluride (Ge.sub.2Sb.sub.2Te.sub.5) or zinc telluride (ZnTe).

7. The device according to claim 2, wherein the first device layer comprises at least one layers, and is disposed at an under portion, at a side portion, or at an upper portion of the second device layer, or is formed to surround the second device layer, and wherein the first device layer is made of a material selected from a group consisting of high molecular polymer-based or metal oxide-based including polyimide, polyethylene terephthalate, polyether-sulfone, polyethylene naphthalate, polycarbonate, silicon (Si), silicon dioxide (SiO.sub.2), glass, or aluminum oxide (AlO.sub.x).

8. The device according to claim 2, wherein when thermal energy is not stored in the first device layer, a current does not flow in the second device layer if a read voltage is applied.

9. The device according to claim 2, wherein when thermal energy is stored in the first device layer, a current flow in the second device layer if a read voltage is applied.

10. The device according to claim 9, wherein if a programming voltage is applied, thermal energy is generated in the second layer of the second device layer by the applied voltage, thereby the thermal energy is stored in the first layer.

11. The device according to claim 9, wherein the device includes a refresh operation of generating heat to store thermal energy in the first device layer by a programming voltage and maintaining the thermal energy stored in the first device layer by the read voltage.

12. The device according to claim 9, wherein the device is operated by a driving method which includes a read operation for periodically reading 0 or 1 depending on a presence or absence of current in the second device layer by periodically applying the read voltage in a form of a voltage pulse train, and an operation of maintaining the current state at 0 wherein thermal energy is not generated when the current state of the second device layer is 0 by the read voltage, thereby the current state is maintained at 0 by maintaining the thermal energy of the first device layer.

13. The device according to claim 10, wherein the device is operated by a driving method which includes a read operation for periodically reading 0 or 1 depending on a presence or absence of current in the second device layer by periodically applying the read voltage in a form of a voltage pulse train, and an operation of maintaining the current state at 0 wherein thermal energy is generated when the current state of the second device layer is 1 by the read voltage, to perform a refresh operation with the read voltage, thereby the current state is maintained at 1 by maintaining the thermal energy of the first device layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The various features of the present disclosure will now be described with reference to the drawing of the various aspects disclosed herein. In the drawings, the same components may have the same reference numerals. The illustrated aspects are intended to illustrate, but not limit the present disclosure. The drawings include the following figures:

[0027] FIG. 1 schematically illustrates the semiconductor memory device according to an exemplary embodiment;

[0028] FIG. 2A illustrates electric and thermal energy flows in the semiconductor memory device of FIG. 1.

[0029] FIG. 2B illustrates electric and thermal energy flows in the semiconductor memory device of FIG. 1.

[0030] FIG. 3A illustrates NDR changes depending on temperature and voltage.

[0031] FIG. 3B illustrates NDR changes depending on temperature and voltage.

[0032] FIG. 4 illustrates the driving method of the semiconductor memory device according to an exemplary embodiment.

[0033] FIG. 5 illustrates explaining the operating principle of the semiconductor memory device according to an exemplary embodiment.

[0034] FIG. 6A illustrates explaining an operation with an unprogrammed state.

[0035] FIG. 6B illustrates explaining an operation with an unprogrammed state.

[0036] FIG. 7A illustrates explaining an operation with a programmed state.

[0037] FIG. 7B illustrates explaining an operation with a programmed state.

[0038] FIG. 8 illustrates explaining a leakage current of the semiconductor memory device according to an exemplary embodiment.

DETAILED DESCRIPTION

[0039] Hereinafter, preferred embodiments of the present invention will be described in detail concerning the attached drawings.

[0040] However, the technical idea of the present invention is not limited to some of the described embodiments but may be implemented in various forms, and one or more of the components may be selectively combined and replaced between the embodiments within the technical idea of the present invention.

[0041] The terms (including technical and scientific terms) used in the embodiments of the present invention, unless explicitly specifically defined and stated, can be interpreted as generally understood by those with ordinary knowledge in the technical field to which this invention belongs, and commonly used terms such as predefined terms can be interpreted by considering the context of the relevant technology.

[0042] The terms used in the embodiments of the present invention are intended to describe the embodiments and not intended to limit the present invention.

[0043] In the specification, a singular form may include the plural form unless specified in the phrase. Also when it is described as “at least one (one or more) of “A else (and) B, C”, it may include one or more of all combinations that can be combined with A, B, and C.

[0044] In describing the components of the embodiment of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

[0045] These terms are intended to distinguish the components from other components, and are not limited to the essence, sequence, or order of the components by the term.

[0046] When it is described that a component is ‘connected’, ‘combined’, or ‘contact’ with another component, the component is not only directly connected, combined, or in contact with another component, it may also include the case of ‘connected’, ‘ combined’ or ‘ contact’ due to other components between one component and another component.

[0047] When described as being formed or placed in “upper (on) or lower (under)” of each component, upper (on) or lower (under) includes not only when two components are directly in contact with each other, but it may also include the case of one or more other components are formed or placed between the two components. In addition, when expressed as “upper (on) or lower (under)” it may contain the meaning of the downward direction as well as the upward direction based on one component.

[0048] A semiconductor memory device according to an embodiment is composed of the material whose electrical characteristics are changed by heat and the material for storing heat, and it will be referred to as Thermal Dynamic RAM (TDRAM). It is not limited to the structures and materials of the semiconductor memory devices presented below, and it may apply to general material and device structures in which electrical properties are changed by heat.

[0049] FIG. 1 is an illustration of the semiconductor memory device according to an exemplary embodiment of the present invention.

[0050] Referring to FIG. 1, the semiconductor memory device according to an embodiment of the present invention may include a first device layer 100 and a second device layer 200, and the second device layer 200 may include a first layer 210, a second layer 220, and a third layer 230.

[0051] The second device layer 200 may be made of a material whose electrical properties are changed by ambient heat and serves as a switch. The second device layer 200 may have a metal-insulator-metal (MIM) structure in which the first layer 210, the second layer 220, and the third layer 230 are sequentially stacked. However, it is sufficient if the second layer 220 is disposed of between the first layer 210 and the third layer 230, and it is not necessary to have the stacked structure.

[0052] That is, the second device layer 200 is disposed between the first layer 210 made of an electrically conductive material and the third layer 230 made of an electrically conductive material. The second device layer includes the second layer 220 whose electrical characteristics are changed by thermal energy.

[0053] The first layer 210 may include an electrically conductive material. As the conductive material, for example, Pt, Ti, Ag, Au, Ru, TiN, W, Al, ITO, ZnO, IGZO, ITZO, NiO, SnO.sub.2, graphene, or MoS.sub.2 may be selected.

[0054] The second layer 220 which is disposed between a first layer 210 and a third layer 230 may include resistance changes material according to temperature. For example, there is the resistance change material comprises one or more selected from the group consisting of metal oxide-based, high molecular polymer-based, or low molecular compound-based material including vanadium oxide (VO.sub.x), niobium oxide (NbO.sub.x), tantalum oxide (TaO.sub.x), germanium antimony telluride (Ge.sub.2Sb.sub.2Te.sub.5), or zinc telluride (ZnTe).

[0055] A third layer 230 may be made of a metallic material. As the metallic material, for example, Pt, Ti, Ag, Au, Ru, TiN, W, Al, ITO, ZnO, IGZO, ITZO, NiO, SnO.sub.2, graphene, or MoS.sub.2 may be selected.

[0056] The first device layer 100 may be comprised of at least one layers adjacent to the second device layer 200. The first device layer 100 may be made adjacent to the second device layer 200 to control the temperature of the second device layer.

[0057] The first device layer 100 may be made of a material storing heat. For example, the first device layer 100 may be made of a material selected from the group consisting of high molecular polymer-based, or metal oxide-based including polyimide, polyethylene terephthalate, polyether-sulfone, polyethylene naphthalate, polycarbonate, silicon (Si), silicon oxide (SiO.sub.2), glass (Glass), or aluminum oxide (AlO.sub.x), but is not limited thereto.

[0058] According to the exemplary embodiment, the semiconductor memory device stores information in the form of thermal energy and does not cause electrical leakage even when thermal energy is leaked.

[0059] FIGS. 2A and 2B are diagrams illustrating electric and thermal energy flows of the semiconductor memory device illustrated in FIG. 1.

[0060] The first device layer 100 is disposed to store thermal energy generated in the second device layer 200. It may be disposed at an under portion, at a side portion, or at an upper portion of the second device layer, or is formed to surround the second device layer 200. The first device layer 100 may be disposed of where thermal energy can be reached, it is not limited to a specific location.

[0061] FIGS. 3A and 3B are diagrams illustrating NDR changes according to temperature and voltage.

[0062] Referring to FIGS. 2A and 2B, the first device layer 100 may store thermal energy when the ambient temperature rises. In this case, the ambient temperature may be controlled by heat generated by the current of the device or it may be controlled using a hot plate or the like.

[0063] If thermal energy is stored in the second device layer 200, the electrical characteristics of the material including of the second device layer 200 are changed by the stored thermal energy, so that the flow of electrical energy may be confirmed.

[0064] FIG. 3A shows the NDR change according to the ambient temperature change, and FIG. 3B shows the NDR change according to the voltage applied to the heater for controlling the temperature. The NDR refers to a phenomenon in which the curve of the current-voltage characteristic graph appears nonlinearly like the shape of an alphabet ‘S’. Contrary to general characteristics, this NDR characteristic shows that the voltage rather decreases when the applied current amount increases in a specific range. The NDR characteristic was caused by a phenomenon in which the voltage drop between the two electrodes was rapidly decreased. This is a phenomenon that occurs when the quantum hybridization state collapses after a specific voltage.

[0065] FIG. 4 is the diagram illustrating a driving method of a semiconductor memory device according to an embodiment of the present invention.

[0066] Referring to FIG. 4, the semiconductor memory device according to the exemplary embodiment may be programmed after accumulating heat by applying a programming voltage to the switching material, that is, the second device layer 200.

[0067] Referring again to FIGS. 2A and 2B, when an electric field is applied from the first layer to the third layer, the current flows through the second layer. That is, heat is generated inside the second layer due to Joule heating (heat is generated by the current passing through the conductor), and the material inside the second layer is changed from an insulating state to a conductive state by the heat.

[0068] At this time, ambient heat may also affect the temperature of the second layer.

[0069] A read voltage may be applied to the second device layer 200 and a current may be read to distinguish a state (e.g., 0 or 1). In this case, the reading process may include a refresh process.

[0070] That is, the semiconductor memory device according to the exemplary embodiment, may be capable of simultaneously performing the refresh process and the reading process without performing other read processes for reading a current.

[0071] FIG. 5 is a diagram illustrating an operating principle of a semiconductor memory device according to an exemplary embodiment.

[0072] Referring to FIG. 5 if little voltage, for example, 0.92V is applied to the second device layer 200 in a state in which information is not stored since the second device layer 200 is not switched, the second device layer 200 is switched, and changed to a state in which information is stored. In this case, the storage of information may be accomplished by accumulating heat in the first device layer 100 by switching the second layer 220 constituting the second device layer 200 by the applied voltage.

[0073] FIGS. 6A and 6B are diagrams for explaining an operation in the unprogrammed state.

[0074] Referring to FIGS. 6A and 6B, if heat is not accumulated in the first device layer 100, in case of the unprogrammed state, even if the read voltage is applied, it is not programmed.

[0075] That is, when the read voltage is applied, the switching material of the second device layer 200 becomes a state in which no current flows (0 or off), so programming is not performed.

[0076] FIGS. 7A and 7B are diagrams for explaining an operation in the programmed state.

[0077] Referring to FIGS. 7A and 7B, if heat is accumulated in the first device layer 100, in the case of the programmed state, the stored thermal energy is maintained when a read voltage is applied.

[0078] That is, when a read voltage is applied, the switching material of the second device layer 200 becomes a state in which no current flows (0 or off), so programming is not performed.

[0079] FIG. 8 is a diagram for explaining a leakage current of a semiconductor memory device according to an exemplary embodiment.

[0080] Referring to FIG. 8, heat leakage is not observed in the form of electricity in the semiconductor memory device according to the embodiment.

[0081] For example, when the semiconductor memory device is in the form of a 2-terminal crossbar, the possibility of a leakage current problem may be low because the resistance state is not changed and stored.

[0082] Thus the semiconductor memory device according to the exemplary embodiment is made of a material whose electrical characteristics are changed by heat and material that stores heat, it does not cause electrical leakage. Also, the resistance drift phenomenon of the device due to repetitive switching may not occur.

[0083] The preferred embodiment of the present invention has been described above, it will be understood by those skilled in the art that the present invention may be variously modified and changed within the spirit and area of the present invention described in the following patent claims.