Abstract
A large area active-matrix organic light-emitting diode microdisplay and method for fabricating the same is provided which includes a panel having resolution of greater than 2,000 pixels per inch and a size of 1.4 or more inches for supporting the needs of virtual reality and augmented reality application.
Claims
1-10. (canceled)
11. A method of fabricating an organic light-emitting diode (OLED) display device, the method comprising: providing a reticle that includes a primary sub-block for forming a pixel array, each pixel of the array including a pixel circuit; fabricating a plurality of pixel arrays on a substrate using the reticle, wherein the plurality of pixel arrays defines a backplane pixel array that includes at least one stitching boundary residing between at least two pixel arrays of the plurality of pixel arrays; and forming an OLED emitter array on the backplane pixel array, wherein each OLED emitter of the OLED emitter array is electrically connected to a different pixel circuit of the backplane pixel array, and wherein the OLED emitter array has uniform pitch across the entire display device.
12. The method of claim 11 further comprising: providing the reticle such that it includes two secondary sub-blocks; fabricating an interconnect region having a sub-pixel driving array on the substrate using the two secondary sub-blocks of the reticle, wherein the sub-pixel driving array includes two or more metal layers and a plurality of sub-pixel drivers; and attaching the plurality of pads to the two or more metal layers by the anisotropic conductive film.
13. The method of claim 11 wherein the pixel array is configured in an active matrix.
14. The method of claim 11 wherein the reticle is used to define the pixel array and a plurality of wiring pads.
15. The method of claim 11 wherein the pixel array includes two transistors and an inverted organic light-emitting diode stack.
16. The method of claim 15 wherein at least one transistor is a high voltage n-channel metal-oxide silicon (NMOS) device or a lateral double-diffused metal-oxide-silicon (LDMOS) device.
17. The method of claim 11 wherein the pixel array has a resolution of at least 2,000 pixels per inch.
18. The method of claim 11 wherein the display device has a panel size of at least 35 mm per side.
19. A method of fabricating an organic light-emitting diode (OLED) display device, the method comprising: providing a reticle that includes a primary sub-block for forming a pixel array, each pixel of the array including a pixel circuit that includes a first thin-film transistor for driving an OLED; fabricating a plurality of pixel arrays on a substrate using the reticle, wherein the plurality of pixel arrays defines a backplane pixel array that includes at least one stitching boundary residing between at least two pixel arrays of the plurality of pixel arrays such that the pixels of the backplane pixel array are arranged with non-uniform spacing across the display device; and forming an OLED emitter array on the backplane pixel array, wherein each OLED emitter of the OLED emitter array is electrically connected to the first thin-film transistor of a different pixel circuit of the backplane pixel array, and wherein the OLED emitter array has uniform pitch across the entire display device.
20. The method of claim 19 further comprising: providing the reticle such that it further includes two secondary sub-blocks; and fabricating an interconnect region having a sub-pixel driving array on the substrate using the two secondary sub-blocks of the reticle, wherein the sub-pixel driving array includes two or more metal layers and a plurality of sub-pixel drivers.
21. The method of claim 19 wherein the backplane pixel array is formed such that it is configured in an active matrix.
22. The method of claim 19 wherein each OLED of the OLED emitter array is formed such that it is configured as an inverted organic light-emitting diode stack.
23. The method of claim 22 wherein the first thin-film transistor is formed such that it is a high voltage n-channel metal-oxide silicon (NMOS) device or a lateral double-diffused metal-oxide-silicon (LDMOS) device.
24. The method of claim 19 wherein the pixel array has a resolution of at least 2,000 pixels per inch.
25. The method of claim 19 wherein the display device has a panel size of at least 35 mm per side.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1A depicts a conventional mobile display panel used in virtual reality applications in accordance with the prior art.
[0021] FIG. 1B is a schematic cross-sectional view of the mobile display panel of FIG. 1A.
[0022] FIGS. 2A and 2B is a plan view of a large area silicon backplane formed using a conventional stitching process.
[0023] FIG. 3 is a schematic view showing a configuration for a large format display in accordance with the illustrative embodiment of the present invention.
[0024] FIG. 4A depicts an enlarged view of a single reticle in accordance with a patterning method of the present invention used to form the large format display device of FIG. 3.
[0025] FIG. 4B depicts an enlarged view of a patterned array die in accordance with the patterning method of FIG. 4A.
[0026] FIG. 5 depicts an enlarged view of an interconnect region of a pixel array in accordance with the patterning method of FIG. 4A.
[0027] FIG. 6A is a schematic view showing a pixel array arrangement having a vertical stitching boundary in accordance with the patterning method used to form the large format display device of the present invention.
[0028] FIG. 6B is a schematic view showing a pixel array arrangement having a non-stitched OLED pattern in accordance with the patterning method used to form the large format display device of the present invention.
[0029] FIG. 7 is a schematic view of a pixel circuit in accordance with the illustrative alternative of the present invention.
DETAILED DESCRIPTION
[0030] FIGS. 1A and 1B illustrates a conventional mobile display panel 100 used in virtual reality applications. The panel 100 consists of a polysilicon thin-film-transistor (TFT) 104 on glass backplane 102, with an OLED layer 106 deposited on top. Preferably, the OLED layer 106 is a side-by-side color architecture with each color stack evaporated through a fine metal mask. Separate driver integrated circuits (ICs) 108 are attached to the glass substrate using an anisotropic adhesive film (ACF) layer 110. Separate flexible printed circuits (FPCs) 112 are attached to the glass substrate using an anisotropic adhesive film (ACF) layer 114.
[0031] FIGS. 2A and 2B illustrates a conventional silicon stitching method 200 used to build semiconductor chips 202 at a foundry that are larger than possible with existing patterning tools. The chip 202 is partitioned into sub-blocks 204, which must fit into a single reticle 206. Each sub-block 204 is patterned across the wafer 208 in sequence. Method 200 is limited to fabricating specialty devices due to high production costs. As shown, the stitching method requires partitioning the chip design into a collection of sub-blocks 204 that all fit onto a single set of reticles 206. During wafer patterning these sub-blocks 204 are exposed sequentially at specific locations in order to reconstruct the complete design at multiple positions across the wafer. Method 200 is costly due to the large number of steps necessary to expose various sub-blocks for each mask layer in the process. For example, if chip design is partitioned into 10 sub-blocks the total patterning time will take 10 times as long as it would take to expose the full design all at once. The patterning throughput will then either be 10 times longer or the number of lithography tools increased by 10 times. As such, cost of production is significantly increased. Additionally, large upfront engineering cost are necessary to create partitioned designs that fit one reticle set. Furthermore, separate layout design rules are required for sub-field boundaries that add to layout complexity and increase overall size of architecture as compared to a non-stitched version. Finally, stitching boundaries result in optical artifacts due to displacement of pixels along stitching line as illustrated in FIG. 6A.
[0032] FIG. 3 illustrates an exemplary view of a panel architecture 300 as proposed by the present invention. Panel architecture 300 includes an OLED emitting layer 304 deposited on a single crystal substrate 302 that is used for implementing the backplane pixel array 306. Separate column driver chips 308 and row drivers chips 310 are attached to the silicon substrate 302 using an ACF layer 312. In some embodiments, a plurality of anisotropic conductive balls (not shown) are formed having the same anisotropic properties as an anisotropic conducting film. The OLED display device contemplated by the present invention resolution of at least 2,000 pixels per inch and a panel size of at least 35 mm per side.
[0033] FIGS. 4A and 4B illustrate an exemplary patterning method 400 provided by the present invention. A single reticle 402 is used, which contains primarily the array sub-block 404 and, secondarily, a pair of small sub-blocks 408 and 410 for the interconnect region 406. In particular, reticle 402 is partitioned into primary sub-block (pixel array) 404 and two secondary sub-blocks 408 and 410 that form the interconnect region 406 for the ACF attachment layer 312 of external driver chips as shown in FIG. 3. Pixel array 404 is formed on a single crystal wafer 314 in this concept (as illustrated in FIG. 3), which also serves as the substrate 302 for the OLED emitters and the external driver chips. A reduced cost silicon wafer can be used as the substrate because the pixel array 404 can be built with NMOS only transistors as illustrated in FIG. 7, resulting in a simplified twelve mask wafer process. In addition, the interconnect regions 406 are formed using only two metal layers and two via layers, further reducing the cost of stitching these sub-blocks which each only require four exposures. As such, reticle masks and patterning exposures is greatly reduced compared to conventional stitching approaches.
[0034] FIG. 5 illustrates an exploded view of the interconnect region 406 of FIGS. 4A and 4B, which consists of two metal layers used to implement data line wiring tracks 502A and select pad wiring tracks 502B and ACF attachment pads 504, including select pads 504A, ground pads 504B, and data line pads 504C in order to achieve higher pixel density with existing ACF interconnect technology. As shown in FIG. 5, dual metals allow pads 504 to be expanded directionally away from pixel array 404 so as to maintain large pad area while still connecting to high-density column array. In some embodiments, connections can be made to both sides of the pixel array to further increase working pixel density achieved. In some embodiments, the chips and 308 and 310 are mounted to a circuit film (not shown) which is adhered to the pad through the ACF layer 312. These films on which the chips are mounted may be formed of tape carrier package TCP or chip-on-film COF.
[0035] FIGS. 6A and 6B illustrate use of a large field stepper for OLED emitter patterning to overlay silicon pixel cells to avoid optical artifacts due to stitching. As shown in FIG. 6A, stitching boundary 602 at pixel array 404 can result in an optical artifact if it is matched at OLED emitter pattern 604. Alternatively, pixel array pitch can be increased across the full pixel array 404 to achieve a uniform appearance. In the present invention, as illustrated in FIG. 6B, OLED emitter 604 pitch is maintained at a uniform level across entire display by offsetting it slightly over silicon pixel cells. This is achieved when only one, or in some embodiments, two stitching boundaries exist across the pixel array 404 which can be accommodated by design rule margins. A large field stepper is available for use in defining OLED emitter patterns up to 50 mm on a side since the resolution required for the OLED patterns is much lower than necessary for silicon device patterns.
[0036] FIG. 7 illustrates an exemplary design for pixel circuit 700 that can be implemented in a simplified negative channel metal-oxide-semiconductor (NMOS) logic process. The pixel circuit 700 uses inverted OLED diode architecture. The pixel circuit 700 includes thin film transistors (TFTs) 702 and 704, a capacitor 706, an OLED 708, which is the light-emitting element. OLED 708 has a common anode 712 and its cathode connected to a ground potential GND 710. In some embodiments, alternative OLED architectures may be employed.
[0037] In some embodiments, various changes may be made in the transparent materials or number of OLED layers, all while preserving the function of the present invention as described herein. The organic light emitting devices may be either top or bottom emitting. Further, it may be appropriate to make various modifications in materials of the present invention, or in the mode of operation of a preferred embodiment of the present invention. Thus, it will be apparent to those skilled in the art after reading this disclosure that various modifications and variations of the can be made in the construction and configuration of the present invention without departing from the scope or spirit of the invention and that the scope of the present invention is to be determined by the following claims.
