Power source device for electric discharge machine

Abstract

A power supply device for an electric discharge machine includes a DC power supply which is connected in parallel to an electrode gap, a plurality of switching elements which are in parallel to each other and which are arranged between the electrode gap and the DC power supply, a current value acquisition unit for acquiring a value of a current, and an ON-OFF control unit which, during the time when the current value reaches a predetermined value until the time when the current starts to fall, sets a cycle for switching the plurality of switching elements from off to on to the same cycle, switches the plurality of switching elements from off to on in a predetermined order for each timing of a phase of 90°, which is 360° divided by the number of the plurality of switching elements, sets an ON-period of each of the plurality of switching elements based on a difference between the value of the current and the predetermined value, and performs ON-OFF control of the plurality of switching elements based on the cycle, the timing, and the ON-period.

Claims

1. A power supply device for an electric discharge machine for supplying a pulsed current to an electrode gap constituted by a workpiece and an electrode, which are opposed to each other with a predetermined gap, for electric discharge machining a workpiece, the power supply device comprising: a DC power supply which is connected in parallel to the electrode gap for applying a voltage for generating the current to the electrode gap, a plurality of switching elements which are in parallel to each other and which are arranged between the electrode gap and the DC power supply, current value acquisition circuitry for acquiring a current value, and an ON-OFF controller which, during the time interval from the time when the current value reaches a predetermined value to the starting time of a fall of the current value, sets a cycle for switching the plurality of switching elements from off to on to be the same cycle, switches the plurality of switching elements from off to on in sequence for each timing of a phase of a predetermined angle, sets an ON-period of each of the plurality of switching elements based on a difference between the current value and the predetermined value, and performs ON-OFF control of the plurality of switching elements based on the cycle, the timing, and the ON-period.

2. The power supply device for an electric discharge machine according to claim 1, wherein the timing of phase of a predetermined angle is an equal timing of a phase of an angle obtained by dividing 360° by the number of the plurality of switching elements.

3. The power supply device for an electric discharge machine according to claim 1, wherein the ON-OFF controller reduces the ON-period when the current value becomes greater than a first threshold value, which is greater than the predetermined value, and increases the ON-period when the current value is less than a second threshold value, which is less than the predetermined value.

4. The power supply device for an electric discharge machine according to claim 1, wherein current regeneration circuitry for regenerating the current is arranged between a first connection point between the electrode gap and one of the plurality of switching elements and a second connection point between the electrode gap and the DC power supply.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1 is a view showing a circuit of a power supply device for an electric discharge machine according to an embodiment of the present invention.

(2) FIG. 2 is a flowchart detailing the operation of the power supply device for an electric discharge machine of FIG. 1.

(3) FIG. 3 is a timing chart detailing the operation of the power supply device for an electric discharge machine of FIG. 1

(4) FIG. 4 is an enlarged view of portion A of the timing chart of FIG. 3.

(5) FIG. 5 is an enlarged view of portion B of the timing chart of FIG. 3.

DETAILED DESCRIPTION OF THE DISCLOSURE

(6) The embodiments of the power supply device for an electric discharge machine according to the present invention will be described in detail below while referring to the drawings.

(7) FIG. 1 is a view showing a circuit of the power supply device for an electric discharge machine according to an embodiment of the present invention. In FIG. 1, the power supply device 1 for an electric discharge machine supplies pulsed current for electric discharge machining a workpiece 2, which is immersed in an electric discharge machining liquid in a machining tank (neither illustrated), to an electrode gap 4 constituted by the workpiece 2 and an electrode 3, which are opposed to each other with a predetermined gap, via a cable 5.

(8) The power supply device 1 for an electric discharge machine comprises a DC power supply 6, NMOS transistors 7a, 7b, 7c, 7d, diodes 8a, 8b, 8c, 8d, 9a, 9b, 9c, 9d, and a control unit 10.

(9) The DC power supply 6 is connected in parallel to the electrode gap 4 for applying a voltage for generating current to the electrode gap 4. The pulsed voltage applied to the electrode gap 4 is, for example, 75 to 160 V, and has a frequency from approximately 1 KHz to several tens of KHz. In the present embodiment, the positive side of the DC power supply 6 is connected to the electrode 3 and the negative side of the DC power supply 6 is connected to the workpiece 2 via a shunt resistor 11.

(10) The NMOS transistor 7a is arranged between the cable 5 and the positive side of the DC power supply 6. The NMOS transistor 7b is connected in parallel to the NMOS transistor 7a, and is arranged between the electrode 3 and the positive side of the DC power supply 6. In the present embodiment, one end of the NMOS transistor 7b is connected to a connection point 21 between the positive side of the DC power supply 6 and the NMOS transistor 7a via a connection point 22 between the connection point 21 and one end of the NMOS transistor 7b, and the other end of the NMOS transistor 7b is connected to a connection point 23 between the cable 5 and the positive side of the DC power supply 6.

(11) The NMOS transistor 7c is connected in parallel to the NMOS transistors 7a, 7b, and is arranged between the electrode 3 and the positive side of the DC power supply 6. In the present embodiment, one end of the NMOS transistor 7c is connected to a connection point 24 between the connection point 22 and one end of the NMOS transistor 7c, and the other end of the NMOS transistor 7c is connected to a connection point 25 between the cable 5 and the connection point 23.

(12) The NMOS transistor 7d is connected in parallel to the NMOS transistors 7a, 7b, 7c, and is arranged between the electrode 3 and the positive side of the DC power supply 6. In the present embodiment, one end of the NMOS transistor 7d is connected to the connection point 24, and the other end of the NMOS transistor 7d is connected to a connection point 26 between the cable 5 and the connection point 25.

(13) Therefore, the NMOS transistors 7a, 7b, 7c, 7d are in parallel to each other and are arranged between the electrode 3 and the positive side of the DC power supply 6. The NMOS transistors 7a, 7b, 7c, 7d are examples of a plurality of switching elements.

(14) The diode 8a is provided for backflow prevention, and has a cathode which is connected to the connection point 23 and an anode which is connected to the NMOS transistor 7a. The diode 8b is provided for backflow prevention, and has a cathode which is connected to the connection point 23 and an anode which is connected to the NMOS transistor 7b. The diode 8c is provided for backflow prevention, and has a cathode which is connected to the connection point 25 and an anode which is connected to the NMOS transistor 7c. The diode 8d is provided for backflow prevention, and has a cathode which is connected to a connection point 26 and an anode which is connected to the NMOS transistor 7d.

(15) The diode 9a is provided for regenerating current immediately after the NMOS transistor 7a is switched from on to off, and is arranged between a connection point 27 between the NMOS transistor 7a and the anode of the diode 8a and a connection point 28 between the electrode gap 4 and the negative side of the DC power supply 6. The connection point 27 is an example of a first connection point and the connection point 28 is an example of a second connection point.

(16) The diode 9b is provided for regenerating current immediately after the NMOS transistor 7b is switched from on to off, and is arranged between a connection point 29 between the NMOS transistor 7b and the anode of the diode 8b and a connection point 30 between the electrode gap 4 and the connection point 28. The connection point 29 is an example of a first connection point and the connection point 30 is an example of a second connection point.

(17) The diode 9c is provided for regenerating current immediately after the NMOS transistor 7c is switched from on to off, and is arranged between a connection point 31 between the NMOS transistor 7c and the anode of the diode 8c and a connection point 32 between the electrode gap 4 and the connection point 30. The connection point 31 is an example of a first connection point and the connection point 32 is an example of a second connection point.

(18) The diode 9d is provided for regenerating current immediately after the NMOS transistor 7d is switched from on to off, and is arranged between a connection point 33 between the NMOS transistor 7d and the anode of the diode 8d and a connection point 34 between the electrode gap 4 and the connection point 32. The connection point 33 is an example of a first connection point and the connection point 34 is an example of a second connection point.

(19) The diodes 9a, 9b, 9c, 9d are examples of current regeneration units.

(20) The control unit 10 is constituted by, for example, a field-programmable gate array (FPGA), and comprises a current value acquisition unit 10a and an ON-OFF control unit 10b.

(21) The current value acquisition unit 10a is connected to a connection point 35 between the connection point 34 and one end of the shunt resistor 11 and a connection point 36 between the other end of the shunt resistor 11 and the workpiece 2, and has a current-sense amplifier (not illustrated) which amplifies and outputs voltage at both ends of the shunt resistor 11 corresponding to the value of the current flowing through the electrode gap 4.

(22) Furthermore, the current value acquisition unit 10a acquires the value of the current flowing through the electrode gap 4 by converting the value of the voltage output from the current-sense amplifier to a current value based on a table, which represents the relationship between voltage and current, stored in a storage unit (not illustrated) of the control unit 10. Further, the current value acquisition unit 10a provides data of the acquired current value I.sub.d to the ON-OFF control unit 10b.

(23) In addition to the table which represents the relationship between voltage and current, data on a target current I.sub.t, a target upper limit, and a target lower limit, which will be described later, as well as a control computer program are stored in the storage unit of the control unit 10.

(24) The ON-OFF control unit 10b receives as input a pulse signal P which is generated by a pulse generation circuit 13 based on pulse generation conditions corresponding to the machining conditions settings of the workpiece 2 set in an NC device 12 automatically or by an operator. The machining conditions settings for the workpiece 2 are determined in accordance with the material of the workpiece 2, the material of the electrode 3, the machining shape of the workpiece 2, etc. The pulse generation conditions include a pulse wave on/off time, the number of pulses of the pulse wave, a pulse pause time, etc.

(25) Further, the ON-OFF control unit 10b generates a pulse signal S1 for turning on or off the NMOS transistor 7a, a pulse signal S2 for turning on or off the NMOS transistor 7b, a pulse signal S3 for turning on or off the NMOS transistor 7c, and a pulse signal S4 for turning on or off the NMOS transistor 7d based on the data of the current value I.sub.d and the pulse signal P.

(26) In the present embodiment, the ON-OFF control unit 10b sets the switching cycles at which the NMOS transistors 7a, 7b, 7c, 7d are turned from off to on to the same cycle T during the time when the current value I.sub.d reaches a target current I.sub.t corresponding to a peak current until the current starts to fall. The target current I.sub.t is an example of the predetermined value.

(27) Furthermore, the ON-OFF control unit 10b switches the NMOS transistor 7a, the NMOS transistor 7b, and the NMOS transistors 7c and 7d from off to on in this order for each timing of a phase of 90° corresponding to ¼ of the switching cycle during the time when the current value I.sub.d reaches the target current I.sub.t until the current starts to fall. In other words, the ON-OFF control unit 10b switches the NMOS transistors 7a, 7b, 7c, 7d from off to on in this order for each timing of a phase of 90° during the time when the current value I.sub.d reaches the target current I.sub.t until the current starts to fall.

(28) The timing of a phase of 90° is an example of a timing of a phase of a value obtained by dividing 360° by the number of the plurality of switching elements. The phase timings need not be uniform in this manner, may be predetermined, may be 360° in one cycle, and may be, for example, 80°, 100°, 80° and 100°. Furthermore, the ON-OFF control unit 10b determines the switching cycle of each of the NMOS transistors 7a, 7b, 7c, 7d and the timing at which the switching cycle of each of the NMOS transistors 7a, 7b, 7c, 7d rises based on a clock (not illustrated) of the control unit 10. The timing at which the switching cycle of each of the NMOS transistors 7a, 7b, 7c, 7d rises corresponds to the timing at which each of the NMOS transistors 7a, 7b, 7c, 7d is switched from off to on.

(29) Furthermore, the ON-OFF control unit 10b sets the ON-period of each of the NMOS transistors 7a, 7b, 7c, 7d based on the difference between the current value I.sub.d and the target current I.sub.t during the time when the current value I.sub.d reaches the target current I.sub.t until the current starts to fall.

(30) In the present embodiment, the ON-OFF control unit 10b reduces the ON-period of the NMOS transistor that is switched from off to on among the NMOS transistors 7a, 7b, 7c, 7d when the current value I.sub.d is greater than the target upper limit, which is greater than the target current I.sub.t. The target upper limit is an example of a first threshold value.

(31) Furthermore, in the present embodiment, the ON-OFF control unit 10b increases the ON-period of NMOS transistor 7a, 7b, 7c, 7d that is switched from off to on among the NMOS transistors 7a, 7b, 7c, 7d when the current value I.sub.d is less than the target lower limit, which is less than the target current I.sub.t. The target lower limit is an example of a second threshold value.

(32) For example, if the ON-period of the NMOS transistors 7a, 7b, 7c, 7d when the current value I.sub.d is between the target upper limit and the target lower limit is T.sub.a, the ON-period of the NMOS transistors 7a, 7b, 7c, 7d when the current value I.sub.d is less than the target lower limit is T.sub.b, the ON-period of the NMOS transistors 7a, 7b, 7c, 7d when the current value I.sub.d is greater than the target upper limit is T.sub.c, and K.sub.b is a correction coefficient, the ON-period T.sub.b is determined based on the formula:
T.sub.b=T.sub.a+(I.sub.t−I.sub.d)×k.sub.b  [Math 1]

(33) and the ON-period T.sub.c is determined based on the formula:
T.sub.c=T.sub.a−(I.sub.t−I.sub.d)×k.sub.c  [Math 2]

(34) For example, the ON-period T.sub.a is ⅛ of the switching cycle, the ON-period T.sub.b is ¼ of the switching cycle, and the ON-period T.sub.c is 1/16 of the switching cycle.

(35) Further, the ON-OFF control unit 10b performs ON-OFF control of the NMOS transistors 7a, 7b, 7c, 7d based on the switching cycle, the timing of the phase of 90°, and the ON-period of each NMOS transistor 7a, 7b, 7c, 7d during the time when the current value I.sub.d reaches the target current I.sub.t corresponding to the peak current until the current starts to fall.

(36) FIG. 2 is a flowchart detailing the operation of the power supply device for an electric discharge machine of FIG. 1. This flow is executed every time the pulse signal P is switched from off to on, mainly by each element of the control unit 10, based on the control computer program stored in the storage unit of the control unit 10.

(37) First, the ON-OFF control unit 10b outputs pulse signals S1, S2, S3, S4 for turning on all of the NMOS transistors 7a, 7b, 7c, 7d to the NMOS transistors 7a, 7b, 7c, 7d, respectively (step S1).

(38) Next, the ON-OFF control unit 10b acquires the current value I.sub.d (step S2). Next, the ON-OFF control unit 10b determines whether the current value I.sub.d has reached the target current I.sub.t (step S3). When the current value I.sub.d has not reached the target current I.sub.t, the process returns to step S2 (No in step S3). Conversely, when the current value I.sub.d has reached the target current I.sub.t (Yes in step S3), the ON-OFF control unit 10b outputs the pulse signals S1, S2, S3, S4 for turning off all of the NMOS transistors 7a, 7b, 7c, 7d to the NMOS transistors 7a, 7b, 7c, 7d, respectively (step S4).

(39) Next, the ON-OFF control unit 10b starts the switching cycle of any of the NMOS transistors 7a, 7b, 7c, 7d (step S5).

(40) The ON-OFF control unit 10b starts the counting of a cycle counter (not illustrated) corresponding to the NMOS transistor for which the switching cycle has started (for example, the NMOS transistor 7a) (step S6). Furthermore, in step S6, the current value acquisition unit 10a acquires the current value I.sub.d.

(41) Next, the ON-OFF control unit 10b determines whether the current value I.sub.d is greater than the target upper limit (step S7). When the current value I.sub.d is greater than the target upper limit (Yes in step S7), the ON-OFF control unit 10b sets the ON-period of the NMOS transistor for which the switching cycle has started to T.sub.c and outputs a corresponding pulse signal to the NMOS transistor (step S8).

(42) Conversely, when the current value I.sub.d is not greater than the target upper limit (No in step S7), the ON-OFF control unit 10b determines whether the current value I.sub.d is less than the target lower limit (step S9). When the current value I.sub.d is less than the target lower limit (Yes in step S9), the ON-OFF control unit 10b sets the ON-period of the NMOS transistor for which the switching cycle has started to T.sub.b and outputs a corresponding pulse signal to the NMOS transistor (step S10).

(43) Conversely, when the current value I.sub.d is not less than the target lower limit (No in step S9), the ON-OFF control unit 10b sets the ON-period of the NMOS transistor for which the switching cycle has started to T.sub.a and outputs a corresponding pulse signal to the NMOS transistor (step S11).

(44) After step S8, step S10, or step S11, the ON-OFF control unit 10b determines whether the pulse signal P has fallen (step S12). When the pulse signal P has fallen (Yes in step S12), the control unit 10 ends the process. Conversely, when the pulse signal P has not fallen (No in step S12), the ON-OFF control unit 10b increases the count of the cycle counter corresponding to the NMOS transistor for which the switching cycle has started by ¼ cycle (step S13), and the process returns to step S6.

(45) As used herein, the ON-period T.sub.b of the NMOS transistors 7a, 7b, 7c, 7d refers to the ON-period until the current value I.sub.d becomes less than the target lower limit and then reaches the target current I.sub.t, and the ON-period T.sub.c refers to the ON-period until the current value I.sub.d reaches the target current I.sub.t after the current value I.sub.d has become greater than the target upper limit.

(46) FIG. 3 is a timing chart detailing the operation of the power supply device for an electric discharge machine of FIG. 1, FIG. 4 is an enlarged view of portion A of the timing chart of FIG. 3, and FIG. 5 is an enlarged view of portion B of the timing chart of FIG. 3.

(47) In the timing chart of FIG. 3, one cycle of a plurality of rising and falling cycles of the pulse signal P supplied to the ON-OFF control unit 10b for machining the workpiece 2 will be described.

(48) Furthermore, in the timing chart of FIG. 3, the cases in which the current value I.sub.d becomes less than the target lower limit during the period represented by portion A and the current value I.sub.d becomes greater than the target upper limit during the period represented by portion B will be described.

(49) In FIG. 3, (a) represents the pulse signal P, (b) represents the voltage of the electrode gap 4, and (c) represents the current value I.sub.d. Furthermore, in FIG. 3, (d), (e), and (f) represent the current flowing through the NMOS transistor 7a, the switching cycle of the NMOS transistor 7a, and the pulse signal S1, respectively. Furthermore, in FIG. 3, (g), (h), and (i) represent the current flowing through the NMOS transistor 7b, the switching cycle of the NMOS transistor 7b, and the pulse signal S2, respectively. Furthermore, in FIG. 3, (j), (k), and (l) represent the current flowing through the NMOS transistor 7c, the switching cycle of the NMOS transistor 7c, and the pulse signal S3, respectively. Furthermore, in FIG. 3, (m), (n), and (o) represent the current flowing through the NMOS transistor 7d, the switching cycle of the NMOS transistor 7d, and the pulse signal S4, respectively.

(50) In the timing chart of FIG. 3, the current value acquisition unit 10a acquires the current value I.sub.d each time a rise of any of the switching cycles of the NMOS transistors 7a, 7b, 7c, 7d is detected.

(51) When the pulse signal P rises at time t1, all of the NMOS transistors 7a, 7b, 7c, 7d are switched from off to on and voltage Vs1 is applied to the electrode gap 4 by the DC power supply 6. The operation for switching all of the NMOS transistors 7a, 7b, 7c, 7d, from off to on at time t1 corresponds to the process of step S1 of FIG. 2.

(52) When dielectric breakdown occurs in the electrode gap 4 at time t2 and the current value I.sub.d reaches the target current at time t3 due to the dielectric breakdown, all of the NMOS transistors 7a, 7b, 7c, 7d are switched from on to off. The operation for switching all of the NMOS transistors 7a, 7b, 7c, 7d from on to off at time t3 corresponds to the process of step S4 of FIG. 2. Furthermore, the operation in which the current value acquisition unit 10a acquires the current value I.sub.d each time a rise of any of the switching cycles of the NMOS transistors 7a, 7b, 7c, 7d is detected corresponds to the process of step S2 in FIG. 2.

(53) When the current value I.sub.d is greater than the target lower limit at time t4 when the waveform of the switching cycle of the NMOS transistor 7d rises, the ON-period of the NMOS transistor 7d is T.sub.a. When the current value I.sub.d is less than the target lower limit at time t5 when the waveform of the switching cycle of the NMOS transistor 7a rises, the ON-period of the NMOS transistor 7a is T.sub.b. The operation of setting the ON-period of the NMOS transistor 7a to T.sub.b at time t5 corresponds to the process of Yes in step S9 and the process of step S10.

(54) When the current value I.sub.d is greater than the target upper limit at time t6 when the waveform of the switching cycle of the NMOS transistor 7d rises, the ON-period of the NMOS transistor 7d is T.sub.c. The operation of setting the ON-period of the NMOS transistor 7d to T.sub.c at time t6 corresponds to the process of Yes in step S7 and the process of step S8. When the current value I.sub.d becomes less than the target upper limit and falls between the target upper limit and the target current I.sub.t at time t7 when the waveform of the switching cycle of the NMOS transistor 7a rises, the ON-period of the NMOS transistor 7a is T.sub.a.

(55) When the pulse signal P falls at time t8, the current value I.sub.d falls and becomes zero at time t9. This process corresponds to the process of Yes in step S12. Furthermore, each time the waveform of the switching cycle of any of the NMOS transistors 7a, 7b, 7c, 7d rises in the period from time t3 to time t4, the period from time t5+T/4 to time t6, and the period from time t7+T/4 to time t8, the ON-period of any of the NMOS transistors 7a, 7b, 7c, 7d is set to T.sub.a. This process corresponds to the process of No in step S7, the process of No in step S9, and the process of step S11.

(56) The switching frequency when the NMOS transistors 7a, 7b, 7c, 7d are switched from off to on in a predetermined order for each 90° phase timing, as in the present embodiment, is a switching frequency which is four times the switching frequency of a single NMOS transistor. Since current ripples decrease in inverse proportion to the switching frequency, the magnitude of the current ripples generated in the electrode gap 4 is a magnitude corresponding to ¼ of the magnitude of the current ripples generated in the electrode gap 4 when a single NMOS transistor is turned on and off. Therefore, current ripples can be reduced.

(57) Furthermore, according to the present embodiment, since the heat generated by the switching loss of the NMOS transistors 7a, 7b, 7c, 7d is distributed among the NMOS transistors 7a, 7b, 7c, 7d, the effect of heat generation is eliminated, and the capability of each of the plurality of switching elements can be improved.

(58) Furthermore, according to the present embodiment, since there is no need to provide a smoothing inductor having a high inductance value to reduce current ripple, there is neither a decrease in the workpiece 2 machining speed nor abnormal arc discharge, which occurs when a smoothing inductor having a high inductance value is provided.

(59) Furthermore, according to the present embodiment, since the ON-period of the NMOS transistors 7a, 7b, 7c, 7d is increased when the current value I.sub.d becomes less than the target lower limit and the ON-period of the NMOS transistors 7a, 7b, 7c, 7d is reduced when the current value I.sub.d becomes greater than the target upper limit, the current value I.sub.d can be prevented from deviating significantly from the target current.

(60) Further, according to the present embodiment, by arranging diodes 9a, 9b, 9c, 9d for regenerating current, the energy stored in the power supply device 1 for an electric discharge machine immediately after the NMOS transistors 7a, 7b, 7c, 7d are switched from on to off can be reduced

(61) The present invention is not limited to the embodiments described above, and various changes and modifications can be made. For example, the number of NMOS transistors may be two, three, five, or more, and when the number of NMOS transistors is two, the two NMOS transistors 7 are switched from off to on in a predetermined order at each phase timing of 180°. Furthermore, at least one of the diodes 8a, 8b, 8c, 8d, 9a, 9b, 9c, 9d may be omitted. Further, PMOS transistors or the like may be used as the switching elements.

REFERENCE SIGNS LIST

(62) 1 power supply device for electric discharge machine 2 workpiece 3 electrode 4 electrode gap 5 cable 6 DC power supply 7a, 7b, 7c, 7d NMOS transistor 8a, 8b, 8c, 8d, 9a, 9b, 9c, 9d diode 10 control unit 10a current value acquisition unit 10b ON-OFF control unit 11 shunt resistor 12 NC device 13 pulse generation circuit 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 connection point