Electrical circuit for testing primary internal signals of an ASIC

Abstract

An electrical circuit for testing primary internal signals of an ASIC. Only test pin is provided via which a selection can be made of a digital or analog signal to be observed. The electrical circuit includes a Schmitt trigger between the test pin and an output terminal of the electrical circuit. A test mode id activated when a switching threshold of the Schmitt trigger is exceeded. At least one sub-circuit is provided for the observation of a digital signal, having a resistor, an NMOS transistor, and an AND gate, at whose first input the digital signal is present. The resistor is between the test pin and the drain terminal of the NMOS transistor. The source terminal is connected to ground, and the gate terminal is connected to the output of the AND gate. The second input of the AND gate being connected to the output terminal of the electrical circuit.

Claims

1. An electrical circuit for testing primary internal signals of an application-specific integrated circuit (ASIC), only one test pin being provided via which a selection can be carried out of digital signals or of an analog signal to be observed, the electrical circuit comprising: a Schmitt trigger situated between the test pin and an output terminal of the electrical circuit, an activation of a test mode being provided when a switching threshold of the Schmitt trigger is exceeded; and at least one sub-circuit configured for observing a digital signal, each of the at least one sub-circuit including a resistor, an NMOS transistor, and an AND gate, wherein at a first input of the AND gate, the digital signal is present, the resistor being situated between the test pin and a drain terminal of the NMOS transistor, a source terminal of the NMOS transistor being connected to ground, a gate terminal of the NMOS transistor being connected to an output of the AND gate, and a second input of the AND gate being connected to the output terminal of the electrical circuit.

2. The electrical circuit as recited in claim 1, wherein a current measurable at the test pin is determinable based on states of all the digital signals or of a selected analog signal, and the state of all digital signals or the state of the selected analog signal being inferable using the measurable current.

3. The electrical circuit as recited in claim 1, further comprising: a further resistor situated between the test pin and ground.

4. The electrical circuit as recited in claim 3, wherein the electrical circuit includes n of the sub-circuits for n of the digital signals, the resistors of the n circuits are provided that are dimensioned corresponding to a calculation R.sub.0=2.sup.0×R, R.sub.1=2.sup.1×R, R.sub.2=2.sup.2×R, . . . , R.sub.n=2.sup.n×R, wherein R.sub.0 is the further resistor, R.sub.1 is the resistor for a first one of the sub-circuits, R.sub.2 is the resistor for a second one of the sub-circuits, and R.sub.n is the resistor for the nth one of the sub-circuits.

5. The electrical circuit as recited in claim 1, wherein the electrical circuit is also configured for observation analog signals, the electrical circuit further comprising: an operational amplifier; a circuit having a further Schmitt trigger configured to limit an input voltage at the test pin; and at least one sub-circuit provided for observing the analog signal.

6. The electrical circuit as recited in claim 5, wherein the sub-circuit provided for observing the analog signal includes: a counter having at least two D flipflops; and for each analog signal to be observed, a respective decoder having a respective AND gate and a respective transmission gate.

7. The electrical circuit as recited in claim 6, wherein a first input of the respective AND gate is connected to a non-inverting output or to an inverting output of a first of the at least two D flipflops, a second input of the respective AND gate is connected to a non-inverting output or to an inverting output of a second of the at least two D flipflops, and an output of the respective AND gate is connected to an input or controlling the respective transmission gate.

8. The electrical circuit as recited in claim 7, further comprising: an OR gate, a first input of the OR gate being connected to the non-inverting output of the first of the at least two D flipflops, a second input of the OR gate is connected to the non-inverting output of the second of the at least two D flipflops, and an output of the OR gate is connected to an input for controlling the operational amplifier.

9. The electrical circuit as recited in claim 7, further comprising: a further AND gate, a first input of the further AND gate is connected to the inverting output of the first of the at least two D flipflops, a second input of the further AND gate is connected to the inverting output of the second of the at least two D flipflops, a third input of the further AND gate is connected to an output of the Schmitt trigger, and an output of the further AND gate is connected to a third input of the respective AND gate which is situated in the sub-circuit configured for observing a digital signal.

10. The electrical circuit as recited in claim 5, wherein an input of the circuit having the further Schmitt trigger for limiting the input voltage at the test pin is situated between two resistors of a voltage divider situated between the test pin of the electrical circuit and ground, and an output of the circuit is connected to a clock signal input of a D flipflop.

11. The electrical circuit as recited in claim 5, wherein the output terminal of the electrical circuit is inverted by an inverter, and is connected to a clear input of a D flipflop.

12. The electrical circuit as recited in claim 5, further comprising: two comparators for selecting the digital or analog signals to be measured via the test pin, and for activating different test modes.

13. The electrical circuit as recited in claim 12, wherein a reference voltage is present at a positive input of each of the comparators, and a negative input of each of the comparators is connected to the test pin.

14. The electrical circuit as recited in claim 13, wherein a further circuit, made up of a transistor and a resistor and a capacitor, is provided between the negative input of each of the comparators and the test pin of the electrical circuit.

15. The electrical circuit as recited in claim 12, further comprising: a D flipflop having a clock signal input connected to the output of the further Schmitt trigger and having a non-inverting output is connected to an input for controlling one of the comparators.

16. The electrical circuit as recited in claim 5, further comprising: two D flipflops for provision of output signals.

17. The electrical circuit as recited in claim 5, further comprising: a shift register made up of D flipflops for selecting signals to be tested and for setting a test mode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments of the present invention are explained in more detail on the basis of the figures and the description below.

(2) FIG. 1 shows an exemplary embodiment of an electrical circuit for testing digital signals in accordance with the present invention.

(3) FIG. 2 shows an exemplary embodiment of an electrical circuit for testing digital and analog signals in accordance with the present invention.

(4) FIG. 3 shows an exemplary embodiment of an electrical circuit for testing digital and analog signals, with the possibility of activating different testing modes in accordance with the present invention.

(5) FIG. 4 shows a signal curve of the above-named exemplary embodiment of an electrical circuit for testing digital and analog signals, with the possibility for activating different test modes, according to FIG. 3, in accordance with the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(6) In the description herein of the exemplary embodiments of the present invention, the voltages related to ground GND at terminals or networks are designated, for example, U.sub.TEST for the terminal TEST, or U.sub.VDD for the network VDD. In contrast, currents that flow into terminals are designated for example I.sub.TEST for the ASIC terminal TEST.

(7) FIG. 1 shows an exemplary embodiment of an electrical circuit for testing digital signals that, according to a first circuit-based realization, is suitable only for testing internal digital signals. Via the ASIC terminal TEST, a change to the test mode can be made when a voltage is applied that is greater than the switching threshold of Schmitt trigger SMT.sub.1. This is indicated by a high level at output terminal TM of the circuit that is connected to the output of Schmitt trigger SMT.sub.1. Schmitt trigger SMT.sub.1 and the AND gates X.sub.1 through X.sub.n are supplied with a supply voltage U.sub.VDD (not shown in FIG. 1). The switching thresholds of the Schmitt trigger are typically at ⅔ or ⅓ of the supply voltage U.sub.VDD.

(8) If the voltage U.sub.TEST at the ASIC terminal TEST is increased from 0V up to the operating voltage of U.sub.VDD, then the output of Schmitt trigger SMT.sub.1 remains at a low level LOW until its input voltage, or the voltage U.sub.TEST at ASIC terminal TEST, is above the switching threshold of, typically, ⅔×U.sub.VDD. During this time, it is possible to determine the value of the resistor R.sub.0=2.sup.0×R using Ohm's law, by determining the current I.sub.TEST that flows in ASIC terminal TEST at the voltage U.sub.TEST applied to this terminal. The resistance results as R.sub.0=R=U.sub.TEST/I.sub.TEST.

(9) As soon as the signal at the output terminal TM=HIGH, the internal digital signals D.sub.1 through D.sub.n of the ASIC determine the additional current that flows into ASIC terminal TEST, in that transistors M.sub.1 through M.sub.n connect resistors R.sub.1 through R.sub.n to ground GND. If the values of the resistances R.sub.1 through R.sub.n increase as in FIG. 1, for example, with R.sub.1=2.sup.1×R, R.sub.2=2.sup.2×R, . . . R.sub.n=2.sub.n×R, then by measuring the overall current that flows into the ASIC terminal TEST, and taking into account R.sub.0=R, it can be ascertained which of the internal digital signals D.sub.1 through D.sub.n has a HIGH or LOW level, because during TM=HIGH, the following holds for the current I.sub.TEST measurable at ASIC terminal TEST: I.sub.TEST=U.sub.TESTR ×[1/2.sup.0+1/(D.sub.1×2.sup.1)+1/(D.sub.2×2.sup.2)+ . . . +1/(D.sub.n×2n)], where in this equation, for D.sub.1 . . . D.sub.n a 1 or a 0 is to be used for a logical HIGH or LOW level respectively. Because the variables U.sub.TEST and R are known, in this way the states of the digital signals D.sub.1 through D.sub.n can be determined via the measured current I.sub.TEST.

(10) If the voltage at the ASIC terminal TEST is reduced from U.sub.VDD to 0 V, then the output of Schmitt trigger SMT.sub.1 remains at a HIGH level until its input voltage, or the voltage at ASIC terminal TEST, is below the switching threshold of, typically, ⅓×U.sub.VDD. TM is then=LOW, and the internal digital signals D.sub.1 through D.sub.n no longer have any influence on the overall current flowing into ASIC terminal TEST.

(11) FIG. 2 shows an exemplary embodiment of an electrical circuit for testing digital and analog signals, in which the circuit shown in FIG. 1 has been expanded to include testability of internal analog voltage signals, this being shown in FIG. 2 as an example for three digital signals D.sub.1 through D.sub.3 and three analog signals A.sub.1 through A.sub.3. The current flowing into ASIC terminal TEST can now be influenced by the voltage UA.sub.1 through UA.sub.3 of one of the analog signals A.sub.l through A.sub.3, in that one of these signals is conducted via one of the transmission gates TG.sub.1 through TG.sub.3 to the positive input of operational amplifier OP.sub.1, which, with the aid of transistor M.sub.4, is operating as an impedance converter. Here, operational amplifier OP.sub.1 controls the gate of transistor M.sub.4 in such a way that the input difference voltage between its positive and its negative input is 0 V. The voltage U.sub.A at the positive input of operational amplifier OP.sub.1 thus corresponds to the voltage drop UR.sub.4 across the resistor R.sub.4=R. Correspondingly, through resistor R.sub.4 there flows a current IR.sub.4=U.sub.A/R that is proportional to the voltage U.sub.A1 through U.sub.A3 of the selected analog voltage signal A.sub.1 through A.sub.3.

(12) Which of the internal analog signals A.sub.1 through A.sub.3 is acquired by measurement at the ASIC terminal TEST is determined by the counter, made up of the D flipflops made up of FF.sub.1 and FF.sub.2, and by the decoder made up of AND gates X.sub.5 through X.sub.7. Depending on the counter state (01, 10, or 11), one of the AND gates has a HIGH level at its output, and thus controls the EN (enable) input of the corresponding transmission gate TG.sub.1 through TG.sub.3 so that this gate produces a low-ohmic connection between its two other terminals. The transmission gates whose EN input are at a LOW level are correspondingly high-ohmic.

(13) If the counter state is not 00, then the output of OR gate X.sub.8 is HIGH, and operational amplifier OP.sub.1 operates in the manner described previously. Simultaneously, the output of AND gate X.sub.4, and thus also the outputs of AND gates X.sub.1 through X.sub.3, are switched to LOW, so that none of the digital signals D.sub.1 through D.sub.3 can influence the current flowing into ASIC terminal TEST. The current flowing into ASIC terminal TEST results as I.sub.TEST=U.sub.TEST/R+U.sub.A/R, where U.sub.A corresponds to a voltage U.sub.A1 through U.sub.A3, corresponding to the counter state. Because the variables U.sub.TEST and R are known, in this way the voltage of the selected internal analog signal can be determined via the measured current I.sub.TEST.

(14) If, in contrast, the counter state is 00, then the output of OR gate X.sub.8 is LOW, and operational amplifier OP.sub.1 is deactivated. The output of operational amplifier OP.sub.1 used here is then at 0 V. Alternatively or in addition, the positive input of operational amplifier OP.sub.1 could be connected by a transistor to ground GND (not shown in FIG. 2). At counter state 00, the output of AND gate X.sub.4 is also at HIGH, so that digital signals D.sub.1 through D.sub.3 can influence the current flowing into ASIC terminal TEST, as described for FIG. 1.

(15) The counter state is incremented upward with each rising edge of the output signal of Schmitt trigger SMT.sub.2. When counter state 11 has been reached, then it is set back to 00 with the next rising edge at the CLK input of D flipflop FF.sub.2. When TM=LOW it is also set to 00, because the HIGH level of inverter X.sub.9 resets the D flipflops FF.sub.1 and FF.sub.2 via their CLR (clear) inputs (the outputs Q of the D flipflops are then LOW).

(16) The output of Schmitt trigger SMT.sub.2 changes from LOW to HIGH when its input voltage increases above the switching threshold of, typically, 2/3×U.sub.VDD. It changes from HIGH to LOW when its input voltage decreases below the switching threshold of, typically, 1/3×U.sub.VDD. The input of Schmitt trigger SMT.sub.2 is connected to the ASIC test pin TEST via the transistors M.sub.6 and M.sub.9, as well as the voltage divider formed from R.sub.7 and R.sub.8, where R.sub.7=R.sub.8=R/2. So that the transistor M.sub.6 can conduct, the voltage at its source terminal has to still be above the supply voltage U.sub.VDD by the threshold voltage U.sub.THP of a PMOS transistor. This is the case in the circuit according to FIG. 2 when U.sub.TEST≥2×(U.sub.VDD+U.sub.THP). If U.sub.TEST is smaller, then M.sub.6 blocks, and the input of Schmitt trigger SMT.sub.2 is connected to GND by R.sub.6. Accordingly, the counter is incremented upward with each voltage pulse whose amplitude is greater than 2×(U.sub.VDD+U.sub.THP).

(17) Transistors M.sub.5 and M.sub.9 are used to protect Schmitt triggers SMT.sub.1 and SMT.sub.2. They limit the input voltage in each case to a maximum of U.sub.VDD-U.sub.THN, where U.sub.THN is the threshold voltage of an NMOS transistor. The resistor R.sub.5 and the transistors M.sub.7 and M.sub.8, on the other hand, limit the source gate voltage of M.sub.6. If the voltage at ASIC terminal TEST is large enough that the drain body diode of M.sub.7 conducts and a channel can form in M.sub.8, then the gate potential of M.sub.6 is increased, so that the source gate voltage of M.sub.6 cannot become substantially greater than the sum of the threshold voltage of a PMOS transistor and the flux voltage of a drain body diode.

(18) The exemplary embodiment according to FIG. 2 is limited to three analog signals A.sub.1, A.sub.2, A.sub.3. However, in generaly, any desired number of analog signals is observable through the addition of further transmission gates, D flipflops, and through the expansion of the 1-of-m decoder. Accordingly, if more than three internal analog signals are to be observable, then the 1-of-m decoder has to be expanded as stated above.

(19) Correspondingly, given more than three analog signals and more than two D flipflops, the non-inverting outputs of the further D flipflops are to be connected to additional inputs of the OR gate, and the inverted outputs of the additional D flipflops are to be connected to additional inputs of the AND gate.

(20) FIG. 3 shows an exemplary embodiment of an electrical circuit for testing digital and analog signals, with the possibility of activating different test modes, in which the circuit shown in FIG. 2 has been correspondingly expanded. Through such a circuit it becomes possible, via the ASIC terminal TEST, to activate different test modes in addition to the testability of internal digital and analog signals.

(21) It is to be noted that the approaches shown in FIG. 2, in which response thresholds having different levels are created for a plurality of Schmitt triggers, could be further pursued. However, because the internal supply voltage U.sub.VDD can also change (in particular can become lower) during the test, the voltage U.sub.TEST at the ASIC terminal TEST would then have to be entrained ratiometrically to the internal supply voltage U.sub.VDD, which sometimes may not be possible because the internal supply voltage may not be measurable via a separate ASIC terminal.

(22) It may therefore be advantageous to use, in addition to the Schmitt trigger SMT.sub.1 used to activate the test mode, an additional Schmitt trigger having a very high response threshold, so that even a significant reduction in the internal supply voltage U.sub.VDD cannot have the result that this Schmitt trigger switches undesirably when there is a voltage U.sub.TEST that remains constant at ASIC terminal TEST and a strongly reduced internal supply voltage U.sub.VDD. The use of a plurality of Schmitt triggers having very high response thresholds is nonetheless possible, but sometimes demands a very high voltage strength of the components that are internally connected to the ASIC terminal TEST in the ASIC.

(23) In the circuit shown in FIG. 3, therefore, in addition to Schmitt trigger SMT.sub.1 for activating the test mode, a further Schmitt trigger SMT.sub.2 having a very high response threshold is used. This circuit also realizes, as an example, the testability of three digital signals D.sub.1 through D.sub.3 and three analog signals A.sub.1 through A.sub.3. In addition, four different test modes can be activated.

(24) The output of the Schmitt trigger SMT.sub.2 changes from LOW to HIGH when its input voltage increases above the switching threshold of, typically, 2/3×U.sub.VDD. It changes from HIGH to LOW when its input voltage decreases below the switching threshold of, typically, ⅓×U.sub.VDD. The input of the Schmitt trigger SMT.sub.2 is connected to the ASIC test pin TEST via the transistors M.sub.6 and M.sub.9 and the voltage divider made up of R.sub.7 through R.sub.9, where R.sub.7=2R/3 and R.sub.8=R/12 and R9=R/4. For transistor M.sub.6 to be able to conduct, the voltage at its source terminal must be greater than the supply voltage U.sub.VDD by the threshold voltage U.sub.THP of a PMOS transistor. This is the case in the circuit according to FIG. 3 when U.sub.TEST≥3×(U.sub.VDD+U.sub.THP). If U.sub.TEST is smaller, then M.sub.6 blocks, and the input of Schmitt trigger SMT.sub.2 is connected to GND by R.sub.6. When TM=LOW, all D flipflops FF.sub.1 through FF.sub.6 are set to Q=LOW, because the HIGH level of the inverter X.sub.9 resets the D flipflops FF.sub.1 through FF.sub.6 via their CLR (clear) inputs (the outputs Q of the D flipflops are then LOW).

(25) If the output of the D flipflop (network EN CMP) is LOW, then the comparators CMP.sub.1 and CMP.sub.2 are deactivated. The outputs of the comparators used here are then LOW. If the output of the D flipflop is HIGH, then the comparators CMP.sub.1 and CMP.sub.2 are activated. Using the comparators CMP.sub.1 and CMP.sub.2, through variation of the voltage at ASIC test pin TEST on the one hand it is possible to select whether the digital signals D.sub.1 through D.sub.3 or one of the analog signals A.sub.1 through A.sub.3 are to be acquired by measurement via the ASIC terminal TEST. On the other hand, it is possible to activate different test modes. Based on the possibility of deactivating the comparators CMP.sub.1 and CMP.sub.2, the internal signals D.sub.1 through D.sub.3 or A.sub.1 through A.sub.3 can also be tested if the operating voltage U.sub.VDD or the reference voltage U.sub.VREF have not assumed their target values. In this way, for example via the ASIC terminal TEST, the internal supply voltage U.sub.VDD starting from which the internal reference voltage U.sub.VREF reaches its target value, or an internal power-on-reset signal changes its state, can be acquired by measurement without there being the risk that one of the comparators CMP.sub.1 and CMP.sub.2 could undesirably switch.

(26) The activated comparators CMP.sub.1 and CMP.sub.2 supply HIGH levels when the voltage at their respective negative input is smaller than the reference voltage U.sub.VREF. The resistors R.sub.10 and R.sub.11, and the capacitors C.sub.1 and C.sub.2, act as filters and delay elements. The transistors M.sub.10 and M.sub.11 protect the comparator inputs from excessively high voltages at their inputs by limiting them to a maximum of U.sub.VDD-U.sub.THN where U.sub.THN is the threshold voltage of an NMOS transistor. Taking into account the voltage divider made up of resistors R.sub.7 through R.sub.9, the comparator outputs of CMP.sub.1 or CMP.sub.2 are correspondingly at HIGH, given a voltage U.sub.TEST>3×U.sub.VREF or, respectively, U.sub.TEST>4×U.sub.VREF; otherwise the respective comparator output is at LOW.

(27) In the exemplary embodiments according to FIG. 2 and FIG. 3, both the flipflops FF.sub.1 and FF.sub.2 and the flipflops FF.sub.4, FF.sub.5, and FF.sub.6 are reset. The flipflops FF.sub.1 and FF.sub.2 here either select all digital signals simultaneously (counter state 00) or one of the analog signals (counter state 01, 10, 11). The flipflops FF.sub.5 and FF.sub.6, in contrast, are provided for the selection of a test mode.

(28) In FIG. 4, the signal curve is shown for the above-named exemplary embodiment of an electrical circuit for testing digital and analog signals, with the possibility of activating different test modes; here, for the representation of the time signal curves, as an example a supply voltage of U.sub.VDD=5 V and a reference voltage of U.sub.VREF=1V are assumed, and times 1 through 7 are identified by circled numerals.

(29) As is shown in FIG. 4, in part higher voltages occur at the test pin than can be processed by the following Schmitt trigger, for example up to 20 V. The circuit formed from components M.sub.6, M.sub.7, M.sub.6, M.sub.9, R.sub.5, and R.sub.6, shown in FIG. 2, protects the input of Schmitt trigger SMT.sub.2 from these high voltages.

(30) At time 1, the voltage U.sub.TEST changes its value from 0 V to 5 V. Correspondingly, the output of Schmitt trigger SMT.sub.1 is at HIGH, and the output of inverter X.sub.9 is at LOW (CLR_FF=LOW).

(31) At time 2, the voltage U.sub.TEST briefly changes its value from 5 V to 20 V (and subsequently back to 5 V). Correspondingly, the output of Schmitt trigger SMT.sub.2 is (briefly) HIGH, and the level of D flipflop FF.sub.3 changes from LOW to HIGH. Comparators CMP.sub.1 and CMP.sub.2 are thereby activated.

(32) At time 3, voltage U.sub.TEST changes its value from 5 V to 2.5 V. Correspondingly, the output of comparator CMP.sub.2 changes, with a time delay, from LOW to HIGH (CMPB=HIGH), and the output of comparator CMP.sub.1 also changes, with a time delay relative to CMP.sub.2, from LOW to HIGH (CMPA=HIGH). Correspondingly, the output of D flipflop FF4 changes from LOW to HIGH (CMPA_Q=HIGH), and the output of OR gate X.sub.15 changes from LOW to HIGH (CMPB_H=HIGH).

(33) At time 4, the voltage U.sub.TEST changes its value from 2.5 V to 5 V. Correspondingly, the output of comparator CMP.sub.1 changes, with a time delay, from HIGH to LOW (CMPA=LOW), and the output of comparator CMP.sub.2 also changes, with a time delay relative to CMP.sub.1, from HIGH to LOW (CMPB=LOW). On the basis of the delay element, made up of transistors M.sub.12 and M.sub.13, resistor R.sub.12, and capacitor C.sub.3, the output of OR gate X.sub.15 changes, with a time delay relative to that of comparator CMP.sub.2, from HIGH to LOW (CMPB_H=LOW). At CMPB_H=LOW, the output of OR gate X.sub.12 is set to HIGH, and that of D flipflop FF.sub.4 is set to LOW, because the HIGH signal of X.sub.12 is at its CLR (clear) input. While CMPB is already LOW and CMPB_H is still HIGH, the output of AND gate X.sub.13 is briefly HIGH (CMPB_P briefly HIGH). Because the output of D flipflop FF.sub.4 was set to HIGH at time 3, at the output of AND gate X.sub.11 there likewise occurs a short HIGH pulse that increments upward the counter made up of D flipflops FF.sub.5 and FF.sub.6, thus changing over from test mode 00 to test mode 01. The corresponding output signals MD.sub.0 and MD.sub.1 can be used in the ASIC to create particular test conditions. On the basis of the counter, made up in the present case of D flipflops FF.sub.5 and FF.sub.6, which is also shown in FIG. 3, a shift register could also be used to set a test mode, where the difference between a 0 and a 1 could be realized using short and long pulses.

(34) At time 5, the voltage U.sub.TEST changes its value from 5 V to 3.5 V. Correspondingly, (only) the output of comparator CMP.sub.2 changes, with a time delay, from LOW to HIGH (CMPB=HIGH). Correspondingly, the output of OR gate X.sub.15 changes from LOW to HIGH (CMPB_H=HIGH).

(35) At time 6, voltage U.sub.TEST changes its value from 3.5 V to 5 V. Correspondingly, the output of comparator CMP.sub.2 changes, with a time delay, from HIGH to LOW (CMPB=LOW). Due to the delay element (M.sub.12, M.sub.13, R.sub.12, C.sub.3) , the output of OR gate X.sub.15 changes, with a time delay relative to that of comparator CMP.sub.2, from HIGH to LOW (CMPB_H=LOW). While CMPB is already LOW and CMPB_H is still HIGH, the output of AND gate X.sub.13 is briefly HIGH (CMPB_P briefly HIGH). Because the output of D flipflop FF.sub.4 was set to LOW at time 4, at the output of AND gate X.sub.10 there also arises a brief HIGH pulse that increments the counter, made up of D flipflops FF.sub.1 and FF.sub.2, upward from 00 to 01, and thus, as described correspondingly for FIG. 2, switches the analog signal A.sub.1 to the operational amplifier OP.sub.1 via the transmission gate TG.sub.2, so that this amplifier becomes capable of being acquired by measurement via the ASIC test pin TEST.

(36) At time 7, the voltage U.sub.TEST briefly changes its value from 5 V to 20 V (and subsequently back to 5 V). Correspondingly, the output of Schmitt trigger SMT.sub.2 is (briefly) HIGH, and that of D flipflop FF.sub.3 changes from HIGH to LOW. Comparators CMP.sub.1 and CMP.sub.2 are thereby deactivated. Now, for example via the ASIC terminal TEST, the internal supply voltage U.sub.VDD starting from which the internal reference voltage U.sub.VREF reaches its target value, or an internal power-on-reset signal changes its state, can be acquired by measurement without there being a risk that one of the comparators could switch undesirably.

(37) In the further time period after time 7, in FIG. 4 it is shown that a change of the voltage U.sub.TEST from 5 V to 2.5 V no longer has any influence on comparators CMP.sub.1 and CMP.sub.2, and thus also no longer has any influence on the state of the D flipflops. If the voltage U.sub.TEST is set to 0 V, then the test mode is exited, and all D flipflops are reset.