METHOD FOR MONITORING A FIRST PROCESSOR OF A SENSOR MODULE BY MEANS OF A SECOND PROCESSOR

Abstract

The present disclosure relates to a method for monitoring a first processor using a second processor in a field device, comprising the following method steps: calculating verification data on the basis of specified input data using a test algorithm on an external computing unit storing the input data and the verification data computed by the test algorithm; transferring the specified input data stored in the sensor module and the verification data; transferring the specified input data; executing the test algorithm on the first processor; making the calculated output data available on the second processor; checking the output data with the verification data using the second processor and, if the output data do not correspond to the verification data, establishing a malfunction.

Claims

1-11. (canceled)

12. A method for monitoring a first digital processor integrated into a sensor module of a field device of automation technology and having a first set of machine commands on which, in order to calculate a measured value on the basis of supplied raw measured values, an algorithm is executed using a second digital processor integrated into a main electronics module of the field device, said method comprising the following method steps: calculating verification data on the basis of specified input data using a test algorithm on an external computing unit that is independent of the field device, wherein the test algorithm is divided into at least one initial section and an end section, wherein the initial section and the end section comprise at least one, preferably all, opcodes of the first set of machine commands used while executing the algorithm on the first processor; storing the input data specified for calculating the verification data and the verification data computed using the algorithm in the sensor module of the field device; transmitting the specified input data stored in the sensor module and the verification data to the main electronics module; transmitting the specified input data from the main electronics module to the sensor module during measuring operation of the field device; executing the test algorithm on the first digital processor of the sensor module in such a way that output data are calculated on the basis of the specified input data transmitted from the main electronics module, wherein the algorithm between the initial section and the end section is executed such that, after the test algorithm has been executed, it can be checked on the basis of the verification data whether the algorithm has been run through completely; making the output data calculated using the first digital processor available in the main electronics module; checking the output data with the verification data, made available by the sensor module, using the second digital processor of the main electronics module and, if the output data do not correspond to the verification data, determining a malfunction.

13. The method according to claim 12, wherein the method steps of transmitting the specified input data from the main electronics module to the sensor module during measuring operation of the field device, the executing step, the making step, and the checking step are carried out cyclically during measuring operation of the field device.

14. The method according to claim 12, wherein the method step of transmitting the specified input data stored in the sensor module and the verification data to the main electronics module is carried out during a system start-up of the field device.

15. The method according to claim 12, wherein the method step of storing the input data specified for calculating the verification data and the verification data computed using the test algorithm in the sensor module of the field device is carried out during manufacture of the sensor module.

16. The method according to claim 12, wherein, during actual measuring operation of the field device, raw measured values are cyclically fed to the first digital processor, and the raw measured values during actual measuring operation are cyclically processed further by the first processor using the algorithm.

17. The method according to claim 12, wherein, during actual measuring operation of the field device, the raw measured values are fed to the first digital processor and are processed further using the algorithm at a higher clock rate than that at which the test algorithm is executed with the specified input data.

18. The method according to claim 12, wherein, after the method steps of executing, making and checking are carried out, are carried out, when carried out again, they are carried out with other input data which were previously transmitted from the sensor module to the main electronics module.

19. The method according to claim 12, wherein the algorithm is divided into several sections, and, when executed, the several sections of the algorithm between the initial section and the end section are executed.

20. The method according to claim 19, wherein the test algorithm is also divided into several sections, and, when executed, the sections of the algorithm and of the test algorithm are executed in an alternating manner.

21. The method according to claim 12, wherein the verification data are calculated on a manufacturing computer during manufacture of the sensor module by the manufacturer of the sensor module.

22. The method according to claim 21, wherein the verification data are calculated on the manufacturing computer using a numerical calculation tool.

Description

[0025] The invention is explained in more detail on the basis of the following drawings. The following are shown:

[0026] FIG. 1: a schematic block diagram of a field device having an electronic field device circuit known from the prior art;

[0027] FIG. 2: a schematic block diagram of an embodiment of a field device which comprises an electronic field device circuit configured with the method according to the invention;

[0028] FIG. 3: a schematic representation of the algorithm which, during actual measuring operation, runs on the first processor of the sensor module—for example, for temperature compensation;

[0029] FIG. 4: a schematic representation of the test algorithm which, according to the invention, runs on the first processor of the sensor module for monitoring the first processor; and

[0030] FIG. 5: a schematic representation of an advantageous variant of the test algorithm which, according to the invention, runs on the first processor of the sensor module for monitoring the first processor.

[0031] The field device 100 shown in FIG. 1 comprises an electronic field device circuit, which is composed of a sensor module 10 and a main electronics module 20, and a complementarily designed, digital communications interface 16, 24. The sensor module and the main electronics 20 are designed in such a way that various sensor modules can be connected to the main electronics 20 or are compatible with one another, depending upon the physical variable to be recorded. In this case, the main electronics 20 are always of the same design, and only the sensor module has a different design, depending upon which physical variable is to be recorded, i.e., for example, whether a pressure or a fill-level variable is to be recorded.

[0032] The sensor module 10 comprises a transducer element 11, e.g., a capacitive or resistive pressure transducer element, and sensor electronics 12, wherein raw measured values in the form of a primary signal are fed from the transducer element to an analog sensor input 14 of the sensor electronics 12. These raw measured values are digitized by the sensor electronics 12 and subsequently processed or processed further into corresponding measured values by a first digital processor 1, e.g., a digital signal processor (DSP), by means of an algorithm Comp running on said processor 1. Typically, a temperature compensation of the raw measured value takes place by means of the algorithm Comp running on the digital signal processor 1. FIG. 3 illustrates the running of the algorithm on the first processor on the basis of which the raw measured values are processed further to form a compensated for measured value. The raw measured value can be processed, for example, at an interval of from a few milliseconds (ms) up to a few tens of milliseconds by the first processor. The processed measured value is made available to the main electronics module 20 via a first digital communications interface 16. In order to achieve increased flexibility during manufacture of the field device, the sensor module is designed as an exchangeable module. As a result, different sensor modules can be combined with the main electronics module during manufacture in order to design the field device specifically for a measurement task.

[0033] In the embodiment shown, the main electronics module 20 comprises a logic unit, a current regulator 32, a HART modem 34, and a communications interface—for example, a controlled current source 36.

[0034] The logic unit 22 comprises a second digital processor, e.g., a microprocessor, a second digital communications interface 24, which communicates with the first digital communications interface 16. The digital measured value is transmitted via this digital communications interface, for example, during normal measuring operation, and the logic unit 22 prompts the current regulator 32 via a third digital communications interface 26 to regulate the controlled current source 36 in such a way that it provides an analog current signal which represents the digital measured value or a measured variable derived therefrom.

[0035] Furthermore, the logic unit 22 comprises a fourth digital communications interface 30, via which the HART modem 34 is activated in order to modulate digital information, e.g., status information, onto the analog current signal.

[0036] The electronic circuits known from the prior art are configured in such a way that the algorithm Comp is executed on the first processor 1 with at least partial use of the machine commands available for the first processor 1.

[0037] In order to meet the SIL measures mentioned at the outset, the algorithm Comp is also installed on the second processor 2. The installation takes place according to the prior art when the field device is started up or in an initialization phase of the field device before it switches to actual measuring operation. In the process, the algorithm is transmitted via the internal communications interface 16 and 24 from the sensor module to the main electronics module. Both the algorithm on the first and on the second processor are then executed in parallel at runtime, i.e., during actual measuring operation of the field device.

[0038] The algorithm calculates the output-side verification data V on the second processor using the machine commands of the second processor 2. For this purpose, the input data E are transmitted from the sensor module to the main module—for example, via the communications interface 16 and 24. The verification data V obtained by the second processor 2 are subsequently compared, according to the prior art, with the output data A obtained by the first processor 1 in order to allow for a check of the first processor 1. In the event that the two results do not match, an error is determined and signaled. The redundant execution of the algorithm both on the first and on the second processor achieves SIL Level 2.

[0039] FIG. 2 shows a schematic block diagram of an embodiment of a field device according to the invention. The field device shown here has the same components as the field device shown in FIG. 1. Identical components are designated by the same reference signs.

[0040] In the embodiment shown in FIG. 2, the sensor module of the field device additionally has a non-volatile memory in which a table (look-up table) is stored. Input data and verification data are saved or stored in the table. According to the invention, the input data and the verification data are calculated externally, i.e., outside the field device—for example, during manufacture by means of a corresponding piece of software on a computing unit. A numerical calculation tool or software such as MATLAB or similar software, for example, can be used for the calculation. In this case, verification data associated with specified input data are calculated. Subsequently, the input data and the verification data are stored in the memory of the sensor module during manufacture of the sensor module, such that said data are available later during actual measuring operation of the field device.

[0041] Therefore, the entire algorithm no longer has to be transmitted via the internal communications interface 16 and 24 in order to fulfill the SIL measures mentioned at the outset, but, rather, only the input and verification data stored in the memory. The transmission of the input and verification data from the sensor module to the main electronics module preferably takes place during a system start-up of the field device before the field device commences actual measuring operation.

[0042] The execution of the test algorithm is initiated by the second processor of the main electronics module. This can take place, for example, cyclically during actual measuring operation. This means that the second processor during actual measuring operation starts executing the test algorithm on the first processor, during which the algorithm is executed on the first processor of the sensor module in order to compensate for the raw measured value. For this purpose, the second processor first transmits the input data, which have been made available in the main electronics module during system start-up, to the sensor module.

[0043] In the next step, initiated by the second processor, the test algorithm is executed on the first processor. For this purpose, output data are calculated by means of the previously transmitted input data. The test algorithm is designed in such a way that all machine commands or all opcodes required for executing the algorithm Comp are used at least once by the test algorithm. The test algorithm is a so-called opcode test, during which at least parts of the opcodes of the first processor are tested.

[0044] As shown by way of example in FIG. 4, the test algorithm can be divided at least into an initial and an end section, OPCT1 and OPCT2. The first processor 1 is further configured such that at least part of the algorithm Comp, and preferably the entire algorithm Comp between the initial section OPCT1 and the end section OPCT2, is executed.

[0045] Alternatively, the test algorithm opcode can be divided into a plurality of sections C1 . . . Cn, and the algorithm Comp can be divided into a plurality of sections S1 . . . Sn, and the first processor can be configured such that, during execution, part of the test algorithm and then part of the actual algorithm are executed alternately until all parts of the algorithm Comp and all parts of the test algorithm have been run through. FIG. 5 illustrates such a variant, in which output data are calculated by the first processor 1 by means of the previously transmitted input data.

[0046] In the next step, the output data calculated by the first processor 1 are made available in the main electronics module, such that the second processor has access to said data. This can be done, for example, by transmitting the output data via the internal communications interface 16 and 24 from the first to the second processor. For this purpose, the output data can first be kept in an internal register 18 of the first processor 1, such that the second processor can access said data via the communications interface 16 and 24.

[0047] Subsequently, the second processor checks whether the available output data correspond to the verification data transmitted from the sensor module to the main electronics module, preferably during the system start-up of the field device. In the event that a deviation of the data is established, an error message is, furthermore, output by the second processor.

LIST OF REFERENCE SIGNS

[0048] 100 Field device [0049] 1 First digital processor [0050] 2 Second digital processor [0051] 10 Sensor module [0052] 11 Transducer element [0053] 12 Sensor electronics [0054] 14 Communications interface [0055] 16 Communications interface [0056] 18 Internal register of the first processor [0057] 20 Main electronics module [0058] 22 Logic unit [0059] 24 Communications interface [0060] 26 Communications interface [0061] 30 Communications interface [0062] 32 Current regulator [0063] 34 HART modem [0064] 36 Controlled power source [0065] E Input data [0066] A Output data [0067] V Verification data [0068] OPCT1 Initial section of the test algorithm [0069] OPCT2 End section of the test algorithm [0070] C1 . . . Cn Individual sections of the test algorithm [0071] Comp Algorithm for further processing the raw measured value, especially for temperature compensation and/or linearization