Gallium Oxide Planar MOS-Schottky Rectifier

Abstract

Ga.sub.2O.sub.3-based rectifier structure and method of forming the same. A Schottky diode structure is combined with a metal-oxide-semiconductor structure to provide a metal oxide-type Schottky barrier diode (MOSSBD) rectifier that includes an n-type β-Ga.sub.2O.sub.3 drift layer on a β-Ga.sub.2O.sub.3 substrate, the drift layer having a plurality of spaced-apart semi-insulating regions formed by in-situ ion implantation of acceptor species at predefined spatially defined regions of the drift layer to create alternating areas of n-type and semi-insulating regions within the n-type drift layer. The thus-formed structure achieves high forward bias current with low specific on-resistance when the anode is biased with positive voltage and low leakage current when the device is operated under reverse bias.

Claims

1. A rectifier having high forward bias current with low specific on-resistance, comprising: a β-Ga.sub.2O.sub.3 n-type drift layer on a β-Ga.sub.2O.sub.3 substrate; and a plurality of predetermined spatially defined semi-insulating regions comprising trenches of ion-implanted acceptor species formed in the β-Ga.sub.2O.sub.3 n-type drift layer; wherein unimplanted regions of the β-Ga.sub.2O.sub.3 n-type drift layer and the ion-implanted regions form alternating n-type and semi-insulating regions in the β-Ga.sub.2O.sub.3 drift layer; and wherein the acceptor species and a depth of the trenches of implanted acceptor species are configured to produce a predetermined electronic response in the rectifier.

2. The rectifier according to claim 1, wherein the rectifier is a planar metal oxide-type Schottky barrier diode (P-MOSSBD) rectifier having low on-resistance in forward bias and a low reverse current and high breakdown field in reverse bias.

3. The rectifier according to claim 1, wherein the acceptor species comprise N, Mg, Co, Fe, Be, Ca, Sr, Zn, or Cd.

4. The rectifier according to claim 1, wherein the β-Ga.sub.2O.sub.3 n-type drift layer is n-doped with Si or Ge.

5. The rectifier according to claim 1, wherein the trenches of implanted acceptor species are uniformly spaced.

6. The rectifier according to claim 1, wherein the trenches of implanted acceptor species are non-uniformly spaced.

7. A rectifier having high forward bias current with low specific on-resistance, comprising: a β-Ga.sub.2O.sub.3 n-type drift layer on a β-Ga.sub.2O.sub.3 substrate; a semi-insulating β-Ga.sub.2O.sub.3 layer formed on the drift layer; a plurality of predetermined spatially defined N-type regions comprising donor ion-implanted species formed in the semi-insulating β-Ga.sub.2O.sub.3 layer; wherein unimplanted regions of the semi-insulating β-Ga.sub.2O.sub.3 layer and the donor ion-implanted regions form alternating semi-insulating and N-type β-Ga.sub.2O.sub.3 regions; wherein the species and a depth of the trenches of implanted donor species are configured to produce a predetermined electronic response in the rectifier.

8. The rectifier according to claim 7, wherein the rectifier is a planar metal oxide-type Schottky barrier diode (P-MOSSBD) rectifier having low on-resistance in forward bias and a low reverse current and high breakdown field in reverse bias.

9. The rectifier according to claim 7, wherein the donor species comprise Si, Ge, or Sn.

10. A method for forming a rectifier having high forward bias current with low specific on-resistance, comprising: forming a β-Ga.sub.2O.sub.3 n-type drift layer on a β-Ga.sub.2O.sub.3 substrate; and forming a plurality of predetermined spatially defined semi-insulating regions comprising trenches of ion-implanted acceptor species formed in the β-Ga.sub.2O.sub.3 n-type drift layer; wherein unimplanted regions of the β-Ga.sub.2O.sub.3 n-type drift layer and the ion-implanted regions form alternating n-type and semi-insulating regions in the β-Ga.sub.2O.sub.3 drift layer; and wherein the acceptor species and a depth of the trenches of implanted acceptor species are configured to produce a predetermined electronic response in the rectifier.

11. The method for forming a rectifier according to claim 10, wherein the rectifier is a planar metal oxide-type Schottky barrier diode (P-MOSSBD) rectifier having low on-resistance in forward bias and a low reverse current and high breakdown field in reverse bias.

12. The method for forming a rectifier according to claim 10, wherein the acceptor species comprise N, Mg, Co, Fe, Be, Ca, Sr, Zn, or Cd.

13. The method for forming a rectifier according to claim 10, wherein the β-Ga.sub.2O.sub.3 n-type drift layer is n-doped with Si or Ge.

14. The method for forming rectifier according to claim 10, wherein the trenches of implanted acceptor species are uniformly spaced.

15. The method for forming a rectifier according to claim 10, wherein the trenches of implanted acceptor species are non-uniformly spaced.

16. A method for forming a rectifier having high forward bias current with low specific on-resistance, comprising: forming a β-Ga.sub.2O.sub.3 n-type drift layer on a β-Ga.sub.2O.sub.3 substrate; forming a semi-insulating β-Ga.sub.2O.sub.3 layer formed on the drift layer; and forming a plurality of predetermined spatially defined N-type regions comprising donor ion-implanted species formed in the semi-insulating β-Ga.sub.2O.sub.3 layer; wherein unimplanted regions of the β-Ga.sub.2O.sub.3 n-type drift layer and the ion-implanted regions form alternating semi-insulating and N-type regions in the β-Ga.sub.2O.sub.3; and wherein the acceptor species and a depth of the trenches of implanted acceptor species are configured to produce a predetermined electronic response in the rectifier.

17. The method for forming a rectifier according to claim 16, wherein the rectifier is a planar metal oxide-type Schottky barrier diode (P-MOSSBD) rectifier having low on-resistance in forward bias and a low reverse current and high breakdown field in reverse bias.

18. The method for forming a rectifier according to claim 16, wherein the donor species comprise Si, Ge, or Sn.

19. The method for forming rectifier according to claim 16, wherein the trenches of implanted acceptor species are uniformly spaced.

20. The method for forming a rectifier according to claim 16, wherein the trenches of implanted acceptor species are non-uniformly spaced.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIGS. 1A-1D are block schematics illustrating exemplary state of the art techniques for the fabrication of Ga.sub.2O.sub.3 planar, junction barrier, and trench-MOS Schottky diodes.

[0016] FIG. 2 is a block schematic illustrating an exemplary planar metal oxide-type Schottky barrier diode (P-MOSSBD) device in accordance with the present invention.

[0017] FIG. 3 is a block schematic illustrating an exemplary P-MOSSBD device structure in accordance with the present invention.

[0018] FIG. 4 is a block schematic illustrating a second embodiment of a P-MOSSBD device in accordance with the present invention.

[0019] FIG. 5 is a block schematic illustrating a third embodiment of a P-MOSSBD device in accordance with the present invention.

[0020] FIG. 6 is a block schematic illustrating a fourth embodiment of a P-MOSSBD device in accordance with the present invention.

[0021] FIGS. 7A and 7B are plots showing the simulated electric filed profile of a planar MOSSBD device without Nitrogen-implanted regions (FIG. 7A) and with Nitrogen-implanted regions in accordance with the present invention (FIG. 7B).

[0022] FIGS. 8A and 8B are plots showing the simulated electric field profile as a function of distance from the device surface (anode contact) through the CENTER cutline for devices having the electric field profiles shown in FIGS. 7A and 7B.

[0023] FIG. 9A and FIG. 9B show electrical characterization (Linear Transfer Length Method, LTLM, and Hall effect) of semi-insulating epitaxial Ga.sub.2O.sub.3 doped with Nitrogen during growth and subsequently implanted with donors (Si, Ge, and Sn) to form n-type regions. These results demonstrate the viability of donor-acceptor engineered Ga.sub.2O.sub.3 regions avoiding the need to etch the material to obtain the desired electric field profile.

DETAILED DESCRIPTION

[0024] The aspects and features of the present invention summarized above can be embodied in various forms. The following description shows, by way of illustration, combinations and configurations in which the aspects and features can be put into practice. It is understood that the described aspects, features, and/or embodiments are merely examples, and that one skilled in the art may utilize other aspects, features, and/or embodiments or make structural and functional modifications without departing from the scope of the present disclosure.

[0025] The present invention provides a Ga.sub.2O.sub.3-based rectifier structure and method of forming the same. In accordance with the present invention, a Schottky diode structure is combined with a metal-oxide-semiconductor structure to provide a planar metal oxide-type Schottky barrier diode (P-MOSSBD) rectifier having low on-resistance in forward bias and a low reverse current, high breakdown field in reverse bias.

[0026] A P-MOSSBD structure in accordance with the present invention includes a β-Ga.sub.2O.sub.3 n-type drift layer on a β-Ga.sub.2O.sub.3 substrate, the drift layer having a plurality of spaced-apart semi-insulating regions being formed therein by in-situ ion implantation of acceptor species at predefined spatially defined regions of the draft layer to create alternating areas of n-type and semi-insulating regions within the n-type drift layer. The thus-formed structure achieves high forward bias current with low specific on-resistance when the anode is biased with positive voltage and low leakage current when the device is operated under reverse bias.

[0027] This approach results in improved rectifying characteristics (particularly reverse leakage) without the need for trench etching, avoiding plasma damage, or the integration of dissimilar p-type materials in the device structure, avoiding trap states at the interface. This approach further takes advantage of the wide range of doping capability and the high crystal quality of epitaxial Ga.sub.2O.sub.3.

[0028] A number of species have been studied for their potential application as an acceptor in Gallium Oxide, including but not limited to Mg, Fe, N, Co, Zn, etc. Theoretically, an even wider range of species have been shown to not be viable acceptors in Ga2O3. In every case, these impurities are energetically positioned too far from the valence band of Ga2O3, a.k.a., they are energetically too deep to ionize and become electrically active. Furthermore, even if holes were possible to form, they would be of extremely low mobility as they would essentially self-trap at the acceptor site.

[0029] The block schematic in FIG. 2 illustrates an exemplary P-MOSSBD structure in accordance with the present invention.

[0030] As illustrated in FIG. 2, such a structure includes a β-Ga.sub.2O.sub.3 substrate 201 having a β-Ga.sub.2O.sub.3 n-type drift layer 202, which has been doped with donor ions such as Silicon (Si) or Germanium (Ge), both energetically shallow donors in Ga.sub.2O.sub.3, formed thereon. Tin (Sn) is also an energetically shallow donor in Ga.sub.2O.sub.3, but it tends to form clusters that can potentially lead to gamma-phase inclusions and is thus not as preferable as Si or Ge. Drift layer 202 is patterned, e.g., through the use of a mask or by any other suitable method, to define a plurality of spaced-apart regions to be implanted with acceptor dopants to form a plurality of semi-insulating trenches 203 within the n-type Ga.sub.2O.sub.3. In such a way, in accordance with the present invention, a Ga.sub.2O.sub.3 material having a plurality of alternating n-type and semi-insulating (SI) regions can be formed without the need for etching or otherwise patterning the Ga.sub.2O.sub.3 to form such trenches.

[0031] Acceptor dopants that can be implanted into the drift layer can include N, Mg, Co, Fe, Be, Ca, Sr, Zn, or Cd. Such acceptors are energetically deep acceptors with ionization energy too far above the valence band of Ga2O3. As such, they do not form electrically-active p-type regions or pn junctions when implanted into the —Ga.sub.2O.sub.3. Therefore, a homojunction approach to reducing reverse leakage current and improving breakdown voltage in Ga2O3 via pn junction induced space charge regions is not viable.

[0032] The spacing, width, and depth of the doped SI, with the trenches being uniformly or non-uniformly spaced, can be tailored for particular device applications. For example, a deeper SI region may result in increased on-state resistance but also lead to improved breakdown voltage. Those skilled in the art will recognize that the optimization of the N-type Ga.sub.2O.sub.3 Schottky regions (width, depth, doping level), SI-Ga.sub.2O.sub.3 MOS regions (width, depth, doping level) will address tradeoffs in on-state resistance, breakdown voltage, barrier height, turn-on voltage, reverse leakage current, reverse recovery time, transit time, switching performance, etc., of the P-MOSSBD diode.

[0033] In many embodiments, an optional dielectric layer 204 (e.g., Al.sub.2O.sub.3 or HfO.sub.2) is deposited on the trenches 203, with the device connected to a power source via cathode 205 and anode 206.

[0034] FIG. 3 is a block schematic illustrating an exemplary P-MOSSBD device in accordance with the present invention, where the device includes an epitaxial N-type Ga.sub.2O.sub.3 drift layer 202, epitaxial Semi-Insulating Ga.sub.2O.sub.3 layer (“SI-GO”) 203, and selectively donor-implanted (e.g., Si, Ge, Sn, etc.) n-type Ga.sub.2O.sub.3 regions 207 within the SI-GO layer 203 and extending into the drift layer 202, where the Schottky area of the P-MOSSBD device is defined by the areas of contact between anode 206 and the implanted areas 207 and the non-implanted SI-GO regions 203 defining the MOS area of the device.

[0035] FIG. 4 is a block schematic illustrating an alternative embodiment of a P-MOSSBD device in accordance with the present invention. In this embodiment, an epitaxial N″ Ga.sub.2O.sub.3 layer (“n-GO”) 207 is formed on drift layer 202, with acceptors being selectively implanted into the N-GO layer to form semi-insulating Ga.sub.2O.sub.3 (SI-GO) regions 203 in the n-GO layer. In this embodiment, the Schottky area of the P-MOSSBD device is defined by the areas of contact between anode 206 and the implanted areas 207 and the non-implanted SI-GO regions 203 defining the MOS area of the device.

[0036] FIG. 5 is a block schematic illustrating a third embodiment of a P-MOSSBD device in accordance with the present invention. In this embodiment, areas of semi-insulating Ga.sub.2O.sub.3 (SI-GO) 203 are formed on the drift layer 202, either via selective epitaxy or pattering of a planar epitaxial layer via etching, where the Schottky areas and MOS areas of the device are as described above.

[0037] FIG. 6 is a block schematic illustrating a fourth embodiment of a P-MOSSBD device in accordance with the present invention. In this embodiment, areas of semi-insulating Ga.sub.2O.sub.3 are formed on epitaxial N-Ga.sub.2O.sub.3 layer 207 either via selective epitaxy or pattering of a planar epitaxial layer via etching, where the Schottky areas and MOS areas of the device are as described above.

[0038] FIG. 7A shows the simulated electric field profile of a planar Ga.sub.2O.sub.3 Schottky diode shown in FIG. 1A, while FIG. 7B shows the simulated electric field profile of a planar MOS-SBD diode with epitaxial n-type regions and Nitrogen-implanted SI-Ga2O3 regions, as illustrated in FIG. 4.

[0039] FIG. 8A shows the simulated electric field profile as a function of distance from the device surface (anode contact) through the CENTER cutline shown in FIGS. 7A and 7B. The peak electric field is significantly reduced as a result on the implant, leading to improved reverse leakage current and breakdown field of the P-MOSSBD device.

[0040] FIG. 8B shows the simulated electric field profile as a function of distance from the device surface (anode contact) through the EDGE cutline shown in FIGS. 7A and 7B. As with the electric field profile through the CENTER cutline shown in FIG. 8A, the peak electric field at the EDGE cutline is significantly reduced as a result on the implant, leading to improved reverse leakage current and breakdown field of the P-MOSSBD device.

[0041] FIG. 9A and FIG. 9B show electrical characterization (Linear Transfer Length Method, LTLM, and Hall effect) of semi-insulating epitaxial Ga.sub.2O.sub.3 doped with Nitrogen during growth and subsequently implanted with donors (Si, Ge, and Sn) to form n-type regions. These results demonstrate the viability of donor-acceptor engineered Ga.sub.2O.sub.3 regions avoiding the need to etch the material to obtain the desired electric field profile.

[0042] Advantages and New Features

[0043] The main new feature introduced by the present invention is the acceptor-implanted regions in between the Schottky diode regions of the vertical Ga.sub.2O.sub.3 rectifier to implement alternating n-type and semi-insulating (SI) regions contacting an anode metal layer. Although doping of Ga.sub.2O.sub.3 with acceptors such as Nitrogen may not result in p-type conductivity in the Ga.sub.2O.sub.3, such acceptors do substantially decrease its electrical conductivity, resulting in semi-insulating (SI) electrical behavior in acceptor-doped material. In this configuration, the rectifier achieves high forward bias current with low specific on-resistance when the anode is biased with positive voltage. In reverse bias, the leakage current is minimized due to the presence of the SI regions (with an optional gate dielectric deposited under the anode). A rectifier in accordance with the present invention thus operates similarly to a junction-barrier Schottky diode or a trench-MOS Schottky diode but does not require any etched structures or p-type regions, thus avoiding the formation of interface states related to etch damage and other reliability complications introduced by the integration of a dissimilar p-type material in the device. The presence of an acceptor-doped regions in the device further reduces the Fermi level near the anode in those regions, allowing for the low reverse current to persist at higher reverse bias compared to that of a Schottky diode. This effect may partially compensate for the absence of a space charge region induced by lateral depletion in a JBS or a trench-MOS diode, achieving similar or better overall performance.

[0044] Alternatives

[0045] A similar rectifier can be obtained by etching a trench in the epitaxial Ga.sub.2O.sub.3 (a.k.a., trench-MOS diode). See U.S. Pat. No. 11,081,598 to Sasaki et al., entitled “Trench MOS Schottky Diode” (2021) and U.S. Pat. No. 10,825,935 to Sasaki et al., entitled “Trench MOS-Type Schottky Diode” (2020); see also M. Mehrotra and B. J. Baliga, “Trench MOS Barrier (TMBS) Rectifier: A Schottky Rectifier with higher than parallel plane breakdown voltage,” Solid-State Electron. 38 (4) 801-806, 1995. Integrating a p-type material on the surface of the Ga2O3 semiconductor can result in p-n or p-i-n diode operation which is based on pn junction theory (carrier diffusion) instead of Schottky diode theory (thermionic-field emission).

[0046] Other alternative devices are the junction-barrier Schottky (JBS) diode, where the regions contacting the anode are of alternative p- and n-type conductivity. In this JBS architecture, the rectifier resembles Schottky diode operation in forward bias and a pn diode in reverse bias. Variations of the JBS architecture, for instance the merged-pin-Schottky (MPS) diode, can be obtained by varying the p-type doping level in the JBS and termination regions.

[0047] In additional embodiments, instead of acceptor species, the Ga.sub.2O.sub.3 can be implanted with donor species such as Si, Ge, or Sn to form n-type regions of Ga.sub.2O.sub.3 within a semi-insulating epitaxial layer.

[0048] Although particular embodiments, aspects, and features have been described and illustrated, one skilled in the art would readily appreciate that the invention described herein is not limited to only those embodiments, aspects, and features but also contemplates any and all modifications and alternative embodiments that are within the spirit and scope of the underlying invention described and claimed herein. The present application contemplates any and all modifications within the spirit and scope of the underlying invention described and claimed herein, and all such modifications and alternative embodiments are deemed to be within the scope and spirit of the present disclosure.