Abstract
A circuit arrangement is provided which includes an array of stages for photon counting current to voltage conversion. Each stage includes a tunable operational transconductance amplifier and a feedback network forming a feedback loop of the operational transconductance amplifier. Each stage is configured to provide an output signal as a function of an input signal that is provided to the amplifier input of the operational transconductance amplifier, wherein the input signal comprises one or more current pulses and the output signal comprises one or more voltage pulses. With the tunable operational transconductance amplifier the transconductance of a stage can be tuned so that differences in peaking time and gain are avoided. Furthermore, an imaging device and a method for operating a circuit arrangement are provided.
Claims
1. A circuit arrangement comprising: an array of stages for photon counting current to voltage conversion, wherein each stage comprises: a tunable operational transconductance amplifier comprising an amplifier input and an output, and a feedback network that is connected to the amplifier input and to the output of the operational transconductance amplifier thereby forming a feedback loop of the operational transconductance amplifier, wherein each stage is configured to provide an output signal as a function of an input signal that is provided to the amplifier input of the operational transconductance amplifier, wherein the input signal comprises one or more current pulses and the output signal comprises one or more voltage pulses.
2. The circuit arrangement according to claim 1, wherein for each stage a noise injection block is connected to a further input of the operational transconductance amplifier.
3. The circuit arrangement according to claim 2, wherein each noise injection block comprises a buffer component with tunable noise level that is arranged between a reference potential terminal and the further input of the respective operational transconductance amplifier.
4. The circuit arrangement according to claim 3, wherein each noise injection block comprises a tunable capacitor that is connected to a first internal node arranged between the buffer component and the further input (14) of the respective operational transconductance amplifier.
5. The circuit arrangement according to claim 1, wherein the circuit arrangement further comprises a plurality of heaters, where each heater is assigned to one of the stages, respectively.
6. The circuit arrangement according to claim 1, wherein for each stage the tunable operational transconductance amplifier is configured to be supplied with a control voltage, where by changing the control voltage the transconductance of the respective operational transconductance amplifier can be tuned.
7. The circuit arrangement according to claim 1, wherein for each stage at least one further tunable operational transconductance amplifier is connected in parallel to the tunable operational transconductance amplifier.
8. The circuit arrangement according to claim 1, wherein each stage is configured to receive current pulses generated by a photon detector.
9. An imaging device comprising the circuit arrangement according to claim 1, wherein the imaging device is in particular a spectral imaging device or a medical imaging device.
10. The imaging device according to claim 9, wherein the imaging device comprises a photon detector and for each stage a pixel of the photon detector is connected to the amplifier input of the operational transconductance amplifier, respectively.
11. The imaging device according toclaim 10, wherein an interposer is arranged between the circuit arrangement and the photon detector.
12. A method for operating a circuit arrangement that comprises an array of stages for photon counting current to voltage conversion, each stage comprising a tunable operational transconductance amplifier with an amplifier input and an output, and a feedback network connected to the amplifier input and to the output of the operational transconductance amplifier thereby forming a feedback loop of the operational transconductance amplifier, the method comprising: providing a respective input signal to each stage of the array of stages, generating, with each stage, an output signal as a function of the respective input signal that is provided to the amplifier input of the respective operational transconductance amplifier, wherein the input signal comprises one or more current pulses and the output signal comprises one or more voltage pulses, and providing control voltages to the tunable operational transconductance amplifiers, respectively, such that the transconductance of the respective operational transconductance amplifier is tuned.
13. The method according to claim 12, wherein for each stage the transconductance of the operational transconductance amplifier is tuned in such a way that the bandwidth of the respective stage is within a predefined range.
14. The method according to claim 12, wherein noise is injected to a further input of the operational transconductance amplifier by a noise injection block for at least one of the stages.
15. The method according to claim 12, wherein in a calibration step an input capacitance is determined for each stage.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0039] The following description of figures may further illustrate and explain exemplary embodiments. Components that are functionally identical or have an identical effect are denoted by identical references. Identical or effectively identical components might be described only with respect to the figures where they occur first. Their description is not necessarily repeated in successive figures.
[0040] FIG. 1 shows the general setup of a photon counting system.
[0041] FIGS. 2 and 3 show possibilities for the arrangement of a sensor on a frontend circuit.
[0042] FIGS. 4 and 5 show circuits for photon counting.
[0043] FIG. 6 shows a circuit arrangement known from prior art.
[0044] FIG. 7 shows an exemplary embodiment of a circuit arrangement and an exemplary embodiment of an imaging device.
[0045] FIGS. 8 and 9 show further exemplary embodiments of the circuit arrangement.
[0046] FIG. 10 shows another exemplary embodiment of the imaging device.
[0047] FIGS. 11 and 12 show further exemplary embodiments of the circuit arrangement.
DETAILED DESCRIPTION
[0048] FIG. 1 shows the setup of a photon counting system 27. A photon detector 25 can be exposed to photons and it is configured to detect photons. The photon detector 25 is configured to provide one or more current pulses to a circuit arrangement 10 in response to the detection of photons. One current pulse is schematically depicted between the photon detector 25 and the circuit arrangement 10. A frontend circuit 28 of the circuit arrangement 10 is configured to convert the one or more current pulses into one or more voltage pulses. The one or more voltage pulses are provided to a network of comparators 29 that constitute an analog-to-digital converter (ADC). One voltage pulse is schematically depicted between the frontend circuit 28 and the comparators 29. The ADC comprises a plurality of comparators 29. Each comparator 29 is configured to convert analog signals into digital signals. It depends on the peak voltage of a voltage pulse provided by the frontend circuit 28 which of the comparators 29 will trigger. This means, each of the comparators 29 is assigned to a different voltage range. In this way, the voltage pulses can be counted in dependence of their peak voltage. For this purpose, the output of each comparator 29 is connected to a counter 30. Thus, spectral information can be obtained with the circuit arrangement 10.
[0049] FIG. 2 shows a possible connection of a photon detector 25 with a circuit arrangement 10. On the circuit arrangement 10 an integrated circuit 31 with through-silicon vias 32 is arranged. The through-silicon vias 32 extend through the integrated circuit 31 and provide electrical contacts of supply and input/output pads to the bottom. Above the integrated circuit 31 the photon detector 25 is arranged. The photon detector 25 is directly electrically connected via electrical connections 33.
[0050] FIG. 3 shows another possible connection of a photon detector 25 with a circuit arrangement 10. On the circuit arrangement 10 an integrated circuit 31 is arranged. On the integrated circuit 31 electrical connections 33 are arranged. On the electrical connections 33 an interposer 26 is arranged. The photon detector 25 is arranged above the interposer 26 and is connected to the interposer 26 via electrical connections 33. Within the interposer 26 electrical connections 33 are arranged that connect the photon detector 25 with the circuit arrangement 10 via the surrounding electrical connections 33. For different parts of the photon detector 25 the electrical connections 33 within the interposer 26 have different lengths.
[0051] FIG. 4 shows a circuit 38 for photon counting which is no embodiment. The circuit 38 is a frontend circuit 28 for photon counting. The circuit 38 comprises an input 34 at which an input current can be received. The circuit 38 can have an input capacitance C.sub.in which represented by an input capacitor 35 connected to a first internal node 21. The first internal node 21 is connected to the input 34 and to an amplifier input 13 of an OTA 12. A further input 14 of the OTA 12 is connected to a reference potential terminal 19. The OTA 12 is configured to convert current pulses received at its amplifier input 13 into voltage pulses that are provided at an output 15 of the OTA 12. One voltage pulse is schematically depicted at the output 15 of the OTA 12. The circuit 38 further comprises a feedback network 16. The feedback network 16 comprises a feedback capacitor 36 and a resistor 37. The feedback capacitor 36 is connected to the output 15 of the OTA 12 and to the amplifier input 13 of the OTA 12. The resistor 37 is connected parallel to the feedback capacitor 36. At an output 15 of the circuit 38 one or more voltage pulses can be provided. For the circuit 38 the peaking time, gain and noise directly depend on the input capacitance C.sub.in.
[0052] FIG. 5 shows another circuit 38 for photon counting which is no embodiment. The circuit 38 comprises an input 34 at which one or more current pulses can be received. The circuit 38 can have an input capacitance C.sub.in which is represented by an input capacitor 35 connected to a first internal node 21. The first internal node 21 is connected to the input 34 and to a first circuit element 39 of the circuit 38. The first circuit element 39 has the setup shown in FIG. 4. The first circuit element 39 is a charge sensitive amplifier. The circuit 38 further comprises a second circuit element 40 which has the setup shown in FIG. 4. Between the first circuit element 39 and the second circuit element 40 a passive coupling network 41 is arranged. The passive coupling network 41 comprises a resistor 37 that is connected parallel to a capacitor 42. By employing the passive coupling network 41 the input capacitance C.sub.in is buffered and the second circuit element 40 is decoupled from the input capacitance C.sub.in. In this way, the impact of the input capacitance C.sub.in on the performance parameters of the second circuit element 40 is reduced. However, the noise level of the circuit 38 still depends on the input capacitance C.sub.in.
[0053] FIG. 6 shows a circuit arrangement 10 known from prior art, for example from US 20180372887 A1. The circuit arrangement 10 comprises a plurality of channels 43. Each channel 43 is connected to a pixel of a photon detector 25. Each channel 43 comprises a frontend circuit 28. Because of the electrical connection between the photon detector 25 and the frontend circuit 28 an input capacitance C.sub.in is introduced which is represented by an input capacitor 35. The circuit arrangement 10 comprises a tunable capacitor 20 for each channel 43. This means, to the input 34 of each frontend circuit 28 a tunable capacitor 20 is connected. The capacitance of the tunable capacitor 20 is adjusted in such a way that for each channel 43 the sum of the input capacitance C.sub.in and the capacitance of the tunable capacitor 20 is equal. Thus, for each frontend circuit 28 the total input capacitance C.sub.in is equal. This leads to an equalization of the performance parameters of different circuits. However, the power consumption is increased as the worst input capacitance C.sub.in is employed for all channels 43. Furthermore, additional non-ideality can be introduced by the tunable capacitors 20.
[0054] FIG. 7 shows an exemplary embodiment of a circuit arrangement 10. The circuit arrangement 10 comprises an array of stages 11 for photon counting current to voltage conversion. The stages 11 can be connected parallel to each other. Each stage 11 comprises an input 34 that is connected to a pixel of a photon detector 25. This means, each stage 11 is configured to receive current pulses generated by the photon detector 25. Each stage 11 can be connected to its own pixel of the photon detector 25. The pixels are configured to receive photons and to generate one or more current pulses in response to receiving a photon. For each stage 11 the respective pixel is connected to an input node 44. The input node 44 is further connected to the input 34 of the respective stage 11. One current pulse is schematically depicted at the input node 44. In addition, an input capacitance C.sub.in is introduced by the connection between the photon detector 25 and the circuit arrangement 10. This input capacitance C.sub.in is represented in FIG. 7 by an input capacitor 35 connected to the input node 44.
[0055] Each stage 11 comprises a tunable OTA 12 comprising an amplifier input 13, a further input 14 and an output 15. Furthermore, each stage 11 comprises a feedback network 16 that is connected to the amplifier input 13 and to the output 15 of the OTA 12 thereby forming a feedback loop of the OTA 12. The feedback network 16 comprises a feedback capacitor 36 and a transconductance feedback element 45. The feedback capacitor 36 is connected to the amplifier input 13 and to the output 15 of the OTA 12. The transconductance feedback element 45 is connected parallel to the feedback capacitor 36. The transconductance feedback element 45 can be a transconductor or a resistor. The feedback loop can be configured to provide feedback from the output 15 of the OTA 12 to the amplifier input 13.
[0056] For each stage 11 the tunable OTA 12 is configured to be supplied with a control voltage, where by changing the control voltage the transconductance g.sub.m of the respective OTA 12 can be tuned. In this way, the transconductance g.sub.m of a stage 11 can be tuned or adjusted.
[0057] The output 15 of the OTA 12 is connected to a second internal node 46. The second internal node 46 is connected to an output 15 of the respective stage 11 and to a load capacitor 47.
[0058] Each stage 11 is configured to provide an output signal as a function of an input signal that is provided to the amplifier input 13 of the OTA 12, wherein the input signal comprises one or more current pulses and the output signal comprises one or more voltage pulses.
[0059] For each stage 11 a variation in the input capacitance C.sub.in has an impact on the feedback factor β which is for higher frequencies is given by
[00001]
where C.sub.fb is the capacitance of the feedback capacitor 36 and C.sub.in is the input capacitance.
[0060] The bandwidth BW of a stage 11 has impact on the peaking time and the gain and is given by
[00002]
where g.sub.m is the transconductance of the respective stage 11 and C.sub.1 is the capacitance of the load capacitor 47. Thus, by tuning the transconductance g.sub.m of the stages 11 the different input capacitances C.sub.in can be balanced. In this way, an equalization of the performance parameters of the different stages 11 is achieved.
[0061] The setup of the circuit arrangement 10 shown in FIG. 7 can be employed in both of the setups shown in FIG. 4 and FIG. 5.
[0062] The circuit arrangement 10 of FIG. 7 can be employed for a method for operating a circuit arrangement 10. The method comprises providing a respective input signal to each stage 11 of the array of stages 11. Furthermore, with each stage 11 an output signal is generated as a function of the respective input signal that is provided to the amplifier input 13 of the respective OTA 12. In order to tune the transconductance g.sub.m of the respective OTAs 12 control voltages are provided to the OTAs 12, respectively. For each stage 11 the transconductance g.sub.m of the OTA 12 is tuned in such a way that the bandwidth of the respective stage 11 is within a predefined range. In a calibration step the input capacitance C.sub.in is determined for each stage 11.
[0063] FIG. 7 further shows an exemplary embodiment of an imaging device 24. The imaging device 24 can be a spectral imaging device or a medical imaging device. The imaging device 24 comprises the circuit arrangement 10 and the photon detector 25. For each stage 11 a pixel of the photon detector 25 is connected to the amplifier input 13 of the OTA 12, respectively.
[0064] In FIG. 8 another exemplary embodiment of the circuit arrangement 10 is shown. The circuit arrangement 10 shown in FIG. 8 has the same setup as shown in FIG. 7 except for an additional noise injection block 17. Each stage 11 comprises a noise injection block 17 that is connected to the further input 14 of the OTA 12. For each stage 11 the noise injection block 17 is connected to the further input 14 of the OTA 12 via a first internal node 21. The first internal node 21 is arranged between a reference potential terminal 19 and the further input 14 of the OTA 12.
[0065] The output noise V.sub.n of a stage 11 is given by
[00003]
where k is a constant. The output noise thus depends on the input capacitance C.sub.in and it is independent from the transconductance g.sub.m. Therefore, for an equalization of the noise level noise injection blocks 17 are employed. Noise can be injected to the further input 14 of the OTA 12 by a noise injection block 17 for at least one of the stages 11.
[0066] FIG. 9 shows another exemplary embodiment of the circuit arrangement 10. The circuit arrangement 10 has the same setup as shown in FIG. 8 with the only difference that the setup of the noise injection block 17 is further specified. The noise injection block 17 comprises a buffer component 18 and a tunable capacitor 20. The buffer component 18 and the tunable capacitor 20 are both connected to the first internal node 21 which is arranged between the buffer component 18 and the further input 14 of the OTA 12. The buffer component 18 has a tunable noise level and it is arranged between the reference potential terminal 19 and the first internal node 21. The transconductance g.sub.m and the noise level of the buffer component 18 can be tuned.
[0067] FIG. 10 shows another exemplary embodiment of the imaging device 24. In this embodiment an interposer 26 is arranged between the circuit arrangement 10 and the photon detector 25.
[0068] FIG. 11 shows another exemplary embodiment of the circuit arrangement 10. In comparison to the circuit arrangement 10 shown in FIG. 7 the circuit arrangement 10 of FIG. 11 further comprises a plurality of heaters 22, where each heater 22 is assigned to one of the stages 11, respectively. The heaters 22 are arranged in close proximity to the respective stages 11.
[0069] FIG. 12 shows another exemplary embodiment of the circuit arrangement 10. In comparison to the circuit arrangement 10 shown in FIG. 7 the circuit arrangement 10 of FIG. 12 further comprises at least one further tunable OTA 23 for each stage 11 where the further tunable OTA 23 is connected in parallel to the tunable OTA 12. The circuit arrangement 10 can comprise several further tunable OTAs 23 which is indicated by dashed lines in FIG. 12. The at least one further OTA 23 can be employed to further tune the transconductance g.sub.m of the respective stage 11.
[0070] It will be appreciated that the disclosure is not limited to the disclosed embodiments and to what has been particularly shown and described hereinabove. Rather, features recited in separate dependent claims or in the description may advantageously be combined. Furthermore, the scope of the disclosure includes those variations and modifications, which will be apparent to those skilled in the art. The term “comprising”, insofar it was used in the claims or in the description, does not exclude other elements or steps of a corresponding feature or procedure. In case that the terms “a” or “an” were used in conjunction with features, they do not exclude a plurality of such features. Moreover, any reference signs in the claims should not be construed as limiting the scope.
