SHAPER CIRCUIT, PHOTON COUNTING CIRCUIT AND X-RAY APPARATUS

Abstract

A shaper circuit includes a first amplifier including an input and an output, the input being configured to receive an input signal, which includes one or more current pulses, a feedback component coupled to the output and to the input of the first amplifier thereby forming a feedback loop of the first amplifier, and an RC component coupled to the output of the first amplifier and to a reference potential terminal. Therein the shaper circuit is configured to provide an output signal as a function of the input signal, the output signal including one or more voltage pulses, and the RC component is configured to largely cancel a low frequency pole of the feedback loop of the first amplifier.

Claims

1. A shaper circuit comprising: a first amplifier comprising an input and an output, the input being configured to receive an input signal, which comprises one or more current pulses, a feedback component coupled to the output and to the input of the first amplifier thereby forming a feedback loop of the first amplifier, and an RC component coupled to the output of the first amplifier and to a reference potential terminal, wherein the shaper circuit is configured to provide an output signal as a function of the input signal, the output signal comprising one or more voltage pulses, wherein the RC component is configured to largely cancel a low frequency pole of the feedback loop of the first amplifier, wherein the RC component comprises a resistor and a capacitor which are connected in series, the resistor or the capacitor being directly connected to the output of the first amplifier, wherein a resistance of the resistor of the RC component is smaller than or equal to a resistance of an internal output resistor of the first amplifier, wherein a capacitance of the capacitor of the RC component is larger than a load capacitance occurring at the output of the first amplifier, wherein the first amplifier comprises an operational transconductance amplifier and a transconductance of said first amplifier is adjusted in dependence on an input capacitance occurring at the input of the shaper circuit, and wherein the shaper circuit is configured for use in a photon counting circuit.

2-6. (canceled)

7. The shaper circuit according to claim 1, further comprising a buffer component which is connected to the output of the first amplifier, the buffer component comprising a second amplifier having unity gain or having a gain below ten.

8. The shaper circuit according to claim 1, wherein the second amplifier and is configured as open loop amplifier and comprises a first and a second metal-oxide semiconductor, MOS, transistor of the same type, said transistors being connected by their drain terminals and by their source terminals which source terminals are connected to the ground potential terminal, wherein a gate terminal of the first transistor is connected to the output of the first amplifier, a gate terminal of the second transistor is connected to its drain terminal and wherein the output signal is provided at the respective drain terminal of the first and the second transistor.

9. The shaper circuit according to claim 1, wherein the second amplifier is configured as open loop amplifier and comprises a third metal-oxide semiconductor, MOS, transistor, a fourth MOS transistor and a fifth MOS transistor that are all of the same type, the third and the fourth transistor being connected by their respective drain terminal, wherein a gate terminal of the third transistor is connected to the output of the first amplifier, a gate terminal of the fourth transistor is connected to its drain terminal, a source terminal of the fourth transistor is connected to a source terminal of the fifth transistor, a gate terminal of the fifth transistor is configured to receive a reference voltage and wherein the output signal is provided at the respective drain terminal of the third and the fourth transistor.

10. The shaper circuit according to claim 1, wherein the second amplifier is configured as open loop amplifier and comprises a sixth metal-oxide semiconductor, MOS, a seventh MOS transistor, an eighth MOS transistor and a ninth MOS transistor that are all of the same type, the sixth and the seventh transistor being connected by their respective source terminal, wherein a gate terminal of the sixth transistor is connected to the output of the first amplifier, a drain terminal of the sixth transistor is connected to a drain terminal of the seventh transistor via a current mirror, a gate terminal of the seventh transistor is configured to receive a reference voltage, a drain terminal of the seventh transistor is connected to a drain terminal and to a gate terminal of the eighth transistor, a source terminal of the eighth transistor is connected to a source terminal of the ninth transistor, a gate terminal of the ninth transistor is configured to receive the reference voltage, and wherein the output signal is provided at the respective drain terminal of the seventh and the eighth transistor.

11. The shaper circuit according to claim 1, wherein the buffer component further comprises an RC divider circuit and the second amplifier is configured in feedback using the RC divider circuit.

12. The shaper circuit according to claim 11, wherein the RC divider circuit comprises a first parallel connection comprising a first resistor and a first capacitor being connected in parallel and a second parallel connection comprising a second resistor and a second capacitor being connected in parallel, wherein the first parallel connection is coupled to an output of the second amplifier, the second parallel connection is connected in series to the first parallel connection and to the reference potential terminal and wherein a connection point between the first and the second parallel connection is connected to an input of the second amplifier.

13. The shaper circuit according to claim 12, wherein each of the first and the second resistor is implemented by a Metal-oxide semiconductor resistor comprising a tenth transistor, an eleventh transistor and a seventh current source, wherein a gate terminal of the tenth transistor is connected to a gate terminal of the eleventh transistor, the gate terminal of the eleventh transistor is connected to a drain terminal of the eleventh transistor and to seventh the current source and a source terminal of the eleventh transistor is connected to a supply potential terminal.

14. A photon counting circuit comprising: a sensor configured to detect one or more photons and convert each photon into a current pulse, the shaper circuit according to claim 1, being connected to the sensor, an analog-to-digital converter configured to receive the output signal of the shaper circuit and to provide a digital value for each of the received voltage pulses, the digital value depending on the height of a converted voltage pulse, and a counter component coupled downstream of the analog-to-digital converter, the counter component being configured to count the digital values.

15. An x-ray apparatus using the photon counting circuit according to claim 14.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The text below explains the proposed shaper circuit, photon counting circuit and X-ray apparatus in detail using exemplary embodiments with reference to the drawings. Components and circuit elements that are functionally identical or have the identical effect bear identical reference numbers. In so far as circuit parts or components correspond to one another in function, a description of them will not be repeated in each of the following figures. Therein,

[0065] FIG. 1 shows a first exemplary embodiment of the proposed shaper circuit,

[0066] FIG. 2 shows a second exemplary embodiment of the proposed shaper circuit,

[0067] FIGS. 3a, 3b, 3c and 3d each show an exemplary embodiment of a buffer component as proposed,

[0068] FIG. 4 shows an exemplary embodiment of the proposed photon counting circuit, and

[0069] FIG. 5 shows an exemplary embodiment of the proposed X-ray apparatus,

[0070] FIG. 6 shows a two-stage photon counting frontend of the state of the art,

[0071] FIG. 7 shows a single-stage photon counting frontend of the state of the art,

[0072] FIGS. 8 and 9 each show curves of the single-stage frontend of the state of the art according to FIG. 7.

DETAILED DESCRIPTION

[0073] FIG. 1 shows a first exemplary embodiment of the proposed shaper circuit.

[0074] The shaper circuit comprises a first amplifier 20, a feedback component 30 and an RC component 40. The first amplifier 20 comprises an input 21 and an output 22. The input 21 is configured to receive an input signal Iin, which comprises one or more current pulses. The feedback component 30 is coupled between the output 22 and the input 21 of the first amplifier 20. The RC component 40 is coupled to the output 22 of the first amplifier 20 and to a reference potential terminal 10. The shaper circuit is configured to provide an output signal Vout as a function of the input signal Iin. The output signal Vout comprises one or more voltage pulses. Therein, the RC component 40 is configured to largely cancel a low frequency pole of the feedback loop of the first amplifier 20.

[0075] In the embodiment depicted in FIG. 1 the feedback component comprises a transconductance element Rfb and feedback capacitor Cfb which are coupled in parallel. The transconductance element Rfb may be realized by a feedback resistor Rfb or by an operational transconductance amplifier.

[0076] The RC component 40 comprises a resistor Rz and a capacitor Cz which are coupled in series between the output 22 of the first amplifier 20 and the reference potential terminal. As depicted in FIG. 1, the resistor Rz is directly connected to the output 22 of the first amplifier 20. A second terminal of the resistor Rz is coupled to a first terminal of the capacitor Cz. A second terminal of the capacitor Cz is connected to the reference potential terminal. In an alternative realization, not shown in FIG. 1, the order of the capacitor Cz and the resistor Rz is reversed, i.e. the capacitor Cz is directly connected to the output 22 of the first amplifier 20 and the resistor Rz is connected to the second plate of the capacitor Cz and, on the other hand, is connected to the reference potential terminal.

[0077] In the depicted example the first amplifier 20 is realized as an operational transconductance amplifier 20 having an inverting input which coincides with the input 21 and a non-inverting input which receives a reference voltage Vref. The depicted exemplary embodiment also shows the parasitic input capacitance represented by input capacitor Cin which is coupled to the input 21 and to the reference potential terminal 10. Furthermore, a load capacitance which occurs at the output 22 is depicted and represented by a load capacitor C1, which is connected to the output 22 and to the reference potential terminal 10.

[0078] The reference potential terminal 10 may be a ground potential terminal or a terminal supplied with a defined reference voltage.

[0079] The shaper circuit converts the current pulses received with the input signal Iin into voltage pulses, which are furnished with the output signal Vout. By means of the RC component 40, a loop gain function or a loop transfer function of the shaper circuit is altered such that a low frequency pole of the feedback loop of the amplifier is largely cancelled. Consequently, overshoot, undershoot or oscillation of the output signal Vout is prevented. This depicted single stage topology of the shaper circuit results in power savings compared with state of the art two-stage topologies.

[0080] A loop gain of the shaper circuit as proposed can be approximated according to the following equation:

[00005]$\begin{array}{cc}{A}_{\mathrm{loop}}\approx \frac{g_m{r}_{\mathrm{out}}.Math.\left(1+s.Math.C_{\mathrm{fb}}.Math.R_{\mathrm{fb}}\right).Math.\left(1+s.Math.C_z.Math.R_z\right)}{\left(1+s.Math.\left(C_{\mathrm{fb}}+C_{\mathrm{in}}\right).Math.R_{\mathrm{fb}}\right).Math.\left(1+s.Math.\left(C_L+C_z\right).Math.r_{\mathrm{out}}\right).Math.\left(1+s.Math.C_L.Math.R_z.Math.\mathrm{rout}\right)}.& \left(7\right)\end{array}$

[0081] Therein A.sub.loop represents a loop gain of the frontend of FIG. 1, r.sub.out represents a resistance of the internal output resistor rout of the first amplifier 20, g.sub.m represents a transconductance gm of the first amplifier 20, s represents the complex frequency jω, C.sub.fb represents a capacitance of the feedback capacitor Cfb, R.sub.fb represents a resistance of the feedback resistor Rfb, C.sub.in represents the input capacitance Cin and C.sub.1 represents the load capacitance C1, C.sub.z represents the capacitance value of the capacitor Cz of the RC component, R.sub.z represents the resistance value of the resistor Rz of the RC component 40.

[0082] By means of the RC component 40, a low frequency pole p1 of the loop gain function as defined in equation (3) is largely cancelled.

[0083] A resistance of the resistor Rz of the RC component 40 is smaller than or equal to a resistance of the internal output resistor rout of the first amplifier 20. Furthermore, a capacitance value of the capacitor Cz of the RC component 40 is larger than a load capacitance C1 at the output 22 of the first amplifier.

[0084] Due to cancelling of the low frequency pole p1, the loop gain A.sub.loop of the shaper circuit is approximated by the following equation

[00006]$\begin{array}{cc}{A}_{\mathrm{loop}}\approx \frac{g_m{r}_{\mathrm{out}}.Math.\left(1+s.Math.C_{\mathrm{fb}}.Math.R_{\mathrm{fb}}\right)}{\left(1+s.Math.\left(C_L+C_z\right).Math.r_{\mathrm{out}}\right).Math.\left(1+s.Math.C_L.Math.R_z.Math.\mathrm{rout}\right)}.& \left(8\right)\end{array}$

[0085] Furthermore, the introduction of the RC component 40 and proper dimensioning of the resistor Rz and the capacitor Cz of said RC component 40 achieves that the high frequency pole p2′ is moved to higher frequencies beyond the zero z1 as detailed in the following graph:

[0086] The high frequency pole p2′ results from the parallel connection of the internal output resistor rout of the first amplifier 20 and the resistor Rz of the RC component 40. Another zero z2 is introduced by the RC component 40 as well as another pole p3 as indicated in the graph and already described above.

[0087] Compared with state of the art single stage topologies as depicted in FIG. 7, for example, the shaper circuit as proposed is able to cope with large input capacitance Cin of up to 1 pF, for example, without overshoot or undershoot of the output signal Vout.

[0088] The RC component 40 may also be denoted as a pole zero network, because it largely cancels the low frequency pole p1 and moves the high frequency pole p2′ to higher frequencies beyond the zero z1. At high frequencies, the capacitor Cz acts as a short, leaving the resistor Rz in parallel to the internal output resistor of the first amplifier, effectively shifting the high frequency pole p2 to the right beyond z1.

[0089] For further improving the proposed shaper circuit's performance, a transconductance value gm of the first amplifier 20 is adjusted in dependence on the input capacitance Cin. Thereby, compensation is achieved for varying input capacitance Cin. As explained above, the input capacitance is highly dependent on package routing. Therefore, by calibrating the transconductance value gm of the first amplifier 20, the influence of the input capacitance Cin is further reduced.

[0090] The transconductance gm of the first amplifier 20 is tuned with respect to a nominal design point in dependence on the input capacitance Cin, a nominal input capacitance Cin0 and a nominal transconductance gm0 according to the following equation:

[00007]$\begin{array}{cc}\mathrm{gm}=\frac{C\mathrm{in}}{C\mathrm{in}0}*\mathrm{gm}0.& \left(9\right)\end{array}$

[0091] Therein, gm represents the transconductance gm of the first amplifier 20, gm0 represents the nominal transconductance gm0 of the first amplifier 20, Cin represents the input capacitance Cin occurring at the input 21 of the shaper circuit and Cin0 represents the nominal input capacitance Cin0.

[0092] Consequently, by calibrating out the influence of the input capacitance, constant performance of the shaper circuit even in the presence of varying input capacitance Cin is guaranteed.

[0093] FIG. 2 shows a second exemplary embodiment of the shaper circuit as proposed. The shaper circuit depicted in FIG. 2 coincides with the shaper circuit of FIG. 1 and additionally comprises a buffer component 50. Said buffer component 50 is connected to the output 22 of the first amplifier 20. The buffer component 50 comprises a second amplifier 51 having unity gain or having a gain below 10. In this exemplary embodiment the output signal Vout is provided at an output of the buffer component 50.

[0094] By means of the buffer component 50 the output 22 of the shaper circuit is isolated from subsequent circuitry which can be connected to said output and may have considerable capacitive load of several hundred nF represented by the load capacitor C1. The second operational amplifier 51 of the buffer component 50 is configured as an open loop circuit in order to keep power consumption by the buffer component 50 as low as possible. A gain of the second amplifier 51 is chosen to be below 10. In the depicted example the gain is below 2 or is a unity gain.

[0095] In the following FIGS. 3A, 3B, 3C and 3D different implementation possibilities for the buffer component are depicted and explained in detail in exemplary embodiments.

[0096] FIG. 3A shows a first exemplary embodiment of a buffer component as proposed. In this embodiment the buffer component comprises the operational amplifier 51 which comprises a first transistor T1 and a second transistor T2. The first and second transistors T1, T2 are respectively realized as a MOS transistor of the same type, i.e. both transistors are realized as NMOS transistors as depicted in FIG. 3A. The first and second transistors T1, T2 are connected by their drain terminals 23 and are also connected by their source terminals. The source terminals of transistors T1 and T2 are also connected to the reference potential terminal 10. A gate terminal of the first transistor T1 is connected to the output 22 of the first amplifier 20. A gate terminal of the second transistor T2 is connected to its drain terminal 23. Said drain terminal 23 is also connected via a first current source Cs1 to a supply potential terminal 11. The supply potential terminal 11 receives a supply voltage Vdd, for example. The output signal Vout is provided at the drain terminals 23 of the first and the second transistor T1, T2.

[0097] The first transistor T1 has a first transconductance gm1, while the second transistor T2 has a second transconductance gm2. A gain realized by the example embodiment of FIG. 3A can be calculated as the quotient of the first transconductance gm1 with the second transconductance gm2. The second transistor T2 therein forms a load transistor to the first transistor T1.

[0098] FIG. 3B shows a second exemplary embodiment of the proposed buffer component. In this embodiment the second amplifier 51 comprises a third, a fourth and a fifth transistor T3, T4, T5, which are all realized as MOS transistors of the same type. Third and fourth transistors T3, T4 are connected by their drain terminals 23. A gate terminal of the third transistor T3 is connected to the output 22 of the first amplifier 20. A gate terminal of the fourth transistor T4 is connected to its drain terminal 23. A source terminal of the fourth transistor T4 is connected to a source terminal of the fifth transistor T5. A gate terminal of the fifth transistor is prepared to receive a reference voltage Vref. Respective source terminals 24 of the fourth and the fifth transistor T4, T5 are connected via a second current source Cs2 to the reference potential terminal 10. A drain terminal of the fifth transistor is connected via a third current source Cs3 to the supply potential terminal 11. The drain terminal of the third transistor T3 is coupled by the first current source Cs1 to the supply potential terminal 11. The output signal Vout is provided at the drain terminals 23 of the third and fourth transistors T3, T4.

[0099] In this exemplary embodiment the fourth transistor T4 representing the load to the third transistor T3 is biased via its source terminal 24 using the fifth transistor T5. Thereby, process, voltage, and temperature variations, PVT variations, of the fourth transistor 14 are compensated. The output signal Vout becomes independent of PVT variations.

[0100] The exemplary embodiment of FIG. 3B realizes an inverting buffer component, i.e. the output signal Vout is provided in its inverted form.

[0101] FIG. 3C shows a third exemplary embodiment of the buffer component. It comprises a sixth, a seventh, an eighth and a ninth transistor T6, T7, T8, T9 which are all realized as MOS transistors of the same type, here NMOS. The sixth and seventh transistors T6, T7 are connected by their source terminals. Said source terminals are coupled to the reference potential terminal 10 via a fourth current source Cs4. A gate terminal of the sixth transistor T6 is connected to the output 22 of the first amplifier 20. A drain terminal of the sixth transistor T6 is connected to a drain terminal of the seventh transistor T7 via a current mirror CM. A gate terminal of the seventh transistor T7 is prepared to receive the reference voltage Vref. A drain terminal 23 of the seventh transistor T7 is connected to a gate and a drain terminal of the eighth transistor T8. A source terminal of the eighth transistor T8 is connected to a source terminal of the ninth transistor T9. Said source terminals are further connected via a fifth current source Cs5 to the reference potential terminal 10. A gate terminal of the ninth transistor T9 is prepared to receive the reference voltage Vref. A drain terminal of the ninth transistor T9 is connected via a sixth current source Cs6 to the supply potential terminal 11. The output signal Vout is provided at the drain terminals 23 of the seventh and the eighth transistor T7, T8.

[0102] The sixth transistor T6 represents the input device of the second amplifier, while the eighth transistor T8 forms the output device. As the transistors T6 and T8 experience the same swing in their respective gate-source voltages and the same large signal operating point, nonlinearity is cancelled in this embodiment.

[0103] Regarding the dimensions of the current sources it is to be considered that first and fourth current source Cs1 and Cs4 determine the speed of the buffer component. So, the current is set high enough not to distort the waveform at the output of the first amplifier 20. The required current will be dependent on the load capacitance of the buffer component. The second, third, fifth and sixth current source Cs2, Cs3, Cs5 and Cs6 are dimensioned with respect the first and fourth current source Cs1 and Cs4 because they determine the transconductance gm2. Therefore, the currents provided by the current sources will be adjusted to provide the required voltage gain, i.e the ratio or quotient of the first transconductance gm1 and the second transconductance gm2.

[0104] FIG. 3D shows a fourth exemplary embodiment of a buffer component 50 as proposed. In the depicted embodiment the buffer component 50 comprises the second amplifier 51 and an RC divider 52. The second amplifier 51 is configured in feedback using the RC divider circuit 52. The RC divider circuit 52 comprises a first parallel connection having a first resistor R1 and a first capacitor C1 which are connected in parallel, and a second parallel connection having a second resistor R2 and a second capacitor C2, which are connected in parallel. The first parallel connection R1, C1 is coupled to an output of the second amplifier 51. The second parallel connection R2, C2 is connected in series to the first parallel connection R1, C1 and to the reference potential terminal 10. A connection point 53 between the first and the second parallel connection is connected to an input of the second amplifier 51. Optionally, the buffer component 50 in this embodiment also comprises a third capacitor C3 which is coupled between the reference potential terminal 10 and the RC divider circuit 52. The connection point 53 is, for instance, coupled to an inverting input of the second amplifier 51, while the non-inverting input of the second amplifier 51 is directly connected to the output 22 of the first amplifier 20.

[0105] The circuit elements of the RC divider circuit 52 are dimensioned to fulfil the following equation:

[00008]$\begin{array}{cc}\frac{R1}{R2}=\frac{C2}{C1}.& \left(10\right)\end{array}$

[0106] Therein, R1 represents the resistance of the first resistor R1, R2 represents the resistance of the second resistor R2, C1 represents the capacitance of the first capacitor C1 and C2 represents the capacitance of the second capacitor C2.

[0107] The depicted realization of the buffer component 50 achieves the following gain in dependency of the complex frequency jω:

[00009]$\begin{array}{cc}A\left(j\omega \right)\approx 1+\frac{R1.Math.\frac{1}{j\omega C1}}{R2.Math.\frac{1}{j\omega C2}}.& \left(11\right)\end{array}$

[0108] Therein, jω represents the complex frequency jω,R1 represents the resistance of the first resistor R1, R2 represents the resistance of the second resistor R2, C1 represents the capacitance of the first capacitor C1, C2 represents the capacitance of the second capacitor C2 and ∥ refers to the parallel connection of resistor R1 and capacitor C1, or of the resistor R2 and capacitor C2, respectively.

[0109] As can be seen, frequency dependency is further reduced.

[0110] As indicated on the side of FIG. 3D, each of first and second resistors R1, R2 may be implemented by a MOS resistor. Said MOS resistor comprises a tenth transistor T10, an eleventh transistor T11, a fourth capacitor C4 and a seventh current source Cs7. A gate terminal of the tenth transistor T10 is connected to a gate terminal of the eleventh transistor T11. The fourth capacitor C4 is connected between the gate terminal and a source terminal of the tenth transistor T10. The gate terminal of the eleventh transistor T11 is connected to a drain terminal of the eleventh transistor T11 and to the seventh current source Cs7. Said current source Cs7 is connected to the reference potential terminal 10 on the other side. A source terminal of the eleventh transistor T11 is connected to the supply potential terminal 11. The AC coupling implemented by the fourth capacitor C4 achieves that a gate-source voltage of the tenth transistor T10 remains mainly constant which minimizes overdrive variation.

[0111] FIG. 4 shows an exemplary embodiment of the proposed photon counting circuit. The photon counting circuit comprises a sensor 60 configured to detect one or more photons and to convert each photon into a current pulse. The photon counting circuit further comprises the shaper circuit 20 which conforms to the shaper circuit according to one of the embodiments described above, an analog-to-digital converter, ADC, 80 and a counter component 90. The shaper circuit 70 is connected to an output of the sensor 60 and receives the input signal Iin from the sensor 60. The ADC 80 is configured to receive the output signal Vout of the shaper circuit 70 and to provide a digital value for each of the received voltage pulses. The digital value thereby depends on the height of a converted voltage pulse. The counter component 90 is coupled downstream of the ADC 80. The counter component 90 is configured to count the digital values.

[0112] The ADC 80 may be realized by an asynchronously flash ADC comprising a number of comparators as indicated in FIG. 4. The counter component 90 may comprise a number of counters as indicated in FIG. 4, the number of counters matching the number of comparators of the flash ADC. In an implementation example, the shaper circuit 70, the ADC 80 and the counter component 90 are realized as an integrated circuit, for example as a complementary MOS, CMOS, integrated circuit. The sensor 60 is connected to said integrated circuit. Due to the realization of the shaper circuit 70 as described above, the influence of external routing traces from the sensor to the shaper circuit 70, especially its parasitic capacitance is greatly reduced. The shaper circuit 70 may also be designated as a CMOS frontend, or as an analog frontend for photon counting. As the shaper circuit 70 generates sharp voltage pulses which are provided with the output signal Vout to the ADC 80, performance of the integrated circuit is greatly improved compared with state of the art implementations.

[0113] FIG. 5 shows an exemplary embodiment of an X-ray apparatus as proposed. The X-ray apparatus 100 comprises at least one photon counting circuit 110 which complies with the photon counting circuit as described above. By using the photon counting circuit as proposed in this application, the X-ray apparatus is enabled to provide pictures with higher quality.

[0114] The X-ray apparatus may also be realized as a computed tomography apparatus.

[0115] It will be appreciated that the disclosure is not limited to the disclosed embodiments and to what has been particularly shown and described hereinabove. Rather, features recited in separate dependent claims or in the description may advantageously be combined. Furthermore, the scope of the disclosure includes those variations and modifications, which will be apparent to those skilled in the art. The term “comprising”, insofar it was used in the claims or in the description, does not exclude other elements or steps of a corresponding feature or procedure. In case that the terms “a” or “an” were used in conjunction with features, they do not exclude a plurality of such features. Moreover, any reference signs in the claims should not be construed as limiting the scope.