Image element and method for operating an image element

Abstract

An image element is disclosed having first and second supply terminals, a light emitting semiconductor component, a driver circuit comprising a driver transistor, a storage capacitor, and a switching transistor, and a trigger circuit comprising an output transistor and a control capacitor. The light emitting semiconductor component and the driver transistor are arranged in series with each other and between the first supply terminal and the second supply terminal. A first electrode of the storage capacitor is coupled to a control terminal of the driver transistor. The switching transistor is configured to switch on and off a current flow through the light emitting semiconductor component. A first electrode of the control capacitor is connected to a control terminal of the output transistor. A first terminal of the output transistor is connected to a control terminal of the switching transistor. Furthermore, a method for operating an image element, in particular such an image element, is disclosed.

Claims

1. An image element, comprising a first and a second supply terminal, a light emitting semiconductor component, a driver circuit comprising a driver transistor, a storage capacitor and a switching transistor, and a trigger circuit comprising an output transistor and a control capacitor, wherein the light emitting semiconductor component and the driver transistor are arranged in series with each other and between the first supply terminal and the second supply terminal, wherein a first electrode of the storage capacitor is coupled to a control terminal of the driver transistor, wherein the switching transistor is configured to switch on and off a current flow through the light emitting semiconductor component, wherein a first electrode of the control capacitor is connected to a control terminal of the output transistor, and wherein a first terminal of the output transistor is connected to a control terminal of the switching transistor.

2. The image element according to claim 1, wherein a second electrode of the control capacitor is coupled to the first supply terminal and a second terminal of the output transistor is coupled to the first supply terminal.

3. The image element according to claim 1, wherein the trigger circuit comprises an output resistor coupled to the first terminal of the output transistor and to the second supply terminal.

4. The image element according to claim 1, wherein the trigger circuit comprises a control resistor coupled to the first and second electrodes of the control capacitor.

5. The image element according to claim 1, comprising a control transistor with a first terminal coupled to a control signal input of the image element, a second terminal coupled to the first electrode of the control capacitor, and a control terminal coupled to a selection input of the image element.

6. The image element according to claim 5, comprising a selection transistor with a first terminal coupled to a signal input of the image element, a second terminal coupled to the first electrode of the storage capacitor, and a control terminal coupled to the selection input of the image element.

7. The image element according to claim 5, comprising a selection transistor with a first terminal coupled to the control signal input of the image element, a second terminal coupled to the first electrode of the storage capacitor, and a control terminal coupled to a further selection input of the image element.

8. The image element according to claim 1, wherein a first terminal of the driver transistor is coupled to the first supply terminal, wherein a second electrode of the storage capacitor is coupled to the first supply terminal, and wherein the light emitting semiconductor component is coupled to the second terminal of the driver transistor and to the second supply terminal.

9. The image element according to claim 1, wherein the switching transistor couples the first electrode of the storage capacitor to the first supply terminal.

10. The image element according to claim 1, wherein the switching transistor is arranged in series with the light emitting semiconductor component and the driver transistor, such that the light emitting semiconductor component, the switching transistor and the driver transistor are arranged between the first supply terminal and the second supply terminal.

11. The image element according to claim 1, wherein the driver transistor, the switching transistor and the output transistor are produced as thin film transistors.

12. The image element according to claim 1, wherein the driver transistor, the switching transistor and the output transistor are realized as n-channel field effect transistors, or the driver transistor, the switching transistor and the output transistor are realized as p-channel field effect transistors.

13. A display device comprising a plurality of image elements according to claim 1, which are arranged in rows and columns in a matrix-like manner, a plurality of column lines, each connected to a respective signal input of the image elements of one of the columns, a plurality of further column lines, each connected to a respective control signal input of the image elements of one of the columns, a plurality of row lines each connected to a respective selection input of the image elements of one of the rows, and a control device connected on the output side to the plurality of column lines, the plurality of further column lines and the plurality of row lines.

14. A method for operating an image element, comprising applying a supply voltage between first and second supply terminals, the supply voltage dropping across a series circuit comprising a light emitting semiconductor component and a driver transistor, supplying a current setting voltage to a storage capacitor, wherein a first electrode of the storage capacitor is coupled to a control terminal of the driver transistor, supplying a trigger setting voltage to a control capacitor, wherein a first electrode of the control capacitor is coupled to a control terminal of an output transistor, providing an output signal by the output transistor, and turning on and/or turning off a current flow through the light emitting semiconductor component by a switching transistor controlled by the output signal.

15. The method according to claim 14, wherein a capacitor voltage applied to the control capacitor changes after the trigger setting voltage is applied, such that the value of the output signal is changed and therefore the current flow is either turned on or turned off.

16. The method according to claim 15, wherein the capacitor voltage changes due to self-discharge of the control capacitor after the trigger setting voltage is applied.

17. An image element, comprising a first and a second supply terminal, a light emitting semiconductor component, a driver circuit comprising a driver transistor, a storage capacitor and a switching transistor, and a trigger circuit comprising an output transistor and a control capacitor, wherein the light emitting semiconductor component and the driver transistor are arranged in series with each other and between the first supply terminal and the second supply terminal, wherein a first electrode of the storage capacitor is coupled to a control terminal of the driver transistor, wherein the switching transistor is configured to switch on and off a current flow through the light emitting semiconductor component, wherein a first electrode of the control capacitor is connected to a control terminal of the output transistor, wherein a first terminal of the output transistor is connected to a control terminal of the switching transistor, and wherein the trigger circuit comprises a control resistor coupled to the first and second electrodes of the control capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further embodiments and further embodiments of the image element or of the method for operating an image element result from the exemplary embodiments explained below in connection with FIGS. 1 to 6. Identical, similar or identically acting circuit parts and components are provided with the same reference signs in the figures. They show:

(2) FIG. 1 an example of an image element;

(3) FIGS. 2A to 2G an exemplary embodiment of an image element and signal waveforms;

(4) FIGS. 3A to 3G a further exemplary embodiment of an image element and signal waveforms;

(5) FIGS. 4A to 4C additional exemplary embodiments of an image element;

(6) FIG. 5 an alternative exemplary embodiment of a detail of an image element; and

(7) FIG. 6 an exemplary embodiment of a display device.

DETAILED DESCRIPTION

(8) FIG. 1 shows an example of an image element 10 with a first and a second supply terminal 11, 12, a light emitting semiconductor component 13 (abbreviated as semiconductor component in the following) and a driver circuit 14. The first supply terminal 11 may be realized as a voltage supply terminal. The second supply terminal 12 may be designed as a reference potential terminal. The semiconductor component 13 is realized as a light emitting diode, abbreviated as LED. The LED may be produced as a μLED or as a high-power LED. The driver circuit 14 comprises a driver transistor 16. The driver transistor 16 is connected in series with the semiconductor component 13. A series circuit comprising the driver transistor 16 and the semiconductor component 13 couples the first supply terminal 11 to the second supply terminal 12, with the driver transistor 16 connected to the first supply terminal 11 and the semiconductor component 13 connected to the second supply terminal 12.

(9) In addition, the driver circuit 14 comprises a storage capacitor 17. A first electrode of the storage capacitor 17 is connected to a control terminal of the driver transistor 16. A second electrode of the control capacitor 17 is connected to the first supply terminal 11. A first terminal of the driver transistor 16 is connected to the first supply terminal 11. A second terminal of the driver transistor 16 is coupled to the second supply terminal 12 via the semiconductor component 13.

(10) In addition, the image element 10 comprises a selection transistor 20. Further, the image element 10 comprises a signal input 21. The signal input 21 is coupled to the first electrode of the storage capacitor 17 via the selection transistor 20. A control terminal of the selection transistor 20 is connected to a selection input 22 of the image element 10. The signal input 21 is connected to a first column line 23. Accordingly, the control input 22 is connected to a first row line 24.

(11) A supply voltage VDD is applied to the first supply terminal 11. The supply voltage VDD can be positive. A reference potential GND can be tapped at the reference potential terminal 12. A current IL flows through the driver transistor 16 and the semiconductor component 13. A current setting voltage VDATA is applied to the first column line 23 and thus to the signal input 21. A selection signal VSCAN is applied to the first row line 24 and thus to the selection input 22. When the selection signal VSCAN makes the selection transistor 20 conductive, the current setting voltage VDATA is supplied from the first column line 23 via the signal input 21 and the selection transistor 20 to the first electrode of the storage capacitor 17 and the control terminal of the driver transistor 16. Subsequently, the selection transistor 20 is switched to non-conducting by the selection signal VSCAN. Thus, a storage voltage VS is applied between the first electrode and the second electrode of the storage capacitor, which can be calculated according to the following equation:
VS=VDD−VDATA,

(12) where VDD is a value of the supply voltage and VDATA is a value of the current setting voltage. Thus, the storage voltage VS is applied, for example, between a source terminal and a gate terminal of the driver transistor 16. More generally, it may be true, for example:
|VS|=|VDD−VDATA|

(13) Consequently, the storage voltage VS determines a value of the current flow IL. According to this example, a brightness of the image element can be preset by setting the value of the current flow IL.

(14) The circuit of the image element 10, also called pixel cell or cell, in an active matrix μLED display device are based on a so-called 2T1C cell illustrated in FIG. 1. A mode of operation is as follows: Each image element 10 has driver transistor 16, selection transistor 20 and storage capacitor 17. The transistors 16, 20 may be realized as thin film transistors (abbreviated as TFT). A line of a display device (shown in FIG. 6) is selected via the selection signal VSCAN. The storage voltage VS on the storage capacitor 17 can be programmed via the current setting voltage VDATA. The storage capacitor 17 is programmed once per frame and holds the storage voltage VS until the next programming. The control terminal of driver transistor 16 is connected to storage capacitor 17, a source terminal of driver transistor 16 is connected to supply voltage VDD, and a drain terminal of driver transistor 16 is connected to reference potential GND (via semiconductor component 13). A constant current flow IL is generated via the constant voltage at the control terminal of the driver transistor 16, which flows through the semiconductor component 13 realized as a μLED. The brightness of the semiconductor component 13 is controlled by the current flow IL. The regulation of the current flow IL and thus of the brightness is analogous.

(15) The transistors 16, 20 of the image element 10 are realized as PMOS transistors. Since there is a dependency between color location and current in μLEDs, changes in the white point can occur in pure analog operation.

(16) FIG. 2A shows an exemplary embodiment of an image element 10 which is a further development of the embodiment shown in FIG. 1. The driver circuit 14 comprises the driver transistor 16 shown in FIG. 1 and the storage capacitor 17. In addition, the driver circuit 14 comprises a switching transistor 30 that couples the control terminal of the driver transistor 16 to the first supply terminal 11. Thus, the switching transistor 30 couples the first electrode of the storage capacitor 17 to the second electrode of the storage capacitor 17.

(17) In addition, the image element comprises a trigger circuit 31 connected on the output side to a control terminal of the switching transistor 30. The trigger circuit 31 is designed to be monostable, for example. The trigger circuit 31 may be realized in a post-triggerable manner. The trigger circuit 31 may be implemented as a monostable trigger circuit stage, monoflop or univibrator. The trigger circuit 31 comprises an output transistor 33 and a control capacitor 34. Further, the flip circuit 31 comprises an output resistor 35 coupling a first terminal of the output transistor 33 to the second supply terminal 12. A control terminal 35 of the output transistor 33 is coupled to a second terminal of the output transistor 33 via the control capacitor 34. The second terminal of the output transistor 33 is connected to the first supply terminal 11.

(18) Further, the trigger circuit 31 comprises a control resistor 36 that couples the first terminal of the control capacitor 34 to the second terminal of the control capacitor 34. Thus, the control resistor 36 couples the control terminal of the output transistor 33 to the second terminal of the output transistor 33.

(19) In addition, the image element 10 comprises a control transistor 40. At a first terminal, the control transistor 40 is connected to a control signal input 41. At a second terminal, the control transistor 40 is connected to the control input of the output transistor 33. A control terminal of the control transistor 40 is connected to the selection input 22. Thus, the control terminal of the control transistor 40 is coupled to the control terminal of the selection transistor 20. A voltage source 42 is arranged between the first and second supply terminals 11, 12 (the voltage source 42 may, for example, be a part of the display device 50 shown in FIG. 6).

(20) The voltage source 42 outputs the supply voltage VDD. An output signal VA can be tapped at a node between the output transistor 33 and the output resistor 35. The output signal VA is supplied to the control terminal of the switching transistor 30. The selection signal VSCAN is supplied to both the control terminal of the control transistor 40 and the control terminal of the selection transistor 20. When the control transistor 40 is rendered conductive, a trigger setting voltage VPWM is applied to the first electrode of the control capacitor 34 and the control terminal of the output transistor 33 via the control signal input 41 of the image element 10 and the control transistor 40. A capacitor voltage VK drops across the control capacitor 34, which can be calculated, for example, according to the following equation:
VK=VDD−VPWM,

(21) where VDD is a value of the supply voltage and VPWM is a value of the trigger setting voltage. More generally, it may be true, for example:
|VK|=|VDD−VPWM|

(22) During turn-on of the control transistor 40 and immediately thereafter, the capacitor voltage VK satisfies the above equation. Due to a current flow through the control resistor 36, the capacitor voltage VK decreases and thus a control voltage VG applied to the control terminal of the output transistor 33 increases:
VG=VDD−VK

(23) The control voltage VG can reach the value of the supply voltage VDD at maximum. The driver transistor 16, the switching transistor 30 and the output transistor 33 are implemented as P-channel field effect transistors. At a low value of the trigger setting voltage VPWM and thus a low initial value of the control voltage VG, the output transistor 33 is conductive. When the value of the control voltage VG is low, the output signal VA is high, so that the switching transistor 30 is non-conducting. The semiconductor component 13 is illuminated. The current flow IL through the semiconductor component 13 is adjusted by the storage voltage VS.

(24) When the control voltage VG rises due to the current flowing through the control resistor 36, the output transistor 33 changes from a conductive state to a non-conductive state so that the output signal VA returns to the value of the second supply terminal 12 and thus to the reference potential GND. As a result, the switching transistor 30 becomes conductive and short-circuits the storage capacitor 30. As a result, the driver transistor 16 is switched non-conducting.

(25) The processes are repeated periodically with a specified time duration T. Thus, the value of the trigger setting voltage VPWM determines the time within the time duration T at which the driver transistor 16 is switched from the conductive state to the non-conductive state. Consequently, a brightness of the semiconductor component 13 and thus a brightness of the image element 10 depends on a value of the current setting voltage VDATA and on a value of the trigger setting voltage VPWM.

(26) To keep a color location constant at different brightness levels, the brightness of the image element 10, referred to as a sub-pixel, can be adjusted using pulse width modulation (abbreviated PWM). The image element 10 is operated digitally. The image element 10 is operated exclusively for a certain time at the nominal current and remains off the remainder of the time. The average brightness over time is perceived by the viewer as the static brightness of the image element 10. Advantageously, the number of transistors and capacitors required is kept low.

(27) The image element 10 is implemented in such a way that a circuit in the image element 10 generates the pulse width modulation itself. This circuit consists exclusively of five transistors and two capacitors. The image element 10 can therefore be manufactured compactly, effectively achieving a high resolution.

(28) The image element 10 realizes the following concept: the transistors 16, 20 form the 2T1C cell. The 2T1C cell is extended by the control capacitor 34 and three transistors 30, 33, 40. The resistors 35, 36 are additional components to extend the 2T1C cell.

(29) The trigger setting voltage VPWM is programmed on the control capacitor 34 via a further column line (also called scan line). During the frame time, the control capacitor 34 discharges via the control resistor 36. If the voltage at the control capacitor 34 falls below a certain value, the μLED 13 in the image element 10 is switched off. The time during which the μLED 13 lights up can be controlled via the trigger setting voltage VPWM.

(30) The control capacitor 34 and the control resistor 36 form a low-pass or resistive-capacitive (abbreviated as RC) element. A threshold voltage VTH of the transistors 13, 20, 30, 33, 40 of the image element 10 is negative, for example, it is about −2V. The transistors 13, 20, 30, 33, 40 of the image element 10 are self-blocking. The transistors 13, 20, 30, 33, 40 of the image element 10 are realized as metal-oxide-semiconductor field-effect transistors, abbreviated MOSFET.

(31) A mode of operation of the image element 10 is as follows: A line is selected with the selection signal VSCAN. The current setting voltage VDATA is used to program the storage capacitor 17 via the signal input 21, which causes a constant current flow IL through the driver transistor 16. The trigger setting voltage VPWM is used to program the control capacitor 34 via the control signal input 41, with the control terminal of the output transistor 33 connected to the control capacitor 34. Thus, immediately after programming, the control voltage VG is equal to the trigger setting voltage VPWM; VG=VPWM. The control capacitor 34 is discharged within one frame through the control resistor 36. The output transistor 33 is conducting as long as VG<VDD+VTH holds, so the switching transistor 30 is non-conducting (VTH is a threshold voltage of the output transistor 33).

(32) When the output transistor 33 becomes non-conductive, the control terminal of the switching transistor 30 is pulled to the reference potential GND via the output resistor 35.

(33) When the output transistor 33 becomes conductive, the control terminal of the switching transistor 30 is pulled to the supply voltage VDD via the output transistor 33. When this happens, the driver transistor 16 becomes non-conductive and the semiconductor component 13 (such as a μLED) turns off.

(34) The product of the resistance value R1 of the control resistor 36 and the capacitance value C1 of the control capacitor 34 gives a time constant Tau (Tau=R1.Math.C1 or Tau˜R1˜C1). For example, the components could be designed as follows: The time constant Tau corresponds approximately to a frame time: This results in a full PWM control effect due to the discharge of the control capacitor 34 via the control resistor 36. Alternatively: Time constant Tau>>frame time T: This results in a longer discharge, which leads to a small control range. Alternatively, time constant Tau<<frame time T: This results in a fast discharge, such that the semiconductor component 13 switches off even if VPWM=0 in the frame.

(35) FIGS. 2B to 2F show exemplary embodiments of signal waveforms of the image element 10 according to FIG. 2A. FIGS. 2B to 2F show the control voltage VG of the output transistor 33, the trigger setting voltage VPWM, the supply voltage VDD, a sum voltage VDD+VTH, and the current flow IL as a function of a time t. The values of the current flow IL were simulated for different trigger setting voltages VPWM (at a supply voltage VDD=10V). The processes can be repeated with the time duration T. The time duration T corresponds to a frame time. In FIG. 2B, the trigger setting voltage VPWM is at 0 Volts. Thus, the control voltage VG at the control terminal of the output transistor 33 starts at 0 Volts and increases. However, since the control voltage VG does not reach the value of a sum voltage VDD+VTH, the output transistor 33 is permanently conducting. The current flow IL is almost constant at a high value.

(36) According to FIG. 2C, the trigger setting voltage VPWM has the value VPWM=0.4.Math.VDD. The control voltage VG of the output transistor 33 thus increases from this value to a value above the sum voltage, so that at a time t1 the output transistor 33 is switched non-conducting, the switching transistor 30 is switched conducting and the driver transistor 13 is switched non-conducting. From this time t1, the current flow IL takes the value 0; the current flow IL does not take a high value again until the beginning of the next time period T.

(37) According to FIG. 2D, the trigger setting voltage VPWM has the value VPWM=0.5.Math.VDD. The time t1 is reached faster.

(38) According to FIG. 2E, the trigger setting voltage VPWM has the value VPWM=0.6.Math.VDD. The time t1 of the switchover is reached even earlier.

(39) According to FIG. 2F, the trigger setting voltage VPWM has the value VPWM=0.9.Math.VDD. The trigger setting voltage VPM is above the value of the sum voltage. Thus, the output transistor 33 is continuously non-conducting and the switching transistor 30 is continuously conducting. Since the driver transistor 16 is thus continuously non-conducting, the current flow IL is at the value 0.

(40) FIG. 2G shows an exemplary dependence between the trigger setting voltage VPWM and a duty cycle D of the image element 10 according to FIG. 2A. The duty cycle D (also called PWM duty cycle) is indirectly proportional to the trigger setting voltage. By varying the trigger setting voltage VPWM, duty cycles D between 0 and 1 or between 0% and 100% can be achieved. The resolution of the pulse width modulation (abbreviated PWM) depends on the design of the RC element, formed by the control capacitor 34 and the control resistor 36, and on the accuracy with which the trigger setting voltage VPWM can be programmed. FIG. 2G shows the relationship between VPWM and the resulting duty cycle for a frame time T˜1.5.Math.Tau and the supply voltage VDD=10V. The trigger setting voltage VPWM shows an effective control action in the range from 1V to 8V. The relationship between the trigger setting voltage VPWM and the duty cycle D is not linear.

(41) FIG. 3a shows a further exemplary embodiment of an image element 10, which is a further development of the embodiments shown in FIGS. 1A and 2A. According to FIG. 3A, the switching transistor 30 is arranged between the semiconductor component 13 and the driver transistor 16. A series circuit comprising the driver transistor 16, the switching transistor 30 and the semiconductor component 13 couples the first supply terminal 11 to the second supply terminal 12. Thus, the current flow IL flows through the driver transistor 16, the switching transistor 30 and the semiconductor component 13. At the beginning of a time period T, the switching transistor 30 is rendered non-conducting by the output signal VA. That is, at the beginning of the time period T, no current flows through the semiconductor component 13. At the time t1, a current flow through the control resistor 36 has reduced the capacitor voltage VK, so that the switching transistor 30 is made conductive by means of the output signal VA, and consequently the current flow IL flows through the above series circuit. The magnitude of the current flow IL is thereby predetermined by the storage voltage VS applied to the storage capacitor 17.

(42) For example, the operation of the image element 10 is: A line is selected with the selection signal VSCAN. The storage capacitor 17 is programmed with the current setting voltage VDATA. No current IL flows through the semiconductor component 13 as long as the switching transistor 30 is non-conducting. The control capacitor 34 is programmed via the trigger setting voltage VPWM; the control terminal of the output transistor 33 is connected to the control capacitor 34; this initially results in VG=VPWM. The control capacitor 34 is discharged within one frame through the control resistor 36. The output transistor 33 is conductive as long as VG<VDD+VTH holds (VTH is the threshold voltage of the output transistor 33). As long as the output transistor 33 is conducting, the switching transistor 30 is non-conducting. If the output transistor 33 becomes non-conducting, the control terminal of the switching transistor 30 is pulled to the reference potential GND via the output resistor 35. When the output transistor 33 becomes conductive, a constant current IL can flow through the semiconductor component 13 realized as μLED.

(43) The component design is similar to FIG. 2A, with one difference: if the time constant Tau<<frame time T, the result is a fast discharge, so that the semiconductor component 13 is turned on even when the trigger setting voltage VPWM=0 in the frame.

(44) FIGS. 3B to 3F show the signals of the image element 10 for the following values of the trigger setting voltage VPWM (simulated results of the current flow IL at VDD=10V): In FIG. 3B the following applies: VPWM=0V In FIG. 3C the following applies: VPWM=0.5.Math.VDD In FIG. 3D the following applies: VPWM=0.7.Math.VDD In FIG. 3E the following applies: VPWM=0.8.Math.VDD In FIG. 3F the following applies, VPWM=0.9.Math.VDD

(45) FIG. 3G shows an example of a dependence of the duty cycle D on the trigger setting voltage VPWM for a frame time T˜1.5.Math.Tau and a supply voltage VDD=10V. The PWM duty cycle D can be directly proportional to the trigger setting voltage VPWM. By varying the trigger setting voltage VPWM, duty cycles between 0% and 100% can be achieved. The trigger setting voltage VPWM has an effective control effect in the range from 1V to 8V. The relationship between the trigger setting voltage VPWM and the duty cycle D is not linear.

(46) The exemplary embodiments of the image element 10 according to FIG. 2A and according to FIG. 3A differ somewhat in their characteristics. The image element 10 shown in FIG. 2A has the advantage of fast switching performance due to the triple amplification of the trigger setting signal VPWM. However, the storage capacitor 17 may possibly be discharged via a leakage current through the switching transistor 30, which may cause the current flow IL (also called analog current level of the μLED) to change during a frame.

(47) The advantage of the image element 10 according to FIG. 3A is that there is no discharge of the storage capacitor 17 via an additional transistor and thus a constant current flow IL is achieved during a frame. However, the switching behavior may be slower, since only a double amplification of the trigger setting signal VPWM is obtained.

(48) The exemplary embodiments of the image element 10 according to FIGS. 2A and 3A can both be implemented with standard active matrix drivers. There are two possible concepts here: The image element 10 comprises a selection input 22 with associated row line 24 (for switching through the current setting voltage VDATA and the trigger setting voltage VPWM) and two signal inputs 21, 42 with associated column lines (one each for the current setting voltage VDATA and the trigger setting voltage VPWM); this is shown in FIGS. 2A and 3A. Alternatively, the image element 10 comprises two selection inputs 22 with associated row lines 24 (one each for the current setting voltage VDATA and for the trigger setting voltage VPWM) and a control signal input 41 with an associated column line 23 (together for providing the current setting voltage VDATA and the trigger setting voltage VPWM).

(49) The common control signal input 41 and the common column line 23 are used in a multiplexing method (see also FIG. 5).

(50) In one example, the time constant Tau is chosen to correspond approximately to the target frame time T.

(51) FIG. 4A shows an alternative exemplary embodiment of an image element 10 that is a further development of the embodiments shown in FIGS. 1, 2A and 3A. The image element 10 is free of the control resistor 36, that is, the image element 10 is free of any resistor coupling the first electrode of the control capacitor 34 to the second electrode of the control capacitor 34. The control capacitor 34 is discharged by a parasitic resistor within the control capacitor 34. The control capacitor 34 is configured as a high self-discharge capacitor. This can be achieved, for example, by selecting a suitable material for the insulator of the control capacitor 34. Thus, it is possible to dispense with the control resistor 36.

(52) FIG. 4B shows an alternative exemplary embodiment of an image element 10, which is a further development of the embodiments shown above. Here, the transistors such as the driver transistor 16, the switching transistor 30, the output transistor 33, the selection transistor 20 and the control transistor 40 are realized as n-channel field effect transistors. The first supply terminal 11 is realized as a reference potential terminal and the second supply terminal 12 is realized as a voltage supply terminal. The second supply terminal 12 is thus at a higher potential than the first supply terminal 11. A supply voltage VA1 can be tapped at the voltage source, which has the same magnitude as the supply voltage VDD but the opposite sign to the supply voltage VDD. The supply voltage VDD is negative. In contrast to FIGS. 1, 2A and 3A, the voltages and signals here are referenced to the potential of the first supply terminal 11.

(53) The threshold voltage VTH of the above transistors 16, 30, 33, 20, 40 is positive; it can be e.g. 2V. The transistors 16, 30, 33, 20, 40 are self-blocking.

(54) The operation of the image element 10 is similar to that shown in FIGS. 2A and 3A. However, the output transistor 33 is conductive as long as VG>VTH; thereby, the switching transistor 30 is non-conductive.

(55) In one example, the current setting voltage VDATA and the trigger setting voltage VPWM may be voltages referenced to the second supply terminal 12; therefore, for example, some of the above equations may apply. Alternatively, the current setting voltage VDATA and the trigger setting voltage VPWM may be voltages referenced to the first supply terminal 11; therefore, for example, the following equations may apply:
VS=−VDATA or |VS|=|VDATA|
VK=−VPWM or |VK|=|VPWM|

(56) FIG. 4C shows an additional exemplary embodiment of an image element 10 which is a further development of the embodiments shown above. Here, too, the transistors 16, 30, 33, 20, 40 are realized as n-channel field-effect transistors (as also in FIG. 4B). Further, the image element 10 is realized without a control resistor 36 (as also shown in FIG. 4A).

(57) FIG. 5 shows an alternative exemplary embodiment of a detail of an image element 10, which is a further development of the embodiments shown above. The image element 10 comprises the control transistor 40 and the selection transistor 20, as already shown in the above figures. However, in FIG. 5, both the first terminal of the control transistor 40 and the first terminal of the selection transistor 20 are connected to the control signal input 41 of the image element 10. The control terminal of the control transistor 40 is connected to the selection input 22 of the image element 10. On the other hand, the control terminal of the selection transistor 20 is connected to a further selection input 43 of the image element 10. Thus, the image element 10 has two digital inputs, namely a selection input 22 and a further selection input 43, and one analog input, namely the control signal input 41. At a time when the current setting voltage VDATA is applied to the control signal input 41, the selection transistor 20 is rendered conductive. At a further point in time when the trigger setting voltage VPWM is applied to the control signal input 41, the control transistor 40 is switched to conductive by means of a further selection signal VSCAN2. This means that the current setting voltage VDATA and the trigger setting voltage VPWM are supplied one after the other with a time delay.

(58) FIG. 6 shows an exemplary embodiment of a display device 50 with an image element 10, which can be implemented according to the exemplary embodiments shown above. The display device 50 is realized as a display, in particular as an active matrix display. The display device 50 implements an array of image elements 10, 51 to 58. The light emitting semiconductor component 13 (abbreviated as semiconductor component) is produced as a light emitting diode, in particular as a micro light emitting diode, abbreviated as μLED. The μLED may, for example, be made of indium gallium nitride InGaN. The display device 50 comprises a first number N of columns and a second number M of rows. In FIG. 6, the first and the second number N=M=3. The display device 50 thus comprises N×M image elements 10, 51 to 58, which may be realized according to one of the exemplary embodiments shown above.

(59) The display device 50 comprises a first number N of column lines 23, 61, 62 and a second number M of row lines 24, 64, 65. The column lines 23, 61, 62 are each connected to a respective signal input 21 of the image elements 10, 51 to 58 of one of the columns. Accordingly, the row lines 24, 64, 65 are each connected to a respective selection input 22 of the image elements 10, 51 to 58 of one of the rows. Additionally, the display device 50 comprises a first number N of further column lines 67 to 69. The further column lines 67 to 69 are each connected to a respective control signal input 41 of the image elements 10, 51 to 58 of one of the columns. Further, the display device 50 comprises a control device 70 connected to the first number N of column lines 23, 61, 62, the first number N of further column lines 67 to 69 and the second number M of row lines 24, 64, 65. In addition, the display device 50 comprises the voltage source 42 connected to the image elements 10, 51 to 58 via lines not shown.

(60) The control device 70 generates a first number N of current setting voltages VDATA, VDATA′, VDATA″ and a first number N of trigger setting voltages VPWM, VPWM′, VPWM″ and provides this to the first number N of column lines 23, 61, 62 and the first number N of further column lines 67 to 69. On a pulse on one of the second number M of row lines 24, 64, 65, the current setting voltages VDATA, VDATA′, VDATA″ as well as the trigger setting voltages VPWM, VPWM′, VPWM″ are taken from bit cells 10, 51 to 58 of the selected row.

(61) The invention is not limited to the exemplary embodiments by the description of the invention based on the exemplary embodiments. Rather, the invention comprises any new feature as well as any combination of features, which in particular includes any combination of features in the claims, even if that feature or combination itself is not explicitly recited in the claims or exemplary embodiments.