MULTI-TUNE FILTER AND CONTROL THEREFOR

Abstract

A multi-tune filter system and a control system for operating the multi-tune filter system are described herein. The multi-tune filter system is a tunable frequency range filter. Further, the multi-tune filter system is a digitally programmable filter with an adjustable passband between first and second customizable frequency bounds f1, f2.

Claims

1. A multi-tune filter system, the filter system having a frequency range filter having a filter topology comprising: a first frequency and a second frequency, where the first frequency is lower than the second frequency; and a third frequency which is greater than the first frequency and lesser than the second frequency, wherein each of the first frequency and the second frequency are selected from the range consisting of 1.5 MHz to 30 Mhz, and wherein the third frequency is equal to one half the sum of the first frequency and the second frequency, and at least one elliptic Cauer-Chebyshev topology implemented with a minimum of two capacitors.

2. (canceled)

3. The multi-tune filter system of claim 1, wherein the first, second, and third frequencies are variable in 100 KHz increments.

4. The multi-tune filter system of claim 1, further comprising a low pass filter topology and a high pass filter topology.

5. The multi-tune filter system of claim 4, wherein the low pass filter topology comprises first, second, and third digital low pass filter legs.

6. The multi-tune filter system of claim 5, wherein the high pass filter topology comprises first, second, and third digital high pass filter legs.

7. The multi-tune filter system of claim 6, wherein at least one of the first, second, and third digital low pass filter legs and at least one of the first, second, and third, digital high pass filter legs are variable and dependent on the third frequency.

8. A method of controlling a multi-tune filter, comprising: selecting a center frequency; setting first and second frequency values equidistant from the center frequency, manipulating a plurality of impedance transformers and a plurality of radio frequency switches, wherein manipulation of the plurality of impedance transformers and plurality of radio frequency switches adjust the first and second frequency values.

9. The method of controlling the multi-tune filter of claim 8, wherein the plurality of impedance transformers and plurality of radio frequency switches are manipulated to change a digital signal.

10. The method of controlling the multi-tune filter of claim 9, wherein the first and second frequency values are respectively determined by a high pass filter leg and a low pass filter leg of the multi-tune filter.

11. (canceled)

12. The method of controlling the multi-tune filter of claim 10, wherein the first and second frequency values correspond to a plurality of impedances, the plurality of impedances derived from the low pass filter leg and the high pass filter leg respectively.

13. The method of controlling the multi-tune filter of claim 12, wherein each of the high pass filter leg and the low pass filter leg comprise nine frequency subranges.

14. A multi-tune filter control system, comprising: a first frequency limit at 1.5 MHz and a second frequency limit at 30 MHz; a first frequency and a second frequency, each of the first and second frequencies being selected within a frequency range defined by the first and second frequency limits; a center frequency between the first and second frequencies; an adjustable passband filter implemented between the first and second frequencies; wherein the first and second frequencies are adjustable through manipulation of the plurality of impedance transformers and plurality of radio frequency switches, and the filter control system further manipulates at least one elliptic Cauer-Chebyshev topology implemented with a minimum of two capacitors.

15. The multi-tune filter control system of claim 14, wherein the first frequency is derived from a plurality of low pass filters and the second frequency is derived from a plurality of high pass filters.

16. The multi-tune filter control system of claim 15, wherein a first digital control signal manipulates the plurality of low pass filters and a second digital control signal manipulates the plurality of high pass filters, and wherein the first and second digital control signals represent the selected first and second frequencies.

17. The multi-tune filter control system of claim 16, wherein one or more of the plurality of low pass filters and one or more of the plurality of high pass filters act on an incoming signal to implement the first frequency bound, the second frequency bound, and the center frequency, transforming the incoming signal to a filtered signal.

18. (canceled)

19. (canceled)

20. The multi-tune filter control system of claim 17, wherein the plurality of low pass filters and the plurality of high pass filters are digitally tuned to implement a center frequency equidistant from each of the first and second frequencies.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are included to provide further understanding and are incorporated in and constitute a part of this specification, illustrate disclosed embodiments and together with the description serve to explain the principles of the disclosed embodiments. In the drawings:

[0022] FIG. 1 is a block diagram of a multi-tune filter system and control therefor;

[0023] FIG. 2 graphically represents the tunable frequency range of the multi-tune filter of FIG. 1;

[0024] FIG. 3 is a diagram of a multi-tune filter system;

[0025] FIG. 4 is a diagram of first, second, and third high pass filter legs of the multi-tune filter system;

[0026] FIG. 5 is a diagram of first, second, and third low pass filter legs of the multi-tune filter system;

[0027] FIGS. 6-10 are exemplary frequency graphs of frequency ranges in which the multi-tune filter system operates;

[0028] FIG. 11 is a timing diagram illustrating digital waveforms received by the multi-tune filter system during a low pass address set command;

[0029] FIG. 12 is a timing diagram illustrating digital waveforms received by the multi-tune filter system during a high pass address set command;

[0030] FIG. 13 is a timing diagram illustrating digital waveforms received by the multi-tune filter system during a read unit command;

[0031] FIG. 14 is a table illustrating a number of tunable combinations for the multi-tune filter system;

[0032] FIGS. 15-20 are exemplary frequency graphs of frequency ranges in which the multi-tune filter system operates;

[0033] FIG. 21 is a block diagram illustrating a multi-tune filter system including a high pass filter array/section and a low pass filter array/section;

[0034] FIG. 22 is a block diagram illustrating interaction between the high pass filter array/section and the low pass filter array/section;

[0035] FIG. 23 is a flowchart illustrating data flows for the low pass address set command, high pass address set command, and the serial out command;

[0036] FIG. 24 is a flowchart illustrating additional data flows for read unit functions;

[0037] FIG. 25 is a flowchart illustrating data flows for a decoder of the multi-tune filter system; and

[0038] FIGS. 26 and 27 are a flowchart illustrating data flows for the data processor of the multi-tune filter system.

[0039] In one or more implementations, not all of the depicted components in each figure may be required, and one or more implementations may include additional components not shown in a figure. Variations in the arrangement and type of the components may be made without departing from the scope of the subject disclosure. Additional components, different components, or fewer components may be utilized within the scope of the subject disclosure.

DETAILED DESCRIPTION

[0040] The detailed description set forth below is intended as a description of various implementations and is not intended to represent the only implementations in which the subject technology may be practiced. As those skilled in the art would realize, the described implementations may be modified in various different ways, all without departing from the scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.

I. General Overview

[0041] Generally, the present disclosure details, with reference to FIGS. 1-27, a multi-tune filter system 100 and a control system 102 for the multi-tune filter system 100. The multi-tune filter system 100 is a tunable frequency range filter, as illustrated in FIGS. 1 and 2. The multi-tune filter system 100 is contrasted with a conventional tunable bandpass filter, which only facilitates adjustment thereof by modifying a center frequency. The multi-tune filter system 100 is a digitally programmable filter with an adjustable passband 104 between first and second customizable frequency bounds f1, f2.

[0042] The first and second customizable frequency bounds f1, f2 are independently tuned to desired frequencies above and below a center frequency fc. The first and second customizable frequency bounds f1, f2 define the range limits of a tuned pass band/frequency range filter implemented by the multi-tune filter system 100. FIG. 2 graphically represents the tunable frequency range of the multi-tune filter of FIG. 1. The multi-tune filter system 100 forms a filter with a completely adjustable center frequency and bandwidth as directed by instructions from a user and/or programming elements.

II. Example Implementations

[0043] Apparatus

[0044] Referring now to FIG. 3, a diagram of the multi-tune filter system 100 comprising a data processor 106, a decoder 108, memory 110, low pass control 112, high pass control 114, serial data out control 116, and a serial data processor 118 is shown. In an exemplary embodiment, the high pass control 114 operates first, second, and third high pass filter legs, 120, 122, 124 shown in FIG. 4. Similarly, the low pass control 112 operates first, second, and third low pass filter legs 126, 128, 130 shown in FIG. 5. FIGS. 6-10 are exemplary frequency graphs of frequency ranges in which the multi-tune filter system 100 operates and implements a tunable frequency range filter.

[0045] Referring back to FIG. 4, a lumped-element high-pass filter topology of each of the three high pass filter legs 120, 122, 124 comprises a 5th-order, elliptic Cauer-Chebyshev filter implemented with a minimum number of capacitors 188. Two capacitors operably connected to each of the three legs 120, 122, 124 are tunable through two 8-bit digitally controlled capacitor arrays/sections 190. The capacitor arrays/sections 190 tune transmission zeros of a transfer function thereby resulting in corresponding adjustment of a filter cutoff frequency for each of the three high pass filter legs 120, 122, 124 while maintaining balanced attenuation flybacks.

[0046] Typically, as the cutoff frequency is tuned away from a nominal value, performance of an elliptic filter may decrease, higher flyback in the attenuation range of the filter may be produced, matching from the nominal input/output impedance (e.g., 50 ohm) may worsen, and higher insertion loss at the passband may occur. To address these characteristics, the multi-tune filter system 100 utilizes multi-aperture core wideband impedance transformers T2, T3 to facilitate tuning. The impedance transformers T2, T3 adjust the input/output impedance of each of the first, second, and third high pass filter legs 120, 122, 124 from a nominal level to a higher or lower level depending on a desired cutoff frequency.

[0047] To implement lower cutoff frequencies, the impedance transformers T2, T3 adjust each high pass filter leg 120, 122, 124, as needed, from nominal 50 ohms to 35 ohms. To implement higher cutoff frequencies, the impedance transformers adjust each high pass filter leg 120, 122, 124, as needed, from nominal 50 ohms to 70 ohms. In the example architecture of FIG. 4, the SW401, SW501, SW601, SW406, SW506, and SW606 RF switches operate to select the 35 ohm impedance at lower cutoff frequencies and 70 ohm impedance at higher cutoff frequencies from the T2 and T3 impedance transformers. This technique extends the tunable frequency range of each of the three legs 120, 122, 124, while maintaining low attenuation flybacks and low passband insertion loss. Selection of 35, 50 or 70 ohms as input/output impedance on each of the high pass filter legs 120, 122, 124 splits the frequency range of each leg into three subranges, one for each impedance setting. The resulting nine high-pass frequency range selection blocks, as shown in FIG. 21, present the frequency range of each of the three high pass filter legs 120, 122, 124 as having three subranges on each leg.

[0048] In FIG. 5, a lumped element low-pass filter topology of each of the three low pass filter legs 126, 128, 130 comprises a 5th-order, elliptic Cauer-Chebyshev filter implemented with a minimum number of capacitors 192. Two capacitors operably connected to each of the three legs 126, 128, 130 are tunable through two 8-bit, digitally controlled capacitor arrays/sections 194. The capacitor arrays/sections 192 tune the transmission zeros of the transfer function thereby resulting in corresponding adjustment of a filter cutoff frequency for each of the three low pass filter legs 126, 128, 130, while maintaining balanced attenuation flybacks.

[0049] As analogously detailed with respect to the topology of FIG. 4, as the cutoff frequency is tuned away from the nominal, the performance of an elliptic filter may decrease, higher flyback in the attenuation range of the filter may be produced, matching from the nominal input/output impedance (e.g., 50 ohm) may worsen, and higher insertion loss at the passband may occur. To address these characteristics, the multi-tune filter system 100 utilizes multi-aperture core wideband impedance transformer T1 to facilitate tuning. The impedance transformer T1 adjusts the input/output impedance of each of the first, second, and third low pass filter legs 126, 128, 130 from a nominal level to a higher or lower level depending on a desired cutoff frequency.

[0050] To implement lower cutoff frequencies, the impedance transformer T1 adjusts each low pass filter leg 126, 128, 130, as needed, from nominal 50 ohms to 35 ohms. To implement higher cutoff frequencies, the impedance transformer T1 adjusts each low pass filter leg 126, 128, 130, as needed, from nominal 50 ohms to 70 ohms. In the example architecture of FIG. 5, the SW101, SW201, SW301, SW106, SW206, and SW306 RF switches operate to select the 35 ohm impedance at lower cutoff frequencies and 70 ohm impedance at higher cutoff frequencies. This technique extends the tunable frequency range of each of the low pass filter legs 126, 128, 130, while low attenuation flybacks and low passband insertion loss. The selection of 35, 50 or 70 ohms as input/output impedance on each of the low pass filter legs 126, 128, 130 splits the frequency range of each leg into three subranges, one for each impedance setting. The resulting nine low-pass frequency range selection blocks, as shown in FIG. 21, present the frequency range of each of the three low pass filter legs 126, 128, 130 as having three subranges on each leg. The output impedance of the low-pass section is selected by the wideband impedance transformer T2 of the high-pass filter section presented in FIG. 4. In certain embodiments, the high pass filter array/section 132 cascades into the low pass filter array/section 134 (see FIG. 21). Therefore, in examples, a filtered signal cascades through the high pass and low pass filter arrays/sections to implement the tunable frequency range filter.

[0051] An exemplary embodiment of the multi-tune filter system 100 is controlled through a serial peripheral interface. The multi-tune filter system 100 may be commanded by two words (e.g., 16 bits each word) to set the adjustable passband 104. In examples, the two words define the first and second customizable frequency bounds f1, f2. The customizable frequency bounds f1, f2 are defined with 100 KHz resolution (e.g. a step size between selectable frequencies for f1 and f2 is 100 KHz, as also illustrated in FIG. 14). The words defining the customizable frequency bounds f1, f2 are between decimal 15 (1.5 MHz) and decimal 300 (30 MHz). In exemplary embodiments, the multi-tune filter operates within the frequency range of 1.5 MHz and 30 MHz, with frequency limits at, or at about, 1.5 MHz and at, or at about, 30 MHz. According to exemplary embodiments, the words defining the customizable frequency bounds f1, f2 may operate to adjust the impedance transformers T1, T2, T3 and the RF switches SW401, SW501, SW601, SW406, SW506, SW606, SW101, SW201, SW301, SW106, SW206, and SW306, to implement the desired tuning of the tunable frequency range filter.

[0052] In exemplary embodiments, the second customizable frequency bound f2 must be greater than f1. In other words, the upper bound of the frequency range is greater than the lower bound thereof. Referring again to the table of FIG. 14, the multi-tune filter system 100 is internally programmed with 71 geometrically distributed tune channels between 1.5 MHz and 30 MHz. The 71 geometrically distributed tune channels provide 100 KHz actual resolution with a 1.5 MHz range. The range may be gradually increased to 30 MHz with a corresponding increase in step size of 800 KHz between tune channels.

[0053] In certain embodiments, when the multi-tune filter system 100 is commanded to tune the first and second customizable frequency bounds f1, f2 between step sizes, then the customizable frequencies may be automatically tuned to nearest rounded frequencies corresponding to the 71 discrete channels shown in FIG. 14.

[0054] FIGS. 11-13 are timing diagrams illustrating digital waveforms received by the multi-tune filter system during varying commands, e.g., selection of the first and second customizable frequencies f1, f2. Tuning addresses start at 15 decimal (1.5 MHz) and end at 300 decimal (30 MHz) in 100 KHz increments for the low pass and high pass addresses. Tuning of the filter is initiated when a last data clock (32nd) pulse of the transmitted address is sent to the unit while a chip select line (CS) is held low.

[0055] FIG. 11 is a timing diagram illustrating digital waveforms received by the multi-tune filter system during a low pass address set command 140. In this example, address 15 is transmitted (i.e., shown in the first (or “low”) byte “0000 1111”) and corresponds to a frequency range bound of 1.5 MHz. The second byte (i.e., “0000 0000”) indicates that the first byte sets the lower customizable frequency bound f1.

[0056] FIG. 12 is a timing diagram illustrating digital waveforms received by the multi-tune filter system during a high pass address set command 142. In this example, address 15 is transmitted (i.e., shown in the first byte “0000 1111”) and corresponds to a frequency range bound of 1.5 MHz. The second byte (i.e., “1001 0000”) indicates that the first byte sets the upper customizable frequency bound f2. As noted previously, in a working example combining the address timing of FIGS. 11 and 12, the second customizable frequency bound f2 must be greater than f1.

[0057] The low pass address set command 140 and the high pass address set command 142 will set the respective customizable frequency bounds f1, f2 when an address in the range of “0000 1111” to “1 0010 1100” (corresponding to 15-300 decimal, as noted hereinabove) is clocked into the multi-tune filter system 100. Tuning of the multi-tune filter system 100 may be performed in about 50 vs.

[0058] FIG. 13 is a timing diagram illustrating digital waveforms received by the multi-tune filter system during a read unit command 144. The read unit command timing is delivered for commands that read information stored within the memory 110 of the multi-tune filter system 100, including reading a unit identification, reading a unit firmware version, and reading a unit production date. The multi-tune filter system 100 remains at the previously tuned adjustable passband 104 when read unit command timing is received.

[0059] FIGS. 15-20 are exemplary frequency graphs of frequency ranges in which the multi-tune filter system operates. For example, in FIG. 15 the first customizable frequency bound f1 is set to 7.9 MHz and the second customizable frequency bound f2 is set to 15.4 MHz. Therefore, the adjustable passband 104 of the multi-tune filter system 100 spans 7.9-15.4 MHz. As illustrated in these examples, the adjustable passband 104 may be adjusted to allow differing frequency bands to pass and to allow the range of the passable band to increase or decrease. For example, FIG. 17 allows a relatively narrow range of frequencies to pass (i.e., 1.5 MHz to 1.8 MHz) while FIG. 16 allows a relatively broader range of frequencies to pass (i.e., 10.9 MHz to 21.5 MHz).

[0060] FIG. 21 is a block diagram illustrating an embodiment of the multi-tune filter system 100 including a high pass filter array/section 132 and a low pass filter array/section 134. FIG. 22 is a block diagram illustrating a flow through the high pass filter array/section and the low pass filter array/section. In this embodiment, a relatively large number of combinations of high pass filter subranges 136 and low pass filter subranges 138 (i.e., in the embodiment of FIG. 21 each filter array/section 132, 134 has nine filter subranges) may be executed. As a result, optimization of power reflected by each leg of the filter arrays/sections 132, 134 (i.e., return loss) is controlled at a system-wide level for desired operation. The cascade of the high pass and low pass filter arrays/sections 132, 134 at certain cutoff combinations may reach a −6.5 dB return loss. When frequencies of the adjustable passband 104 experience return loss above −9.5 dB, a 4.0 dB insertion loss is acceptable.

[0061] For the multi-tune filter system 100 shown and described with respect to FIGS. 1-5, a maximum passband insertion loss at ambient temperature is less than −4 dB. Furthermore, a passband return loss is between −6 dB and −10 dB.

[0062] Control Methods

[0063] The control 102 for the multi-tune filter system 100 is shown and described with reference to FIGS. 23-27. FIG. 23 is a flowchart illustrating data flows for the low pass address set command 140, high pass address set command 142, and the serial out/read unit command 144. The low pass address set command 140 corresponds to the timing diagram of FIG. 11. The high pass address set command 142 corresponds to the timing diagram of FIG. 12. Also, the serial out command 144 corresponds to the read command timing diagram of FIG. 13. Together these three commands facilitate control of the multi-tune filter system 100. Furthermore, the low pass address set command 140 and the high pass address set command 142 operate to customize the adjustable passband 104 of the multi-tune filter system 100.

[0064] The low and high pass address set commands 140, 142 have corresponding enablement check steps 146 that check a setting of a tune enable status register 202 (refer ahead to FIG. 25). The tune enable status register 202 is checked to determine whether the customizable frequency bounds f1, f2 may be set by a received command.

[0065] FIG. 24 is a flowchart illustrating additional data flows for the serial out command 144. Referring to FIG. 25, a flowchart illustrating data flows for a decoder 108 of the multi-tune filter system 100 is illustrated. The decoder 108 receives a high byte of the 16-bit words accepted by the multi-tune filter system 100. Along branch 150, the decoder 108 receives a request to execute the low pass address set command 140. Accordingly, a low pass status register 200 and the tune enable status register 202 are set to enable setting of the low pass customizable frequency bound f1.

[0066] Similarly, along branch 152, the decoder 108 receives a request to execute the high pass address set command 142. Accordingly, a high pass status register 206 and the tune enable status register 202 are set to enable setting of the high pass customizable frequency bound f2. In read unit, branches 154, 156, 158 the tune enable status register 202 is disabled to prevent setting of either of the customizable frequency bounds f1, f2. The read unit branches 154, 156, 158 perform one or more of variations on the serial out command 144 (see also FIGS. 23 and 24). In each of the read unit branches a serial out enable status register 208 is set to enable serial output of the multi-tune filter system 100. At default branch 160, if a 16-bit word is not recognized then a default command is performed that returns status registers to initialized settings. Initialized settings include disabling the serial out enable status register 208 and setting the tune enable status register 206 to enable tuning.

[0067] FIGS. 26 and 27 are a flowchart illustrating data flows for the data processor 106 of the multi-tune filter system 100. The data processor 106 accepts inputs from the serial data processor 118, the decoder 108, and a system clock. The data processor 106 also can access the memory module 110 via a memory control unit.

[0068] Referring now to FIGS. 26 and 27, the data processor 106 accepts inputs from user control (i.e., via the serial data processor 118) and develops control signals for the low pass control 112 and the high pass control 114 (see FIG. 3). As a result, the data processor 106 coordinates setting and maintaining the customizable frequency bounds f1, f2 that define the adjustable passband 104 and create a technical improvement within the field of filtering technology.

[0069] Control branch 162 (C-A-B-C) performs the steps for read unit functions (as further described with respect to FIGS. 23-25). An initialization control branch 164 is executed by the data processor 106 during initialization and ends by setting an initialize unit status register 210.

[0070] If initialization has already been performed then the data processor moves to control branches 164, 166, whereby the data processor 106 performs the low and high pass address set commands 140, 142 and the serial data out command 144, respectively. At decision block 168, the data processor 106 checks whether an incoming instruction is one of the low and high pass address set commands 140, 142 or the serial data out command 144.

[0071] The first control branch 164 (C-D-E-C or C-D-F-C) executes the low and high pass address set commands 140, 142. At step 170, a serial data out register is locked during first control branch 164. Then at step 172, a system tune ready initialization is set, followed by setting the tune enable status register 202 to “on” thereby preparing the multi-tune filter system 100 to receive a customizable frequency bound setting. At step 174, the data processor 106 sends a read command to memory control, and at step 176 an address within memory to be read is transmitted to the memory control. The memory control returns the contents of the memory location to a temporary storage register for storing the customizable frequency bound f1, f2 during either the low or high pass address set commands 140, 142. Step 178 detects a selection of which customizable frequency bound f1, f2 is being set.

[0072] At decision step 180 along the control branch 164, a low pass enable status register 212 is checked. Alternatively, a high pass enable status register could be checked; however, only one of the two status registers (i.e., low pass enable or high pass enable) need be checked to determine whether the command to be performed is the low pass address set command 140 or the high pass address set command 142. In the present example, if the low pass enable status register 212 is enabled (“YES”) at the decision step 180, then the low pass command 140 is executed (D-E-C) to set the first customizable frequency bound f1. But, if the low pass enable status register 212 is not enabled (“NO”) at the decision step 180, then the high pass command 142 is executed (D-F-C) to set the second customizable frequency bound f2.

[0073] The second control branch 166 (C-G-C) executes the serial data out command 144 and the read unit functions. First, at step 182, the tune enable status register 202 is disabled because during the serial data out command 144, bytes received from the serial data processor 118 are not stored as the customizable frequency bounds f1, f2. Instead, memory units accessed during execution of the second control branch 166 are only read and not written.

[0074] Referring again to FIG. 27, at decision step 184 an ID select status register 214 is polled. If the ID select status register 214 is enabled (“YES”), then identification information of the multi-tune filter system 100 is transmitted through the serial data out control 116 to identify the unit for a user. Further, at decision step 186, a firmware select status register is 216 is polled. If the firmware select status register 216 is enabled (“YES”) then a current firmware version is read from memory and transmitted through the serial data out control 116. If neither of the ID select status register 214 and the firmware select status register 216 are enabled, then a build date of the multi-tune filter system 100 is transmitted through the serial data out control 116.

[0075] The status registers described hereinthroughout may instead be bits of an instruction received by the serial data processor 118. Received instructions may be temporarily, permanently, and/or semi-permanently stored in one or more volatile or non-volatile memory modules (e.g., random access memory (SRAM), flash memory, and electrically erasable programmable read-only memory (EEPROM)). The present disclosure contemplates that the control algorithm(s) 102 and the multi-tune filter system 100 may be integrated with an embedded microcontroller comprising one or more suitable processing modules and one or more memory modules (e.g., the processors 106, 118 and the memory 110) for storing the customizable frequency bounds f1, f2 and other parameters defining the adjustable passband 104. Also, in examples, one or more memory modules may instead be disposed remotely, such as in cloud storage and/or on a server, and accessible by the one or more processing modules through one or more wired and/or wireless connections. For example, the processors 106, 118 and the memory 110 may be configured as part of a communications device or as a separate control module associated only with the multi-tune filter 100. Also, example embodiments may integrate the processors, 106, 118, the memory 110, and the other control components as a single control module. Alternatively, these processing components may be separate, but communicatively coupled.

[0076] The embodiment(s) detailed hereinabove may be combined in full or in part, with any alternative embodiment(s) described.

INDUSTRIAL APPLICABILITY

[0077] The disclosed systems and methods can be implemented with an electronics system, using, for example, software, hardware (e.g., passive and/or active electronic components), and/or a combination of both, either with a dedicated microcontroller, integrated into another entity (e.g., communications device), or distributed across multiple entities. An exemplary system includes a bus or other communication mechanism for communicating information, and a processor coupled with the bus for processing information. The processor may be locally or remotely coupled with the bus. By way of example, the filter system may be implemented with one or more processors. The processor may be a general-purpose microprocessor, a microcontroller, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a controller, a state machine, gated logic, discrete hardware components, or any other suitable entity that can perform calculations or other manipulations of information. The filter system also includes a memory, such as a Random-Access Memory (RAM), a flash memory, a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable PROM (EPROM), registers, a hard disk, a removable disk, a CD-ROM, a DVD, or any other suitable storage device, coupled to a bus for storing information and instructions to be executed by processor.

[0078] According to one aspect of the present disclosure, the disclosed system can be implemented using a number of active and/or passive electronic components in response to a processor executing one or more sequences of one or more instructions contained in memory. Such instructions may be read into memory from another machine-readable medium, such as a data storage device. Execution of the sequences of instructions contained in main memory causes the processor to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in memory. In alternative implementations, hard-wired circuitry may be used in place of or in combination with software instructions to implement various implementations of the present disclosure. Thus, implementations of the present disclosure are not limited to any specific combination of hardware circuitry and software. According to one aspect of the disclosure, the disclosed system can be implemented using one or many remote elements in an electronics system (e.g., cloud computing), such as a processor that is remote from other elements of the exemplary filter system described above.

[0079] A reference to an element in the singular is not intended to mean “one and only one” unless specifically stated, but rather “one or more.” The term “some” refers to one or more. Underlined and/or italicized headings and subheadings are used for convenience only, do not limit the subject technology, and are not referred to in connection with the interpretation of the description of the subject technology. Relational terms such as first and second and the like may be used to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. All structural and functional equivalents to the elements of the various configurations described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and intended to be encompassed by the subject technology. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the above description.

[0080] Numerous modifications to the present disclosure will be apparent to those skilled in the art in view of the foregoing description. Preferred embodiments of this disclosure are described herein, including the best mode known to the inventors for carrying out the disclosure. It should be understood that the illustrated embodiments are exemplary only and should not be taken as limiting the scope of the disclosure.