METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure, the mothed including: providing a substrate, a heterojunction structure, and a P-type semiconductor layer, which are distributed from bottom to top; forming a patterned mask layer on the P-type semiconductor layer, the patterned mask layer covering at least a portion of the P-type semiconductor layer in a gate region; removing an exposed portion of the P-type semiconductor layer by in-situ etching with a corrosive gas, by using the patterned mask layer as a mask; and then activating the P-type dopant ions in the P-type semiconductor layer.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate, a heterojunction structure, and a P-type semiconductor layer, which are distributed from bottom to up; forming a patterned mask layer on the P-type semiconductor layer, wherein the patterned mask layer at least covers a portion of the P-type semiconductor layer in the gate region; removing an exposed portion of the P-type semiconductor layer by in-situ etching with a corrosive gas, by using the patterned mask layer as a mask; and activating P-type dopant ions in the P-type semiconductor layer.

2. The method for manufacturing the semiconductor structure according to claim 1, wherein the in-situ etching comprises: a step of forming the patterned mask layer and a step of etching, which are performed in one reaction chamber, or in different chambers of one vacuum interconnect device.

3. The method for manufacturing the semiconductor structure according to claim 1, wherein a material of the P-type semiconductor layer is GaN, removing the exposed portion of the P-type semiconductor layer by in-situ etching is performed at a temperature higher than 300° C., and the corrosive gas comprises H.sub.2 and/or NH.sub.3, a mixture of Cl.sub.2 and N.sub.2, or HCl.

4. The method for manufacturing the semiconductor structure according to claim 3, wherein removing the exposed portion of the P-type semiconductor layer by in-situ etching is performed at a temperature higher than 700° C.

5. The method for manufacturing the semiconductor structure according to claim 1, wherein after activating P-type doped ions in the P-type semiconductor layer, the method further comprises: growing an N-type semiconductor layer on two sides of the P-type semiconductor layer and on the heterojunction structure by using the patterned mask layer as a mask.

6. The method for manufacturing the semiconductor structure according to claim 5, wherein a material of the N-type semiconductor layer is GaN or AlGaN.

7. The method for manufacturing the semiconductor structure according to claim 1, wherein after activating P-type dopant ions in the P-type semiconductor layer, the method further comprises: growing an N-type semiconductor layer on top of the patterned mask layer, on two sides of the patterned mask layer and the P-type semiconductor layer, and on the heterojunction structure.

8. The method for manufacturing the semiconductor structure according to claim 7, wherein a material of the N-type semiconductor layer is AlN.

9. The method for manufacturing the semiconductor structure according to claim 3, wherein a material of the heterojunction structure adjacent to the P-type semiconductor layer is AlGaN.

10. The method for manufacturing the semiconductor structure according to claim 1, wherein after removing the exposed portion of the P-type semiconductor layer by in-situ etching, the method further comprises: performing a step of cooling down; and stopping supplying the corrosive gas during the step of cooling down.

11. The method for manufacturing the semiconductor structure according to claim 10, wherein in the step of cooling down, supplying the corrosive gas is stopped at a temperature greater than or equal to 600° C.

12. The method for manufacturing the semiconductor structure according to claim 10, wherein in the step of cooling down, an inert protective gas is provided.

13. The method for manufacturing the semiconductor structure according to claim 1, wherein P-type dopant ions in the P-type semiconductor layer is activated by annealing at a temperature greater than 500° C.

14. The method for manufacturing the semiconductor structure according to claim 1, wherein a material of the patterned mask layer is silicon dioxide, silicon nitride or silicon oxynitride.

15. The method for manufacturing the semiconductor structure according to claim 1, further comprising: forming a source electrode on a source region, forming a drain electrode on a drain region, and forming a gate electrode on the activated P-type semiconductor layer.

16. The method for manufacturing the semiconductor structure according to claim 5, further comprising: removing the patterned mask layer to expose the P-type semiconductor layer.

17. The method for manufacturing the semiconductor structure according to claim 5, further comprising: removing the patterned mask layer to expose the P-type semiconductor layer by wet etching.

18. The method for manufacturing the semiconductor structure according to claim 7, further comprising: removing the patterned mask layer and a portion of the N-type semiconductor layer on the patterned mask layer to expose the P-type semiconductor layer.

19. The method for manufacturing the semiconductor structure according to claim 7, further comprising: removing the patterned mask layer and a portion of the N-type semiconductor layer on the patterned mask layer to expose the P-type semiconductor layer by dry etching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure according to a first embodiment of the present disclosure;

[0036] FIGS. 2 and 3 are schematic diagrams illustrating intermediate structures corresponding to process in FIG. 1;

[0037] FIG. 4 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a second embodiment of the present disclosure.

[0038] FIG. 5 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a third embodiment of the present disclosure.

[0039] FIG. 6 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a fourth embodiment of the present disclosure.

[0040] FIG. 7 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a fifth embodiment of the present disclosure.

[0041] FIG. 8 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a sixth embodiment of the present disclosure.

[0042] FIGS. 9 and 10 are schematic diagrams of intermediate structures corresponding to a method for manufacturing a semiconductor structure according to a seventh embodiment of the present disclosure.

[0043] In order to facilitate the understanding of the present disclosure, all reference signs appearing in the present disclosure are listed below: [0044] Substrate 10 [0045] Heterojunction structure 11 [0046] Channel layer 111 [0047] Potential barrier layer 112 [0048] Gate region 11a [0049] Source region 11b [0050] Drain region 11c [0051] P-type semiconductor layer 12 [0052] Patterned mask layer 13 [0053] N-type semiconductor layer 14 [0054] Gate electrode 15a [0055] Source electrode 15b [0056] Drain electrode 15c

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] In order to make the above-mentioned purposes, features and advantages of the present disclosure more apparent and understandable, specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0058] FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure according to a first embodiment of the present disclosure; and FIGS. 2 and 3 are schematic diagrams illustrating intermediate structures corresponding to the process of FIG. 1.

[0059] Firstly, referring to step S1 in FIG. 1 and FIG. 2, a substrate 10, a heterojunction structure 11, and a P-type semiconductor layer 12, which are distributed from bottom to up are provided.

[0060] A material of the substrate 10 may be sapphire, silicon carbide, silicon, silicon on insulator (SOI), lithium niobate, GaN, AN, or diamond.

[0061] The heterojunction structure 11 may include a group III nitride material.

[0062] In this embodiment, the heterojunction structure 11 includes a channel layer 111 and a potential barrier layer 112, which are distributed from bottom to up. A two-dimensional electron gas may be formed at an interface of the channel layer 111 and the potential barrier layer 112. Materials of the channel layer 111 and the potential barrier layer 112 may be group III nitride materials. In an optional embodiment, the channel layer 111 is an intrinsic GaN layer and the potential barrier layer 112 is an N-type AlGaN layer. N-type ions may be at least one of Si ions, Ge ions, Sn ions, Se ions, and Te ions. In other optional embodiments, the materials combination of the channel layer 111 and the potential barrier layer 112 may also be GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN, or InN/InAlN. Furthermore, in addition to having one layer respectively, the channel layer 111 and the potential barrier layer 112 shown in FIG. 2 may also have multiple layers respectively, which are distributed alternately; or the channel layer 111 has one layer and the potential barrier layer 112 has multiple layers to form a multi-barrier structure.

[0063] The epitaxial growth processes of the channel layer 111 and the potential barrier layer 112 can include: Atomic Layer Deposition (ALD), or Chemical Vapor Deposition (CVD), or molecular beam epitaxial (MBE), or Plasma Enhanced Chemical Vapor Deposition (PECVD), or Low Pressure Chemical Vapor Deposition (LPCVD), or Metal-Organic Chemical Vapor Deposition (MOCVD), or a combination thereof

[0064] In some embodiments, the heterojunction structure 11 includes a back barrier layer and a channel layer, which are distributed from bottom to up.

[0065] The heterojunction structure 11 includes a gate region 11a, and a source region 11b and a drain region 11c at both sides of the gate region 11a respectively. The gate region 11 a is used to form a gate electrode, the source region 11b is used to form a source electrode, and the drain region 11c is used to form a drain electrode.

[0066] A nucleation layer and a buffer layer (not shown) distributed from bottom to up may be also placed between heterojunction structure 11 and the substrate 10, a material of the nucleation layer may be, for example, AlN, AlGaN, and etc., and a material of the buffer layer may include at least one of AIN, GaN, AlGaN, or AlInGaN. The nucleation layer may alleviate the problem of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layers, such as the channel layer 111 in the heterojunction structure 11 and the substrate 10, and the buffer layer may reduce the dislocation density and the defect density of the epitaxially grown semiconductor layer and may improve the crystal quality.

[0067] The material of the P-type semiconductor layer 12 is a group III-V compound. In this embodiment, the P-type semiconductor layer 12 is specifically GaN. In other embodiments, it may be other materials.

[0068] The epitaxial growth of the P-type semiconductor layer 12 may refer to the epitaxial growth of the channel layer 111 and the potential barrier layer 112. The P-type dopant ions may be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions to deplete a two-dimensional electron gas below the gate region to form an enhanced device. The P-type dopant ions in the P-type semiconductor layer 12 may be achieved by in-situ doping.

[0069] In some embodiments, the substrate 10, the heterojunction structure 11, and the P-type semiconductor layer 12, which are distributed from bottom to up in step S1 may also be an existing pre-final structure.

[0070] Secondly, referring to step S2 in FIG. 1 and FIG. 2, a patterned mask layer 13 is formed on the P-type semiconductor layer 12, where the patterned mask layer 13 at least covers a portion of the P-type semiconductor layer 12 in the gate region 11a. Referring to FIGS. 2 and 3, the patterned mask layer 13 is used as a mask, and an exposed portion of the P-type semiconductor layer 12 is removed by in-situ etching with a corrosive gas.

[0071] The material of the mask layer 13 may be silicon dioxide, silicon nitride or silicon oxynitride, and may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical evaporation deposition (LPCVD) or atomic layer deposition (ALD) accordingly. The patterning may be achieved by dry etching or wet etching. Referring to FIG. 2, in this embodiment, the size of the patterned mask layer 13 is slightly larger than the size of the gate region 11 a.

[0072] In this embodiment, the material of the P-type semiconductor layer 12 is GaN, and the corresponding corrosive gas includes H.sub.2 and/or NH.sub.3.

[0073] At high temperature, for example, at a temperature greater than 300° C., the chemical equation for the reaction of H.sub.2 with the exposed portion of P-type semiconductor layer 12 is:

##STR00001##

[0074] At high temperature, for example, at a temperature greater than 300° C., the chemical equation for the reaction of NH.sub.3 with the exposed portion of P-type semiconductor layer 12 is:

##STR00002##

[0075] The above reaction is preferably performed at 700° C. or higher.

[0076] The etching of the above P-type semiconductor layer 12 is dry etching. The dry etching may be inductively coupled plasma etching (ICP).

[0077] Since a material of the P-type semiconductor layer 12 is GaN, which may react with the targeted corrosive gas H.sub.2 and/or NH.sub.3 to complete the etching removal. Therefore, the P-type semiconductor layer 12 may be etched in-situ by injecting the corrosive gas into a process chamber of a previous step. The advantage includes that: a transfer process between the chambers when etching may be avoided, a risk of contamination is avoided, and a production efficiency is improved. The process chamber of the previous step may include the chamber where the mask layer 13 is formed and patterned, and may also include the chamber where the heterojunction structure 11 and the P-type semiconductor layer 12 are epitaxially grown.

[0078] In other embodiments, the process chamber of the previous step and the chamber for etching may also be different chambers of one vacuum interconnect device.

[0079] The corrosive gas such as H.sub.2 and/or NH.sub.3 do not react with the patterned mask layer 13, and thus the etch selectivity is good when the P-type semiconductor layer 12 is patterned. In addition, by selecting the material of the potential barrier layer 112, the potential barrier layer 112 cannot react with the corrosive gas such as H.sub.2 and/or NH.sub.3. The potential barrier layer 112 may be used as an etch stop layer for the process of patterning the P-type semiconductor layer 12 without causing etch damage to the heterojunction structure 11.

[0080] In some embodiments, the corrosive gas may also be a mixture gas of Cl.sub.2 and N.sub.2, or HCl. In the mixture gas of Cl.sub.2 and N.sub.2, the amount of substance of Cl.sub.2 is preferably less than 10% of the total amount of substance of the corrosive gas.

[0081] Afterwards, referring to step S3 in FIG. 1 and FIG. 3, P-type dopant ions in the P-type semiconductor layer is activated.

[0082] A large amount of H ions is present in the process environment where the P-type semiconductor layer 12 is grown, such as the MOCVD growth environment. If the H ions are not removed, the P-type dopant ions (acceptor dopant, such as Mg ions) in the group III nitride materials may bond with the H ions, so as to be passivated by a large amount of H ions without generating cavities.

[0083] Activating the P-type dopant ions in the P-type semiconductor layer 12 may be achieved by high temperature annealing, e.g., at a temperature greater than 500° C., to allow the H ions to escape. In some embodiments, high-temperature annealing is performed in an inactive gas to prevent the introduction of H ions. For example, the P-type dopant ions may be activated in a hydrogen-free gas atmosphere such as nitrogen, a mixture of nitrogen and oxygen, laughing gas (NO), or argon and etc. During high-temperature annealing, nitrogen molecules and decomposition products of nitrogen molecules may effectively penetrate into the surface of the group III nitride materials, nitrogen vacancy caused during etching are well compensated, and the quality of the P-type semiconductor layer 12 may be improved.

[0084] Activating the P-type dopant ions in the P-type semiconductor layer 12 may also be an in-situ treatment, i.e., which is performed in the same chamber as step S2.

[0085] Referring to FIG. 3, when activating the P-type dopant ions in the P-type semiconductor layer 12, the P-type semiconductor layer 12 is covered by the patterned mask layer 13. When a material of the patterned mask layer 13 is silicon dioxide, oxygen ions in the silicon dioxide may adsorb H ions in the P-type semiconductor layer 12, such that H ions are released to the outside via the surface. Thus, the release velocity of H ions in the P-type semiconductor layer 12 may be accelerated.

[0086] FIG. 4 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a second embodiment of the present disclosure. Referring to FIG. 4, a manufacturing method of the semiconductor structure of this second embodiment is substantially the same as the manufacturing method of the semiconductor structure of first embodiment, and the different includes that: between the step S2 and the step S3, a step of cooling down is performed, and supplying the corrosive gas is stopped during the step of cooling down.

[0087] The advantage includes that the P-type dopant ions in the P-type semiconductor layer 12 may be prevented from combining with the H ions in the corrosive gas and being passivated.

[0088] Optionally, in the step of cooling down, supplying the corrosive gas is stopped at a temperature greater than or equal to 600° C.

[0089] FIG. 5 is a schematic diagram of an intermediate structure corresponding to a method of manufacturing nitride semiconductor substrate according to a third embodiment of the present disclosure. Referring to FIG. 5, a manufacturing method of the semiconductor structure of this third embodiment is substantially the same as the manufacturing method of the semiconductor structure of the second embodiment, and the different includes that: an inert protective gas is provided during the step of cooling down. The inert protective gas may include nitrogen or argon. The inert protective gas may prevent the P-type semiconductor layer 12 from being oxidized.

[0090] FIG. 6 is a schematic diagram of an intermediate structure corresponding to a method of manufacturing nitride semiconductor substrate according to a fourth embodiment of the present disclosure. Referring to FIG. 6, a manufacturing method of the semiconductor structure of this fourth embodiment is substantially the same as the manufacturing methods of the semiconductor structure of the first embodiment to the third embodiment, and the different includes that: at step S3, before activating P-type dopant ions in the P-type semiconductor layer 12, the patterned mask layer 13 is removed to expose the portion of P-type semiconductor layer 12 in the gate region 11a.

[0091] The P-type semiconductor layer 12 in the gate region 11a is exposed, such that H ions may also be released from the top surface of the P-type semiconductor layer 12 to the outside.

[0092] FIG. 7 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a fifth embodiment of the present disclosure. Referring to FIG. 7, the manufacturing method of the semiconductor structure of this fifth embodiment is substantially the same as the manufacturing method of the semiconductor structure of the first embodiment to the fourth embodiment, and the different includes that: the method for manufacturing a semiconductor structure provided by the fifth embodiment further includes a step S4. At step S4, by using patterned mask layer 13 as a mask, an N-type semiconductor layer 14 is grown on two sides of the P-type semiconductor layer 12 and the heterojunction structure 11.

[0093] A material of the N-type semiconductor layer 14 is a group III-V compound, which, may be for example GaN or AlGaN, and the above materials are difficult to grow on the patterned mask layer 13. The percentage of amount of substance of Al in the AlGaN material is preferably less than 10%. The N-type semiconductor layer 14 may be achieved by doping N-type ions within a III-V compound, the N-type ions may be at least one of Si ions, Ge ions, Sn ions, Se ions or Te ions. The material of the N-type semiconductor layer 14 may also be an unintentionally doped III-V compound due to the presence of Si ions in the epitaxial growth environment.

[0094] The N-type semiconductor layer may provide electron carriers to the heterojunction structure, thereby reducing a resistance between the source electrode and the drain electrode while the source electrode and the drain electrode are connected with each other.

[0095] Afterwards, the patterned mask layer 13 may be removed to expose the P-type semiconductor layer 12. The patterned mask layer 13 may be removed by wet etching.

[0096] FIG. 8 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a semiconductor structure according to a sixth embodiment of the present disclosure. Referring to FIG. 8, a manufacturing method of the semiconductor structure of this sixth embodiment is substantially the same as the manufacturing method of the semiconductor structure of the fifth embodiment, and the different includes that: at step S4, the N-type semiconductor layer 14 is also grown on the top and two sides of the patterned mask layer 13.

[0097] The material of N-type semiconductor layer 14 may be, for example, AlN, which may be grown on the patterned mask layer 13.

[0098] Afterwards, the patterned mask layer 13 and the N-type semiconductor layer 14 on the patterned mask layer 13 may be removed to expose the P-type semiconductor layer 12. The patterned mask layer 13 and the N-type semiconductor layer 14 on the patterned mask layer 13 may be removed by dry etching.

[0099] FIGS. 9 and 10 are schematic diagrams of intermediate structures corresponding to the method for manufacturing a semiconductor structure according to the seventh embodiment of the present disclosure. Referring to FIGS. 9 and 10, the manufacturing method of the semiconductor structure of this seventh embodiment is substantially the same as the manufacturing method of the semiconductor structure of the first embodiment to the sixth embodiment, except that after step S4 (or after step S3 if step S4 is not performed), the source electrode 15b is formed on the source region 11b, the drain electrode 15c is formed on the drain region 11c, and the gate electrode 15a is formed on the activated P-type semiconductor layer 12.

[0100] Specifically, a metal layer, such as Ti/Al/Ni/Au, Ni/Au, etc., may be formed first by sputtering; the metal layer outside the gate region 11a, source region 11b, and the drain region 11c are removed by etching, and ohmic contacts between the source electrode 15b and the source region 11b, the drain electrode 15c and the drain region 11c, and the gate electrode 15a and the P-type semiconductor layer 12 in the gate region 11a are formed by high-temperature annealing.

[0101] The difference between the method of making the semiconductor structure of FIG. 9 and that of FIG. 10 is that: in FIG. 9, both the source electrode 15b and the drain electrode 15c are in contact with the potential barrier layer 112; in FIG. 10, both the source electrode 15b and the drain electrode 15c are in contact with the channel layer 111.

[0102] Although the present disclosure discloses the above contents, the present disclosure is not limited thereto. One of ordinary skill in the art may make various variants and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be set forth by the appended claims.