HIGH EFFICIENCY ULTRAVIOLET LIGHT-EMITTING DEVICES INCORPORATING A NOVEL MULTILAYER STRUCTURE

Abstract

A multilayer structure comprising regions of higher aluminum (Al) composition as compared to adjacent layers, in combination with an undulating active region and controlled buffer layer crystal quality, promotes radiative recombination and improves the performance and efficiency of ultraviolet (UV) or far-UV light-emitting diodes (LEDs), laser diode (LDs), or other light emitting devices.

Claims

1. A device, comprising: a light-emitting diode (LED) comprised of one or more III-nitride semiconductor layers containing aluminum, including an active region having a single or multiple quantum well structure emitting at an ultra-violet (UV) wavelength, and at least one cladding layer; and an n-side multilayer structure located adjacent to the active region of the LED, wherein the n-side multilayer structure contains one or more of the III-nitride semiconductor layers with a higher aluminum composition as compared to adjacent layers of the n-side multilayer structure, the active region and/or the cladding layer.

2. The device of claim 1, wherein the III-nitride semiconductor layers containing aluminum comprise Al.sub.xGa.sub.1−xN alloys where 0≤x≤1.

3. The device of claim 1, wherein the n-side multilayer structure provides an ability to fine-tune and control surface morphology and crystal quality, to achieve a specific targeted surface morphology and crystal quality in the active region.

4. The device of claim 3, wherein the n-side multilayer structure achieves an undulating active region.

5. The device of claim 1, wherein the active region's surface has a disc-hillock morphology with a root mean square (RMS) roughness of between 0.5 to 15 nm over a 2 μm by 2 μm region, but comprises local regions at least 100 nm by 100 nm in size with an RMS roughness of less than 1 nm.

6. The device of claim 1, wherein at least one of the III-nitride semiconductor layers has a (102) rocking curve full width at half-maximum of between 150-500 arcseconds or dislocation density between 1×10.sup.7 to 1×10.sup.10 cm.sup.−2.

7. The device of claim 1, wherein the n-side multilayer structure comprises one or more of the III-nitride semiconductor layers with different aluminum molar fractions, such as Al.sub.xGa.sub.1−xN where 0≤x≤1, Al.sub.yGa.sub.1−yN where 0≤y≤1, and Al.sub.zGa.sub.1−zN where 0≤z≤1.

8. The device of claim 7, wherein the one or more of the III-nitride semiconductor layers are formed in a repeating pattern, one or more of the III-nitride semiconductor layers differ in thickness, at least one of the III-nitride semiconductor layers has a thickness of less than 200 angstroms, and the n-side multilayer structure has a total thickness of less than 500 nm.

9. The device of claim 1, wherein the n-side multilayer structure is in contact with the active region.

10. The device of claim 1, wherein the III-nitride semiconductor layers of the n-side multilayer structure are undoped, unintentionally doped, doped, and/or modulation doped, with a doping concentration adjusted to be 5×10.sup.21/cm.sup.3 or less and n-type when the III-nitride semiconductor layers are doped or modulation doped.

11. The device of claim 1, further comprising: a p-cladding layer that is a short period superlattice (SPSL) made of alternating layers of Al.sub.kGa.sub.1−kN and Al.sub.mGa.sub.1−mN doped with magnesium, where 0≤k≤1 and 0≤m≤1; a three-dimensional (3D) polarization doped III-nitride semiconductor layer grown on or above a p-type III-nitride semiconductor layer of the LED; a tunnel junction grown on or above a p-type III-nitride semiconductor layer of the LED, wherein the tunnel junction comprises an n-type III-nitride semiconductor layer; and/or a p-type doped Al.sub.xGa.sub.1−xN hole injection layer grown on or above a III-nitride semiconductor layer of the LED.

12. A method, comprising: fabricating a III-nitride multilayer structure on or above a substrate; and fabricating a light-emitting diode (LED) comprised of one or more III-nitride semiconductor layers containing aluminum, including an active region having a single or multiple quantum well structure emitting at an ultra-violet (UV) wavelength, and at least one cladding layer; and wherein the III-nitride multilayer structure is located adjacent to the active region of the LED, and the III-nitride multilayer structure contains III-nitride semiconductor layers with a higher aluminum composition as compared to adjacent layers of the III-nitride multilayer structure, the active region and/or the cladding layer.

13. The method of claim 12, wherein the III-nitride semiconductor layers containing aluminum comprise Al.sub.xGa.sub.1−xN alloys where 0≤x≤1

14. The method of claim 12, wherein trimethylindium is used in the growth of the III-nitride semiconductor layers.

15. The method of claim 14, wherein a higher flow of the trimethylindium is used in the growth of the III-nitride semiconductor layers as compared to a flow of trimethylaluminum and trimethylgallium.

16. The method of claim 12, wherein: a flow of at least one metalorganic precursor and/or ammonia is paused for at least 3 seconds in between growth of alternating layers in the III-nitride multilayer structure, a flow of at least one metalorganic precursor and/or ammonia is paused for at least 3 seconds in between growth of different layers in the active region, or a flow of at least one metalorganic precursor and/or ammonia is paused for at least 3 seconds in order to create a layer of higher aluminum composition at least once in the LED.

17. The method of claim 12, wherein a V to III ratio used in growth of the III-nitride multilayer structure is less than 500, preferably less than 100, more preferably less than 50, and most preferably less than 20.

18. The method of claim 12, wherein the cladding layer is an AlGaN cladding layer and a V to III ratio used in growth of the AlGaN cladding layer in between the substrate and an interlayer is less than 500, preferably less than 100, more preferably less than 50, and most preferably less than 20.

19. The method of claim 12, wherein a V to III ratio used in growth of layers in the active region is less than 500, preferably less than 100, more preferably less than 50, and most preferably less than 20.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

[0034] FIG. 1A is a cross-sectional schematic of the first nitride semiconductor device of the present invention, comprising an n-AlGaN to a p-AlGaN short-period superlattice (SPSL) TJ with a top contact that may be partially or fully transparent or reflective, and incorporating a multilayer structure below the active region, and FIGS. 1B, 1C and 1D are magnified callouts from FIG. 1A.

[0035] FIG. 2A is a cross-sectional schematic of the second nitride semiconductor device of the present invention, comprising an n-AlGaN to a 3D polarization doped p-AlGaN TJ with a top contact that may be partially or fully transparent or reflective, and incorporating a multilayer structure below the active region, and FIGS. 2B and 2C are magnified callouts from FIG. 2A.

[0036] FIG. 3A is a cross-sectional schematic of the third nitride semiconductor device of the present invention, comprising a p-GaN hole injection layer on top of a p-AlGaN SPSL with a top contact that may be partially or fully transparent or reflective, and incorporating a multilayer structure below the active region, and FIGS. 3B, 3C and 3D are magnified callouts from FIG. 3A.

[0037] FIG. 4A is a cross-sectional schematic of the fourth nitride semiconductor device of the present invention, comprising a p-GaN hole injection layer on top of a 3D polarization doped AlGaN layer with a top contact that may be partially or fully transparent or reflective, and incorporating a multilayer structure below the active region, and FIGS. 4B and 4C are magnified callouts from FIG. 4A.

[0038] FIGS. 5A and 5B are atomic force microscopy (AFM) images of a typical disc-hillock morphology observed in the multilayer structure and active region surfaces.

[0039] FIG. 6 is a cross-sectional transmission electron microscopy (TEM) image of an undulating active region.

[0040] FIG. 7 is a graph of quick test (QT) power at 20 mA (mW) vs. (102) full-width at half-maximum (FWHM) (arcsec) that shows the output power measured for LEDs grown on substrates with different MN layer (102) FWHMs.

[0041] FIG. 8 is a flowchart illustrating a method for fabricating a device according to the present invention.

[0042] FIG. 9 is a graph of quick electroluminescence (EL) power (mW) vs. current (mA) that shows the output power measured for LEDs grown with and without the novel multilayer structure versus input current.

[0043] FIG. 10 is a graph of spectral radiant power (μW/nm) vs. wavelength (nm) that shows a comparison of typical spectral radiant power between a typical UV-C LED with a multilayer structure and a typical conventional near UV-C LED without a multilayer structure (e.g., a conventional UV LED).

[0044] FIG. 11 is an AFM image of a typical surface morphology of an active region of a conventional UV-C or near UV-C LED.

[0045] FIG. 12A is a cross-sectional schematic of a conventional UV-C LED, and FIGS. 12B and 12C are magnified callouts from FIG. 12A.

DETAILED DESCRIPTION OF THE INVENTION

[0046] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

Overview

[0047] The present invention describes UV light emitting III-nitride-based device structures incorporating a III-nitride-based multilayer structure (interlayer) deposited or formed on a substrate via MOCVD. The use of III-nitride-based multilayer structures incorporated into UV light emitting devices offers a means of improving the III-nitride device performance.

[0048] III-nitride-based light emitting device structures incorporating a doped multilayer structure provide a means of enhancing the performance of III-nitride-based UV light emitting LEDs by greatly enhancing the device output power at constant current, in comparison with III-nitride-based UV light emitting LEDs without the multilayer structure. The present invention discloses a III-nitride-based UV light emitting LEDs with a doped multilayer structure and discloses a means of creating such a doped multilayer structure to achieve enhanced device performance.

Technical Description

[0049] The prior art in III-nitride-based UV light emitting LEDs typically comprises an n-type region with a simple layer structure, such as one or more thick layers of uniform doping and composition. Whereas superlattices and multilayer structures are commonplace in active regions and p-type structures, they have not been applied to the n-side of the device in current state-of-the-art, commercially available III-nitride-based UV light emitting LEDs. This invention demonstrates the improved light output characteristics of III-nitride-based UV light emitting LEDs in which a doped multilayer structure has been introduced in the n-type side of the active region of the device.

Embodiment 1

[0050] FIG. 1A is a schematic sectional view showing the structure of a III-nitride-based UV light emitting LED, according to a first embodiment of the present invention. This LED comprises a sapphire substrate 103 (e.g., either a flat or patterned sapphire substrate), and deposited successively in the following order on the substrate 103: a first buffer layer 104 made of AlN (closest to the substrate 103 surface), a second buffer layer 105 made of Al.sub.aGa.sub.1−aN, an n-contact or n-cladding layer 106 made of Al.sub.bGa.sub.1−bN doped with silicon, an n-side multilayer structure 101 comprised of an Al.sub.cGa.sub.1−cN/Al.sub.aGa.sub.1−aN/Al.sub.eGa.sub.1−eN superlattice (SL) doped with silicon (with layers 101a, 101b and 101c shown in the magnified callout of FIG. 1B), an active region 102 comprising a multiple quantum well structure made of Al.sub.fGa.sub.1−fN/Al.sub.gGa.sub.1−gN (with layers 102a and 102b shown in the magnified callout of FIG. 1C), a UID (unintentionally doped) or p-type Al.sub.hGa.sub.1−hN spacer 108, a p-type Al.sub.jGa.sub.1−jN EBL 109 doped with magnesium, a p-type cladding layer 110 comprising an SPSL made of alternating layers with layers 110a and 110b of Al.sub.kGa.sub.1−kN/Al.sub.mGa.sub.1−mN doped with magnesium (shown in the magnified callout in FIG. 1D), a TJ transparent current spreading layer 114 made of Al.sub.nGa.sub.1−nN doped with silicon, and an n-contact layer 112 that is the furthest from the substrate 103 surface, where 0≤a,b,c,d,e,f,g,h,j,k,m,n≤1, and each of a, b, c, d, e, f, g, h, j, k, m, n can be different from one another. The n-contact layer 112 may comprise a reflective mirror contact that covers the majority (>50%) of the surface or the entire surface, where the layer is fabricated from various materials that may include metallic V, Al, Ni, Au, Ag, Pt, Pd, In, or other metals, or IZO, ITO, MgF.sub.2, SiO.sub.2, gallium oxide (Ga.sub.2O.sub.3) (n-type or intrinsic), or other compounds. The n-contact layer 112 may also comprise a current spreading pad that does not cover the entire top surface and supplies current to the n-type transparent TJ current spreading layer 114, where electrodes are formed to cover less than 50% of the surface to allow for light to escape out of the top surface. Also, the device has a portion where a surface of the n-side nitride semiconductor layer 106 is exposed and an n-electrode 107 composed of various materials that may include metallic V, Al, Ni, Au, Ag, Pt, Pd, In, or other metals, or IZO, ITO, MgF.sub.2, SiO.sub.2, Ga.sub.2O.sub.3 (n-type or intrinsic), or other compounds is formed thereon. The n-contact or n-cladding layer 112 and n-electrode 107 may be either reflective, transparent, or opaque, and similar materials may be used to coat the entire device to improve and direct the light output.

[0051] The LED device according to the first embodiment has the active region 102 with the multi quantum well structure sandwiched between an n-region including the first buffer layer 104, the second buffer layer 105, the n-contact or n-cladding layer 106, and the n-side multilayer structure 101, and a p-region including the UID or p-type spacer 108, the p-type AlGaN EBL 109, and the p-type cladding SPSL layer 110.

[0052] The nitride semiconductor device according to the first embodiment includes the n-side multilayer structure layer 101 beneath the active region 102 in the n-region, depositing, as shown in the magnified callout in FIG. 1B, one or more III-nitride semiconductor layers with different aluminum molar fractions, such as a first nitride semiconductor film 101c containing Al.sub.cGa.sub.1−cN, a second nitride semiconductor film 101b containing Al.sub.dGa.sub.1−dN, and a third nitride semiconductor film 101a containing Al.sub.eGa.sub.1−eN, where the compositions c, d, e may all be different from one another and are in the range 0≤c,d,e≤1. The films 101a, 101b, and 101c could also be formed from etchback of the underlying previous film layer instead of direct deposition, where the AlGaN alloy composition of the topmost part of the previous layer is changed with gas etching of the material. The multifilm layers 101a, 101b, and 101c could also be doped with silicon, germanium, or other elements, at a concentration below 10.sup.21 cm.sup.−3. The n-side multilayer structure 101 includes at least one of each of the first nitride semiconductor film 101c and the second nitride semiconductor film 101b in an example stack 101c/101b, and preferably includes the third nitride semiconductor film 101a as well as more than two total repetitions of the structure such as in an example stack of (101c/101b/101a/101b) repeated three times. The n-side multilayer structure 101 can be any combination of the layers 101c, 101b, and 101a, in any particular order. More or less layers of different compositions or thicknesses can also be incorporated.

[0053] In one embodiment, the n-side multilayer structure 101 comprises a sequence of 101b/101c/101b/101a/101b/101c/101b/101a/101b/101c/101b/101a/101b, or in shorthand notation, (101b/101c/101b/101a)×3+101b.

[0054] Where the n-side multilayer structure 101 is formed in contact with the active region 102, one of the nitride semiconductor films 101a, 101b, or 101c is held in contact with an initial layer (a well or a barrier layer) of the active region 102. This layer may be any of the layers 101a, 101b, 101c, or additional included layers.

[0055] Additionally, even though the n-side multilayer structure 101 is formed in direct contact with the active region 102 in the illustrated embodiment, another layer made of an n-type nitride semiconductor may intervene between the n-side multilayer structure 101 and the active region 102.

[0056] In a preferred embodiment, at least one first nitride semiconductor film 101a, and/or at least one second nitride semiconductor film 101c, may have a film thickness not greater than 300 angstroms, preferably not greater than 150 angstroms. At least one third nitride semiconductor film 101b may have a film thickness not greater than 150 angstroms, preferably not greater than 50 angstroms, and more preferably not greater than 20 angstroms. The n-side multilayer structure 101 may be as follows: (101b/101c/101b/101a)×n+101b, where n may be less than 20, preferably less than 10, and more preferably between 1 and 8. The film 101b would preferably be formed by gas etchback of underlying films (either 101a, 101c, or whatever layer is immediately below) to form a thin, high Al content layer. The compositions of the films 101a/101b/101c may be in the range of 0.5≤c,d,e≤1 for UV-C LEDs, and more preferably in the range of 0.55≤c,d,e≤0.85 for 101a and 101c and in the range of 0.7≤c,d,e≤1 for 101b. The nitride semiconductor films 101a/101b/101c may be doped with silicon at a concentration below 10.sup.21 cm.sup.−3, and more preferably in the range of 10.sup.17 to 10.sup.20 cm.sup.−3. When different numbers of each of the films 101a, 101b, and 101c are deposited with controlled thicknesses, and with control of the deposition parameters in MOCVD such as ammonia flow, etchback conditions for 101b, growth rate, growth duration, doping concentration of Si, metalorganic flow, etc., different surface morphologies and crystal qualities can be achieved in and above the n-side multilayer structure 101. When the films 101a, 101b, and 101c have thicknesses, doping, and compositions within the above-mentioned range, the crystal quality and radiative recombination rate of emitting nitride semiconductor film layers deposited on such a n-side multilayer structure 101 can be drastically improved, due to the improvements on the crystal quality and growth morphology of the n-side multilayer structure 101. The n-side multilayer structure 101 thus provides the ability to fine-tune and control the surface morphology and crystal quality, to achieve a specific targeted surface morphology and crystal quality in the active region 102 to be grown above, and also to achieve an undulating active region 102. One preferred targeted surface morphology in the n-side multilayer structure 101 and undulating active region 102 is detailed in FIGS. 5A, 5B and 6 and is defined as a “disc-hillock” morphology. The disc-hillocks are circular or elliptical nano-discs, with near-atomically flat (below 2 nm root mean square (RMS) roughness, or more preferably below 1 nm RMS roughness) surfaces, and between 50 to 1000 nm in length and width. The discs are between 1 nm and 20 nm tall relative to the surrounding area, and form elevated regions that are locally extremely smooth, enabling well-defined quantum well structures to be grown on top of the discs, and thus increasing the output capability of the device. Over a wider region, the locally flat disc-hillocks undulate up and down, creating a surface morphology with an average RMS roughness of between 0.5 to 15 nm, or more preferably between 1 to 5 nm, over a 2 μm by 2 μm region, but comprises local regions at least 100 nm by 100 nm in size with an RMS roughness of less than 1 nm. The RMS roughness over a large area is defined as the undulating amplitude and should be at least 0.5 nm for the effects of the undulating morphology to be realized. This undulating active region 102 may improve the light emission efficiency of the device due to electron and hole localization from the disc-hillocks, and extremely smooth surfaces on top of the disc-hillocks enable sharp quantum well heterostructures which increase carrier localization further.

[0057] The crystal quality of the first buffer layer 104 made of AlN is extremely important to LED performance, as crystallographic defects can act as non-radiative recombination centers and decrease the light output efficiency in high enough concentrations. Crystal quality can be estimated with an x-ray diffraction (102) peak rocking curve full width at half-maximum (RC-FWHM) measurement, which correlates with the dislocation density of the material. In material with a (102) peak RC FWHM that is above 500 arcseconds, the dislocation density is too high, and electrons and holes are unable to travel far without interacting with a defect and recombining without emitting light, thus causing a decrease in efficiency. In material with a (102) peak RC FWHM that is below 150 arcseconds, the preferred undulating disc-hillock crystal growth morphology may be unable to be achieved. This limits LED performance due to the lack of the beneficial carrier localization effects from the desired undulating disc-hillock morphology. LED power output versus (102) RC FWHM is detailed in FIG. 7, and a maximum in LED output power is observed for RC-FWHM of the AlN buffer layer 104 between 250 and 330 arcseconds. A decrease in LED output power is observed at very low (200 arcseconds) and very high (440 arcseconds). Thus, it is preferred that the (102) RC-FWHM of the AlN buffer layer 104 be between 150 and 500 arcseconds or dislocation density between 1×10.sup.7 to 1×10.sup.10 cm.sup.−2.

[0058] In a second preferred embodiment, the nitride semiconductor films 101a, 101b, and 101c may have different thicknesses, doping, and/or compositions. For example, at least one of the first/second/third nitride semiconductor films 101a.sub.i/101b.sub.i/101c.sub.i can have a film thickness, doping concentration, and/or alloy composition of AlGaN different from that of the next neighboring first/second/third nitride semiconductor films 101a.sub.i−1/101b.sub.i−1/101c.sub.i−1 and 101a.sub.i+1/101b.sub.i+1/101c.sub.i+1 (i.e., the thickness of the film 101a.sub.i/101b.sub.i/101c.sub.i can be different from the thicknesses of the films 101a.sub.i−1/101b.sub.i−1/101c.sub.i−1 and 101a.sub.i+1/101.sub.b+1/101c.sub.i+1 which are respectively below and above the film 101a.sub.i/101b.sub.i/101c.sub.i in the sequence of first/second/third nitride semiconductor films). By way of further example, assuming that the first nitride semiconductor film 101a is made of a lower Al composition AlGaN and the second nitride semiconductor film 101c is made of a higher Al composition AlGaN (the third nitride semiconductor film 101b is assumed to be a constant thickness, doping, and composition throughout the n-side multilayer structure 101), the individual layers 101a.sub.i and 101c.sub.i closer to the n-AlGaN cladding 106 may have a varying film thickness either increasing or decreasing as the distance from the layers 101a.sub.i and 101c.sub.i to the active region 102 decreases. In so doing, the n-side multilayer structure 101 can have a varying index of refraction with the nitride semiconductor films 101a.sub.i and 101b.sub.i having varying indexes of refraction resulting in an average increase or decrease in the index of refraction between the n-AlGaN cladding 106 and active region 102. Thus, the n-side multilayer structure 101 can exhibit substantially the same effects as those of a continuous grading composition nitride semiconductor layer while retaining its ability to control the crystal quality and surface morphology. Accordingly, in a semiconductor device such as a semiconductor laser of a type requiring the use of a beam waveguide, the n-side multilayer structure 101 can operate as a beam waveguide to adjust the mode of the laser beam.

[0059] In a third preferred embodiment, the first and second nitride semiconductors layers 101a and 101c can be made of the same semiconductor material with similar thicknesses, while the layer 101b can be formed through the gas etching of the layers 101a and 101c resulting in a much thinner layer 101b. The thickness of layers of type 101a and 101c may be between 50 and 300 angstroms, while the thickness of layers of type 101b may be between 1 and 20 angstroms. This creates a single layer with effectively a singular composition with only very slight deviations, but with the thin layers 101b and controlled doping of Si throughout the structure 101, allow for control of the growth morphology and crystal quality similar to previously detailed preferred embodiments.

[0060] In the practice of the first, second, and third preferred embodiment, one, two, or all of the three nitride semiconductor films 101a/101b/101c may be either undoped or doped with n-type impurities such as Si and Ge. To enhance the crystal quality, the first and second nitride semiconductor films 101a, 101b, and 101c are preferably doped with silicon at a concentration below 10.sup.21 cm.sup.−3, and more preferably in the range of 10.sup.17 to 10.sup.20 cm.sup.−3. The layers 101a/101b/101c may also be doped with a varying or constant concentration through the individual layers, and throughout the entire structure 101. For example, the doping of layers of type 101a, 101b, or 101c closer to the n-AlGaN cladding 106 may have a lower or higher average concentration compared with layers closer to the active region 102, and individual layers 101a, 101b, or 101c may have a linear grading ramp where the dopant concentration linearly increases or decreases throughout the individual layers.

[0061] In the practice of the first, second and third preferred embodiment, the p-type cladding layer 110 that is an SPSL comprises alternating nitride semiconductor layers 110a and 110b, wherein the thickness of these layers may be below 100 angstroms, preferably below 50 angstroms, and more preferably below 30 angstroms. The composition of one of the layers 110a and 110b may be Al.sub.xGa.sub.1−xN where 0≤x≤0.5, or more preferably 0≤x≤0.3, and the other of the layers 110a and 110b may be Al.sub.yGa.sub.1−yN where 0.5≤y≤1, or more preferably 0.7≤x≤1. The layers 110a and 110b may be p-type doped with preferably Mg, or alternatively Be or other elements, to a concentration in the range of 10.sup.16 to 10.sup.21 cm.sup.−3, or more preferably 10.sup.18 to 10.sup.20 cm.sup.−3.

[0062] The EBL 109 comprises Al.sub.xGa.sub.1−xN where 0.6≤x≤1, with a thickness of between 2 to nm, and may be p-type doped with preferably Mg, or alternatively Be or other elements, to a concentration in the range of 10.sup.16 to 10.sup.21 cm.sup.−3, or more preferably 10.sup.18 to 10.sup.20 cm.sup.−3.

Embodiment 2

[0063] The nitride semiconductor light emitting device according to embodiment 2, as shown in FIG. 2A (wherein FIGS. 2B and 2C are magnified callouts of layers 101a, 101b and 101c, and 102a and 102b, respectively), has the same structure as in embodiment 1 except that the p-type cladding layer 110 in embodiment 2 comprises a 3D polarization doped nitride semiconductor layer 113, thereby substituting for the p-type cladding layer 110 that is an SPSL described in embodiment 1.

[0064] The 3D polarization doped nitride semiconductor layer comprises a layer of Al.sub.xGa.sub.1−xN of thickness less than 300 nm where 0≤x≤1, where the composition throughout the layer can be constant or varied. A possibility for a varied composition profile would be a linearly increasing or decreasing Al composition between the start of the layer 113 (just above layer 109), to the end of the layer 113 (just below layer 114). The layer may also be undoped, or doped with Mg, Be, or other elements, at an average concentration between 10.sup.16 to 10.sup.21 cm.sup.−3. The doping concentration profile may be constant or varied throughout the layer. Some examples of possible varied doping concentration profiles are a linearly increasing or decreasing amount of dopant, or a constant low or zero doping concentration for most of the layer with a few thin (less than 10 nm thick) sheets of extremely high concentrations (delta doping).

[0065] A preferred embodiment would be where the composition of the layer 113 is linearly graded from Al.sub.xGa.sub.1−xN where 0.7≤x≤1 at the boundary between layers 109 and 113 to Al.sub.yGa.sub.1−yN where 0≤y≤0.5 at the boundary between layers 114 and 113.

Embodiment 3

[0066] The nitride semiconductor light emitting diode according to embodiment 3, as shown in FIG. 3A (wherein FIGS. 3B, 3C and 3D are magnified callouts of layers 101a, 101b and 101c, 102a and 102b, and 110a and 110b, respectively), has the same structure as embodiment 1, except that the TJ current spreading n-type layer 114 is replaced with a p-type doped Al.sub.xGa.sub.1−xN hole injection layer 111 of thickness less than 500 nm where the composition is 0≤x≤0.7, or more preferably of a thickness between 5 and 50 nm and a composition 0≤x≤0.3, and that the n-contact layer 112 is now replaced with a p-contact layer to the p-type hole injection layer 111, which similar to the n-contact layer 112 in embodiment 1, may comprise a reflective mirror contact that covers the majority (>50%) of the surface or the entire surface, where the layer is fabricated from various materials that may include metallic V, Al, Ni, Au, Ag, Pt, Pd, In, or other metals, or IZO, ITO, MgF.sub.2, SiO.sub.2, Ga.sub.2O.sub.3 (n-type or intrinsic), or other compounds. The p-contact layer 112 may also comprise a current spreading pad that does not cover the entire top surface and supplies current to the p-type hole injection layer 114, where electrodes are formed to cover less than 50% of the surface to allow for light to escape out of the top surface.

[0067] The p-type doped hole injection layer 111 may fully or partially cover the p-type cladding layer 110 below. A partial coverage hole injection layer where less than 70% of the p-type cladding layer 110 surface is covered by the hole injection layer 111 may enhance light output due to the light absorptive effects of the low Al content hole injection layer 111. A full coverage hole injection layer 111 may enhance light output due to the increased number of supplied hole carriers for recombination and light emission in the active region 102.

Embodiment 4

[0068] The nitride semiconductor light emitting diode according to embodiment 4, as shown in FIG. 4A (wherein FIGS. 4B and 4C are magnified callouts of layers 101a, 101b and 101c, and 102a and 102b, respectively), has the same structure as embodiment 2 except that the TJ current spreading n-type layer 114 is replaced with a p-type doped Al.sub.xGa.sub.1−xN hole injection layer 111 of thickness less than 500 nm where the composition is 0≤x≤0.7, or more preferably of a thickness between 5 and 50 nm and a composition 0≤x≤0.3. Also, similar to embodiment 3, the n-contact layer 112 (as in embodiment 1) is replaced with a p-contact layer 112 to act as a p-contact to the p-type hole injection layer 111.

[0069] Similar to embodiment 3, the p-type doped hole injection layer 111 may fully or partially cover the p-type cladding layer 110 below. A partial coverage hole injection layer where less than 70% of the p-type cladding layer 110 surface is covered by the hole injection layer 111 may enhance light output due to the light absorptive effects of the low Al content hole injection layer 111. A full coverage hole injection layer 111 may enhance light output due to the increased number of supplied hole carriers for recombination and light emission in the active region 102.

Process Steps

Example 1

[0070] Example 1 describes a method for fabricating the first embodiment of the present invention and is illustrated by reference to FIGS. 1A and 8.

[0071] Block 800 represents a first step where a substrate 103 is loaded in a reactor and cleaned. In Example 1, a C-face sapphire substrate 103 is set in the MOCVD reactor, and the temperature of the substrate 103 is increased to 1000-1400° C. with ammonia flow to clean the substrate 103. Instead of a C-face sapphire substrate 103, the substrate 103 may include a C-face AlN layer pre-deposited on a sapphire substrate 103 prepared with sputtering and annealing, another MOCVD reactor, or other material deposition technique. The sapphire substrate 103 may or may not be patterned to improve light extraction in the final UV LED. The substrate 103 may also have its principal surface represented by an R-, A-, M-, or other crystallographic face. The substrate 103 may also be composed of other materials, for example, SiC (including 6H, 4H or 3C), Si, ZnO, GaAs, GaN, AlN, BN, Ga.sub.2O.sub.3, spinel (MgAl.sub.2O.sub.4), or some other material, and may or may not have a pre-deposited layer of AlN deposited from a separate MOCVD reactor or other material deposition tool.

[0072] Block 801 represents a step where, subsequent to the ammonia substrate cleaning, a first buffer layer 104 made of AlN which has a thickness of about 150 nm is grown on the substrate 103, using hydrogen as a carrier gas, and ammonia and TMA (trimethylaluminum) as material gasses. Such a buffer layer 104 may be omitted, depending on the kind of the substrate, the growing method, etc.

[0073] Block 802 represents a step where, after growing the buffer layer 104, the flow of TMA is stopped, the flow of ammonia is changed to match the condition for the growth of the next layer 105, and the temperature is decreased to 1250° C. A second buffer layer 105, made of Al.sub.xGa.sub.1−xN where 0.6≤x≤1 (preferably x=0.85), is then deposited using ammonia, TMG (trimethylgallium), and TMA as material gasses, and TMI (trimethylindium) as a surfactant to improve the morphology. Such a buffer layer 105 may also be omitted, depending on the kind of the substrate, the growing method, etc. After growing the second buffer layer 105, the flows of TMA, TMG, and TMI are stopped, the ammonia flow is changed to match the condition for the growth of the next layer 106, and the temperature is decreased to 1200° C. An n-type contact or cladding layer 106, made of Al.sub.xGa.sub.1−xN where 0.4≤x≤1 (preferably x=0.65) and doped with Si to a concentration preferably of 5×10.sup.19/cm.sup.3 is grown using ammonia, TMG, and TMA as material gasses, TMI as a surfactant, and silane or disilane gas as a dopant gas. An ultralow ammonia flow condition may be used to grow the n-type contact or cladding layer 106, as it may improve the electrical characteristics of the n-type contact or cladding layer 106. Ultralow ammonia flow is defined here as having a V/III ratio, or ratio of ammonia gas flow to total metal organic flow, being below 100.

[0074] The thickness of the n-contact layer or cladding 106 is not specifically limited to any thickness, but if an ultralow ammonia flow condition is used, the thickness should preferably be between 100 to 1000 nm, due to strain and material growth effects compromising the material surface quality above thicknesses of 1000 nm. Moreover, the n-type impurity (preferably Si, but may also be Ge or other elements) may be desirably doped in with a high concentration to the degree that the crystal quality and electrical characteristics of the nitride semiconductor is not deteriorated and preferably in the concentration between 1×10.sup.18/cm.sup.3 and 5×10.sup.21/cm.sup.3.

[0075] Block 803 represents a next step where the temperature is maintained at 1200° C. and a first nitride semiconductor film (layer 101b), made of n-doped Al.sub.xGa.sub.1−xN where 0.6≤x≤1 and having a thickness of between 5 and 20 Angstroms, is grown using TMA, TMG, and ammonia as material gasses, disilane or silane as a dopant gas, and TMI as a surfactant. This layer may also (preferably) be created with etchback under hydrogen carrier gas, ammonia, and TMI, of the top surface of the previous layer (in this case, this would be the n-type contact or cladding layer 106), by etching out some Ga and decreasing the Ga composition, after shutting off the flow of disilane/silane, TMA, and TMG while keeping the flow of ammonia, hydrogen carrier gas, and TMI unchanged. Subsequently, if TMA, TMG, and disilane/silane were shut off, they are now turned back on, and a second nitride semiconductor film (layer 101c) made of n-doped Al.sub.xGa.sub.1−xN where 0.4≤x≤1 (preferably 0.6) of thickness between 50 and 300 Angstroms (preferably 140 Angstroms) is deposited. After this step, another layer 101b is deposited in a similar manner as previously described, via etchback of a thin region of layer 101c or via material growth with material gasses. Then, a layer 101a, which is similar to layer 101c, comprising n-doped Al.sub.xGa.sub.1−xN where 0.4≤x≤1, but may have a different composition compared to layer 101c (preferably 0.8), is deposited in a similar manner to how layer 101c was deposited. For layer 101a, the TMA and TMG may be changed from the deposition condition of layer 101c to account for any compositional differences between the two layers. After layer 101a is deposited, another layer 101b is deposited. These operations, which form a structure 101 of 101b/101c/101b/101a, may then be repeated any number of times, and may also include an incomplete repetition and end on any one of the layers 101a, 101b, 101c to form the n-side multilayer structure 101 (preferably repeated three times plus an additional deposition of layer 101b, for example). The n-type impurity (preferably Si but may also be Ge or other elements) may be desirably doped in a concentration throughout the structure 101 between 1×10.sup.17/cm.sup.3 and 1×10.sup.20/cm.sup.3, and more preferably between 5×10.sup.17/cm.sup.3 and 5×10.sup.19/cm.sup.3.

[0076] Block 804 represents a next step where the temperature is maintained at 1200° C. and a quantum well (layer 102b) made of Al.sub.xGa.sub.1−xN where 0≤x≤1 (preferably x=0.4 to 0.6 for UV-C emission) which may or may not be n-type doped having a thickness between 5 and 100 angstroms (preferably 15 angstroms) is grown using TMG, TMA, and ammonia as material gasses, TMI as a surfactant, and disilane or silane as a n-type dopant (if doped). Subsequently, a quantum barrier (layer 102a) made of Al.sub.xGa.sub.1−xN where 0≤x≤1 (preferably x=0.6 to 0.9 for UV-C emission) which may or may not be n-type doped having a thickness between 50 and 500 angstroms (preferably 140 angstroms) is grown using TMG, TMA, and ammonia as material gasses, TMI as a surfactant, and disilane or silane as a n-type dopant (if doped). Additional possible etchback layers similar to layer 101b may or may not be employed between the quantum well and quantum barrier layers 102a, 102b. A total of between 1 and 20 pairs (preferably 6 pairs) of quantum well and quantum barrier layers 102b/102a are formed, preferably finishing on a quantum barrier layer 102a. Thus, the active region 102 is formed. The active region 102 may be grown with the well layer 102b first and the barrier layer 102a last, or the order may begin with the barrier layer 102a and end with the well layer 102b. Thus, the order of depositing the barrier and well layers 102a, 102b is not specifically limited to a particular order. If the quantum well and quantum barrier layers 102b, 102a are doped, the n-type impurity (preferably Si, but may also be Ge or other elements) may be desirably doped in a concentration throughout the active region 102 between 1×10.sup.17/cm.sup.3 and 1×10.sup.20/cm.sup.3.

[0077] Block 805 represents a next step where the temperature is maintained at 1200° C., and using TMG, TMA, and ammonia as material gasses, TMI as a surfactant, disilane or silane as a n-type dopant (if n-type doped), or cyclopentadienyl magnesium (Cp.sub.2Mg) as a p-type dopant (if p-type doped), a spacer layer 108 made of Al.sub.xGa.sub.1−xN where 0≤x≤1 (preferably x=0.6 to 0.9 for UV-C emission) which may or may not be n-type doped having a thickness between 50 and 500 angstroms (preferably 140 angstroms) is grown. If doped, the n-type impurity (preferably Si, but may also be Ge or other elements) or p-type impurity (preferably Mg, but may also be Be or other elements) may be desirably doped in a concentration throughout the spacer layer 108 between 1×10.sup.17/cm.sup.3 and 1×10.sup.20/cm.sup.3. The spacer layer 108 may improve the separation of p-type dopant atoms between the region with p-type doping (layers 109 and 110) and n-type doping, and/or improve the positioning of the p-n junction such that maximal carrier recombination occurs in the quantum well layers, improving LED light output and performance.

[0078] Block 806 represents a next step where the temperature is maintained at 1200° C., and using TMG, TMA, and ammonia as material gasses, Cp.sub.2Mg as a p-type dopant gas, and TMI as a surfactant, a nitride semiconductor film 109, made of p-type doped Al.sub.xGa.sub.1−xN where 0≤x≤1 (preferably x=0.7 to 0.9 for UV-C emission) which had a thickness of between 20 and 200 angstroms (preferably 50 angstroms) was grown. This layer 109 acts as an electron blocking layer, and maximizes radiative recombination in the active layer 102. The layer 109 may also contain B or Sc, in an alloy Sc.sub.jGa.sub.nAl.sub.xB.sub.zN where 0≤j≤1, 0≤n≤1, 0≤x≤1, 0≤z≤1, and j+n+x+z=1. The p-type impurity (preferably Mg but may also be Be or other elements) may be desirably doped in a concentration throughout the electron blocking layer 109 between 1×10.sup.18/cm.sup.3 and 1×10.sup.21/cm.sup.3.

[0079] Block 807 represents a next step where the temperature is maintained at 1200° C., and using TMG, TMA, and ammonia as material gasses, Cp.sub.2Mg as a p-type dopant gas, and TMI as a surfactant, a nitride semiconductor layer 110 is grown for a p-type contact or cladding layer. To form layer 110, a nitride semiconductor layer 110a composed of p-type Al.sub.xGa.sub.1−xN where 0≤x≤1 (preferably 0.5≤x≤1, and more preferably 0.7≤x≤0.9) with thickness between 3 and 30 angstroms (preferably between 5 and 20 angstroms) is first deposited with the above-mentioned reactants. Then, the flow of the material gasses are adjusted, and a nitride semiconductor layer 110b composed of p-type Al.sub.xGa.sub.1−xN where 0≤x≤1 (preferably 0≤x≤0.5, and more preferably 0.1≤x≤0.3) with thickness between 3 and 30 angstroms (preferably between 5 and 20 angstroms) is deposited. Subsequently, layers 110a and 110b are deposited in an alternating manner, with a total number of layers between 10 and 80 layers, preferably between 20 and 60 layers. The p-type contact or cladding layer 110 may be grown with the layer 110a first and the layer 110b last, 110b first and 110a last, or may begin and end with both 110b or 110a. Thus, the order of depositing the layers 110a and 110b is not specifically limited to a particular order throughout the p-contact layer 110. The p-type impurity (preferably Mg but may also be Be or other elements) may be desirably doped in a concentration throughout the p-type contact layer 110 between 1×10.sup.17/cm.sup.3 and 1×10.sup.21/cm.sup.3.

[0080] Block 808 represents a next step where an n-type tunnel junction layer 114 is deposited at a temperature between 600 to 1400° C., using TMG, TMA, and ammonia as material gasses, silane or disilane as a n-type dopant gas, and TMI as a surfactant, with composition Al.sub.xGa.sub.1−xN where 0≤x≤1. The thickness should be preferably below 500 nm. The n-type impurity (preferably Si but may also be Ge or other elements) may be desirably doped in a concentration throughout the tunnel junction layer 114 between 1×10.sup.17/cm.sup.3 and 1×10.sup.21/cm.sup.3.

[0081] Block 809 represents a final step where a region of the device is etched to expose the n-contact layer 106. Electrodes 112 and 107 are then formed or bonded on top of the exposed region of layer 106 and on top of layer 114. The electrodes 112 and 107 may contain metals such as V, Al, Ni, Au, Ag, Pt, Pd, In, or other metals, and/or may contain Ga.sub.2O.sub.3, IZO, ITO, and/or other semiconductor or dielectric materials. The electrodes may be annealed at elevated temperatures.

[0082] During the device fabrication process, after the device growth by MOCVD or MBE, the device processing temperature should preferably be below 1000° C. (or more preferably 750° C.), in order to minimize relaxation and intermixing between the layers in the hetero-interface of the p-side layers, especially layer 110, or the Mg-doped Al.sub.xGa.sub.(1-x)N/Mg-doped Al.sub.yGa.sub.(1-y)N (x>y) SPSL, and prevent the structural or crystallographic degradation of all layers and/or passivation of the p-type doped layers (109, 110, 113, 111).

[0083] Block 810 represents an end result, namely, an optoelectronic device, such as an LED comprised of one or more nitride semiconductor layers containing aluminum, such as Al.sub.xGa.sub.1−xN alloys where 0≤x≤1, including an active region 102 having a single or multiple quantum well structure emitting at a UV wavelength, and at least one cladding layer. An n-side multilayer structure 101 is located adjacent to the active region 102 of the LED, wherein the n-side multilayer structure 101 contains layers one or more layers 101a, 101b, 101c, with a higher aluminum composition as compared to adjacent layers 101a, 101b, 101c, the active region 102 and/or the cladding layer.

[0084] The n-side multilayer structure 101 provides an ability to fine-tune and control surface morphology and crystal quality, to achieve a specific targeted surface morphology and crystal quality in the active region 102. Specifically, the n-side multilayer structure 101 may be used to achieve an undulating active region 102.

[0085] The n-side multilayer structure 101 comprises one or more nitride semiconductor layers 101a, 101b, 101c, with different aluminum molar fractions, such as Al.sub.xGa.sub.1−xN where 0≤x≤1, Al.sub.yGa.sub.1−yN where 0≤y≤1, and Al.sub.zGa.sub.1−zN where 0≤z≤1.

[0086] The nitride semiconductor layers 101a, 101b, 101c are undoped, unintentionally doped, doped, and/or modulation doped, with a doping concentration adjusted to be 5×10.sup.21/cm.sup.3 or less and n-type when the nitride semiconductor layers 101a, 101b, 101c, are doped or modulation doped.

[0087] The nitride semiconductor layers 101a, 101b, 101c, are formed in a repeating pattern, and may differ in thickness, wherein at least one of the nitride semiconductor layers 101a, 101b, 101c, has a thickness of less than 200 angstroms, and the n-side multilayer structure layer 101 has a total thickness of less than 500 nm.

[0088] The n-side multilayer structure 101 is adjacent an n-side of the active region 102 and, optionally, the n-side multilayer structure 101 is in contact with the active region 102.

[0089] At least one of the nitride semiconductor layers, such as an AlN buffer layer 104, an n-AlGaN cladding layer 106, and/or the n-side multilayer structure 101, has a (102) rocking curve full width at half-maximum of between 150-500 arcseconds or dislocation density between 1×10.sup.7 to 1×10.sup.10 cm.sup.−2. This condition should mostly likely apply to the AlN buffer layer 104, although the n-AlGaN cladding 106 and n-side multilayer structure 101 may also be in this range, but on the higher side, e.g., a (102) rocking curve full width at half-maximum of between 150-900 arcseconds and/or a dislocation density between 1×10.sup.7 to 1×10.sup.10 cm.sup.−2, due to increasing defects from strain, lattice mismatch, Si doping, etc. The device also comprises: a p-cladding layer that is a SPSL made of alternating layers of Al.sub.kGa.sub.1−kN and Al.sub.mGa.sub.1−mN doped with magnesium, where 0≤k≤1 and 0≤m≤1; a 3D polarization doped nitride semiconductor layer grown on or above a p-type nitride semiconductor layer of the LED; a tunnel junction grown on or above a p-type nitride semiconductor layer of the LED, wherein the tunnel junction comprises an n-type nitride semiconductor layer; and/or a p-type doped Al.sub.xGa.sub.1−xN hole injection layer grown on or above a III-nitride semiconductor layer of the LED.

Example 2

[0090] Example 2 describes a method for fabricating the second embodiment of the present invention and is illustrated by reference to FIGS. 2A and 8. The fabrication process in Example 2 is the same as in Example 1, except for the p-contact layer: layer 110 in Example 1 is replaced with layer 113 in Example 2. Layer 113 is a nitride semiconductor polarization doped p-type contact layer. To form layer 113, a nitride semiconductor layer composed of p-type Al.sub.xGa.sub.1−xN where 0≤x≤1 and where the composition varies throughout the layer (for example, in a preferably linearly increasing or decreasing manner) is grown using TMG, TMA, and ammonia as material gasses, Cp.sub.2Mg as a p-type dopant gas (optional), and TMI as a surfactant. The polarization doped layer 113 may be undoped, doped with a constant concentration of preferably Mg (or Be or other elements) below a concentration of 1×10.sup.21/cm.sup.3, or doped with a varying concentration of preferably Mg (or Be or other elements) between a concentration of 1×10.sup.17/cm.sup.3 to 1×10.sup.21/cm.sup.3.

Example 3

[0091] Example 3 describes a method for fabricating the third embodiment of the present invention and is illustrated by reference to FIGS. 3A and 8. The fabrication process in Example 3 is the same as in Example 1, except for the n-type TJ layer 114. In Example 3, the layer 114 is replaced with a p-type contact layer 111 composed of p-type doped Al.sub.xGa.sub.1−xN where 0≤x≤1, preferably 0≤x≤0.2. This layer is deposited at a temperature between 800 to 1200° C. (preferably 1050° C.) using TMG, TMA, and ammonia as material gasses, Cp.sub.2Mg as a p-type dopant gas, and (optionally) TMI as a surfactant, and doped with a concentration of preferably Mg (or Be or other elements) between 1×10.sup.17/cm.sup.3 and 1×10.sup.21/cm.sup.3. The thickness of this layer should be thicker than 50 angstroms, and preferably should be approximately 200 angstroms. The layer 111 may completely cover the immediate layer 110 beneath it, or may also be grown in a patchy island morphology that does not cover the entire surface, preferably covering less than 70% of the available surface area of layer 110 (or whichever layer is immediately below that layer).

Example 4

[0092] Example 4 describes a method for fabricating the fourth embodiment of the present invention and is illustrated by reference to FIGS. 4A and 8. The fabrication process in Example 3 is the same as in Example 1, except for the layer 110 being replaced with a layer 113 similar to that described in Example 2, and the layer 114 being replaced with a layer 111 similar to that described in Example 3.

Advantages and Improvements

[0093] FIG. 9 shows the output power measured for LEDs with an n-side multilayer structure 101 and without an n-side multilayer structure 101 (a conventional UV-C LED). The output power of the LEDs was evaluated by measuring the light output using a silicon photodetector through the back of the substrate. This is commonly referred to as an “on-wafer” measurement, or “quick electroluminescence (EL).” It is clear from FIG. 9 that the use of an optimized multilayer structure leads to a significant increase in the output power of about 300% compared to conventional UV-C LED devices.

[0094] FIG. 10 shows a comparison of typical spectral radiant power between a typical UV-C LED with an n-side multilayer structure 101 and a near UV-C LED without an n-side multilayer structure 101 (a conventional UV LED). The peak spectral radiant power and integrated spectral radiant power for the novel UV-C LED both demonstrate an above 300% increase compared with the conventional near UV-C LED.

[0095] FIG. 11 shows the typical surface morphology of an active region of a conventional UV-C or near UV-C LED. As can be seen, the surface is extremely smooth overall and does not contain any disc-hillocks, in contrast to FIGS. 5A and 5B. It can be noted that the average RMS roughness of the conventional UV LED active region surface over a 2 μm×2 μm region is lower than that of the UV LED with the novel multilayer structure.

[0096] FIG. 12A shows the typical schematic sectional view of a conventional UV-C LED (wherein FIGS. 12B and 12C are magnified callouts of layers 102a and 102b, and 110a and 110b, respectively). Compared with FIG. 3A, it is evident that the n-side multilayer structure 101 is not present.

Alternatives and Modifications

[0097] A number of alternatives and modifications are available for the present invention, as set forth below:

[0098] 1. A III-nitride light emitting device, comprising: a III-nitride-based n-side multilayer structure having regions of higher Al composition compared to adjacent layers.

[0099] 2. A III-nitride light emitting device, comprising: at least one III-nitride semiconductor layer has a (102) rocking curve full width at half-maximum of between 150-500 arcseconds or dislocation density between 1×10.sup.7 to 1×10.sup.10 cm.sup.−2.

[0100] 3. The device of 2, wherein the III-nitride semiconductor layer is AlN.

[0101] 4. The device of 1, wherein at least one III-nitride semiconductor layer of the n-side multilayer structure has a (102) rocking curve full width at half-maximum of between 150-500 arcseconds or dislocation density between 1×10.sub.7 to 1×10.sup.10 cm.sup.−2.

[0102] 5. A III-nitride light emitting device, comprising: an active region that is undulating.

[0103] 6. The device of 1-4, wherein an active region is undulating.

[0104] 7. The device of 1-6, wherein the n-side multilayer structure does not emit light.

[0105] 8. The device of 1-7, wherein the active region is on, above, below, or adjacent to the n-side multilayer structure.

[0106] 9. The device of 1-8, wherein at least some of the n-side multilayer structure emits light and is part of the undulating active region.

[0107] 10. The device of 1-9, wherein at least one of the individual layers of the n-side multilayer structure contains at least some Si, Ge, Mg, C, O, Be, Ca, Fe, or other impurity.

[0108] 11. The device of 1-10, wherein at least one of the individual layers of the active region contains at least some Si, Ge, Mg, C, O, Be, Ca, Fe, or other impurity.

[0109] 12. The device of 1-11, wherein the active region contains a lower concentration of Si, Ge, Mg, C, O, Be, Ca, Fe, or other impurity compared to the n-side multilayer structure.

[0110] 13. The device of 1-12, wherein the active region contains an equal or higher concentration of Si, Ge, Mg, C, O, Be, Ca, Fe, or other impurity compared to the multilayer structure.

[0111] 14. The device of 1-13, wherein the device is formed on or above a free-standing GaN, AlN, sapphire (including flat sapphire, patterned sapphire, or any other type of sapphire), SiC, or other growth substrate.

[0112] 15. The device of 1-14, wherein the basal plane of the growth substrate used is the c-plane.

[0113] 16. The device of 1-15, wherein the miscut of the substrate is between 0.2 and 1 degree towards the m-direction.

[0114] 17. The device of 1-15, wherein the miscut of the substrate is between 0.2 and 1 degree towards the a-direction.

[0115] 18. The device of 1-15, wherein the miscut of the substrate is greater than or equal to 1 degree towards the m-direction.

[0116] 19. The device of 1-15, wherein the miscut of the substrate is greater than or equal to 1 degree towards the a-direction.

[0117] 20. The device of 1-15, wherein the miscut of the substrate is less than or equal to 0.2 degrees towards the m-direction.

[0118] 21. The device of 1-15, wherein the miscut of the substrate is less than or equal to 0.2 degrees towards the a-direction.

[0119] 22. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the multilayer structure is in the range of 10's to 10.sup.21 cm.sup.−3.

[0120] 23. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the multilayer structure is in the range of 10.sup.16 to 10.sup.21 cm.sup.−3.

[0121] 24. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the multilayer structure is in the range of 10.sup.16 to 10.sup.20 cm.sup.−3.

[0122] 25. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the multilayer structure is in the range of 10.sup.17 to 10.sup.20 cm.sup.−3.

[0123] 26. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the multilayer structure is in the range of 10.sup.18 to 10.sup.20 cm.sup.−3.

[0124] 27. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the active region is in the range of 10.sup.15 to 10.sup.21 cm.sup.−3.

[0125] 28. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the active region is in the range of 10.sup.16 to 10.sup.21 cm.sup.−3.

[0126] 29. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the active region is in the range of 10.sup.16 to 10.sup.20 cm.sup.−3.

[0127] 30. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the active region is in the range of 10.sup.17 to 10.sup.20 cm.sup.−3.

[0128] 31. The device of 1-21, wherein the impurity concentration of the mentioned impurities in the active region is in the range of 10.sup.18 to 10.sup.20 cm.sup.−3.

[0129] 32. The device of 1-31, further comprising at least one III-nitride electron blocking layer on or above the active region, having a composition Al.sub.xGa.sub.1−xN wherein 0≤x≤1.

[0130] 33. The device of 1-32, wherein the electron blocking layer contains at least some Mg, Be, Ca, C, O, Fe, or other impurity.

[0131] 34. The device of 1-33, wherein the impurity concentration of the mentioned impurities in the electron blocking layer is in the range of 10.sup.15 to 10.sup.21 cm.sup.−3.

[0132] 35. The device of 1-33, wherein the impurity concentration of the mentioned impurities in the electron blocking layer is in the range of 10.sup.16 to 10.sup.21 cm.sup.−3.

[0133] 36. The device of 1-33, wherein the impurity concentration of the mentioned impurities in the electron blocking layer is in the range of 10.sup.16 to 10.sup.20 cm.sup.−3.

[0134] 37. The device of 1-33, wherein the impurity concentration of the mentioned impurities in the electron blocking layer is in the range of 10.sup.17 to 10.sup.20 cm.sup.−3.

[0135] 38. The device of 1-33, wherein the impurity concentration of the mentioned impurities in the electron blocking layer is in the range of 10.sup.18 to 10.sup.20 cm.sup.−3.

[0136] 39. The device of 1-38, further comprising at least one III-nitride superlattice on or above the active region, having at least two periods of alternating layers of Al.sub.xGa.sub.1−xN and Al.sub.yGa.sub.1−yN, where 0≤x≤1 and 0≤y≤1, and containing at least some Mg, Be, Ca, C, O, Fe, or other impurity.

[0137] 40. The device of 1-39, wherein the individual layers of the III-nitride superlattice are between 0.3 nm and 3 nm thick.

[0138] 41. The device of 1-39, wherein the impurity concentration of the mentioned impurities in the p-type superlattice layers are in the range of 10.sup.15 to 10.sup.21 cm.sup.−3.

[0139] 42. The device of 1-39, wherein the impurity concentration of the mentioned impurities in the p-type superlattice layers are in the range of 10.sup.16 to 10.sup.21 cm.sup.−3.

[0140] 43. The device of 1-39, wherein the impurity concentration of the mentioned impurities in the p-type superlattice layers are in the range of 10.sup.16 to 10.sup.20 cm.sup.−3.

[0141] 44. The device of 1-39, wherein the impurity concentration of the mentioned impurities in the p-type superlattice layers are in the range of 10.sup.17 to 10.sup.20 cm.sup.−3.

[0142] 45. The device of 1-39, wherein the impurity concentration of the mentioned impurities in the p-type superlattice layers are in the range of 10.sup.18 to 10.sup.20 cm.sup.−3.

[0143] 46. The device of 1-38, further comprising at least one III-nitride p-type layer on or above the active region that is 3D polarization doped.

[0144] 47. The device of 46, wherein the 3D polarization doped p-type III-nitride layer has a continuously varying composition of between Al.sub.xGa.sub.1−xN and Al.sub.yGa.sub.1−yN where 0≤x≤1 and 0≤y≤1, and containing at least some Mg, Be, Ca, C, O, Fe, or other impurity at a continuously varying or constant composition.

[0145] 48. The device of 46-47, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.15 to 10.sup.21 cm.sup.−3.

[0146] 49. The device of 46-47, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.16 to 10.sup.21 cm.sup.−3.

[0147] 50. The device of 46-47, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.16 to 10.sup.20 cm.sup.−3.

[0148] 51. The device of 46-47, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.17 to 10.sup.20 cm.sup.−3.

[0149] 52. The device of 46-47, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.18 to 10.sup.20 cm.sup.−3.

[0150] 53. The device of 46-47, wherein the Mg concentration in the p-type AlGaN layer with a continuously varying composition is below 10.sup.21 cm.sup.−3.

[0151] 54. The device of 46-47, wherein the Mg concentration in the p-type AlGaN layer with a continuously varying composition is below 10.sup.20 cm.sup.−3.

[0152] 55. The device of 46-47, wherein the Mg concentration in the p-type AlGaN layer with a continuously varying composition is below 10.sup.19 cm.sup.−3.

[0153] 56. The device of 46-47, wherein the Mg concentration in the p-type AlGaN layer with a continuously varying composition is below 10.sup.18 cm.sup.−3.

[0154] 57. The device of 46-47, wherein the Mg concentration in the p-type AlGaN layer with a continuously varying composition is below 10.sup.17 cm.sup.−3.

[0155] 58. The device of 46-47, wherein the Mg concentration in the p-type AlGaN layer with a continuously varying composition is below 10.sup.16 cm.sup.−3.

[0156] 59. The device of 46-47, wherein the Mg concentration in the p-type AlGaN layer with a continuously varying composition is below 10.sup.15 cm.sup.−3.

[0157] 60. The device of 1-38, further comprising at least one III-nitride p-type layer on or above the active region, having a composition of Al.sub.xGa.sub.1−xN where 0≤x≤1, and containing at least some Mg, Be, Ca, C, O, Fe, or other impurity.

[0158] 61. The device of 60, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.15 to 10.sup.21 cm.sup.−3.

[0159] 62. The device of 60, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.16 to 10.sup.21 cm.sup.−3.

[0160] 63. The device of 60, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.16 to 10.sup.20 cm.sup.−3.

[0161] 64. The device of 60, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.17 to 10.sup.20 cm.sup.−3.

[0162] 65. The device of 60, wherein the impurity concentration of the mentioned impurities in the p-type AlGaN layer with a continuously varying or constant composition is in the range of 10.sup.18 to 10.sup.20 cm.sup.−3.

[0163] 66. The device of 1-65, further comprising a conducting layer on or above the rest of the device.

[0164] 67. The device of 66, wherein the conducting layer comprises at least some IZO or ITO.

[0165] 68. The device of 66, wherein the conducting layer comprises at least one metallic layer composed of V, Al, Ni, Au, Ag, Pt, Pd, In, and/or other metal.

[0166] 69. The device of 66, wherein the conducting layer forms a tunnel junction to a p-type layer below it.

[0167] 70. The device of 69, wherein the conducting layer is partially or fully transparent.

[0168] 71. The device of 70, wherein the conducting layer is composed of Ga.sub.2O.sub.3.

[0169] 72. The device of 70, wherein the conducting layer is n-type Al.sub.xGa.sub.1−xN where 0≤x≤1 and contains at least some Si, Ge, or other impurity.

[0170] 73. The device of 70, wherein the impurity concentration of the mentioned impurities in the transparent conducting Al.sub.xGa.sub.1−xN layer is in the range of 10.sup.15 to 10.sup.21 cm.sup.−3.

[0171] 74. The device of 70, wherein the impurity concentration of the mentioned impurities in the transparent conducting Al.sub.xGa.sub.1−xN layer is in the range of 10.sup.16 to 10.sup.21 cm.sup.−3.

[0172] 75. The device of 70, wherein the impurity concentration of the mentioned impurities in the transparent conducting Al.sub.xGa.sub.1−xN layer is in the range of 10.sup.16 to 10.sup.20 cm.sup.−3.

[0173] 76. The device of 70, wherein the impurity concentration of the mentioned impurities in the transparent conducting Al.sub.xGa.sub.1−xN layer is in the range of 10.sup.17 to 10.sup.20 cm.sup.−3.

[0174] 77. The device of 70, wherein the impurity concentration of the mentioned impurities in the transparent conducting Al.sub.xGa.sub.1−xN layer is in the range of 10.sup.18 to 10.sup.20 cm.sup.−3.

[0175] 78. The device of 66-77, wherein the conducting layers are directly on or above a p-type Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice.

[0176] 79. The device of 78, wherein the conducting layer comprises n-type Al.sub.xGa.sub.1−xN that is grown directly on or above the p-type Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice.

[0177] 80. The device of 76, wherein the growth temperature of the n-type Al.sub.xGa.sub.1−xN conducting layer is lower than that of the p-type Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice.

[0178] 81. The device of 76, wherein the n-type Al.sub.xGa.sub.1−xN conducting layer is grown on or above the Mg-doped Al.sub.yGa.sub.1−yN of the p-type Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice.

[0179] 82. The device of 76, wherein the n-type Al.sub.xGa.sub.1−xN conducting layer is grown on or above the Mg-doped Al.sub.xGa.sub.1−xN of the p-type Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice.

[0180] 83. The device of 75-79, wherein the thickness of each layer in the p-type Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice is less than 5 nm.

[0181] 84. The device of 75-79, wherein the thickness of each layer in the p-type Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice is less than 3 nm.

[0182] 85. The device of 75-79, wherein the thickness of each layer in the p-type Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice is less than 2 nm.

[0183] 86. The device of 75-82, wherein the as grown Mg-doped Al.sub.xGa.sub.1−xN/Mg-doped Al.sub.yGa.sub.1−yN (x>y) superlattice has p-type conductance without any additional treatments after material growth.

[0184] 87. The device of 63-74, wherein the conducting layers are directly on or above a 3D polarization p-type doped layer composed of AlGaN with a continuously varying composition of between Al.sub.xGa.sub.1−xN and Al.sub.yGa.sub.1−yN wherein 0≤x≤1 and 0≤y≤1, as described in 43-56.

[0185] 88. The device of 87, wherein the conducting layer comprises n-type Al.sub.xGa.sub.1−xN (0≤x≤1) that is grown directly on or above the 3D polarization doped p-type AlGaN layer.

[0186] 89. The device of 88, wherein the growth temperature of the n-type Al.sub.xGa.sub.1−xN conducting layer is lower than that of the 3D polarization doped p-type AlGaN layer.

[0187] 90. The device of 87-89, wherein the as grown 3D polarization doped p-type AlGaN layer has p-type conductance without any additional treatments after material growth.

[0188] 91. The device of 66, wherein the conducting layer includes a homogeneous p-type GaN layer on or above the rest of the device, containing at least some Mg, Be, Ca, C, O, Fe, or other impurity.

[0189] 92. The device of 66, wherein the conducting layer includes a p-type GaN layer covering less than 70% of the surface on or above the rest of the device, containing at least some Mg, Be, Ca, C, O, Fe, or other impurity.

[0190] 93. The device of 91-92, wherein the impurity concentration of the mentioned impurities in the p-GaN layer is in the range of 10.sup.15 to 10.sup.21 cm.sup.−3.

[0191] 94. The device of 91-92, wherein the impurity concentration of the mentioned impurities in the p-GaN layer is in the range of 10.sup.16 to 10.sup.21 cm.sup.−3.

[0192] 95. The device of 91-92, wherein the impurity concentration of the mentioned impurities in the p-GaN layer is in the range of 10.sup.16 to 10.sup.20 cm.sup.−3.

[0193] 96. The device of 91-92, wherein the impurity concentration of the mentioned impurities in the p-GaN layer is in the range of 10.sup.17 to 10.sup.20 cm.sup.−3.

[0194] 97. The device of 91-92, wherein the impurity concentration of the mentioned impurities in the p-GaN layer is in the range of 10.sup.18 to 10.sup.20 cm.sup.−3.

[0195] 98. The device of 91-92, wherein the conducting layer further comprises at least one metallic or conductive oxide layer on or above the p-type GaN layer.

[0196] 99. The device of 98, wherein the layer comprises V, Al, Ni, Au, Ag, Pt, Pd, In, and/or other metals on or above the p-type GaN layer.

[0197] 100. The device of 98, wherein the conducting layer comprises at least one layer of IZO, ITO, Ga.sub.2O.sub.3, or other conductive oxide on or above the p-type GaN layer.

[0198] 101. The device of 1-100, wherein the entire device is grown on or above a layer of AlN of dislocation density more than 107 cm.sup.−2.

[0199] 102. The device of 1-100, wherein the entire device is grown on or above a layer of AlN of dislocation density more than 10.sup.8 cm.sup.−2.

[0200] 103. The device of 1-100, wherein the entire device is grown on or above a layer of AlN of dislocation density more than 5×10.sup.8 cm.sup.−2.

[0201] 104. The device of 1-103, wherein the active region is undulating with an amplitude of at least 0.5 nm over a 2 μm by 2 μm region.

[0202] 105. The device of 1-103, wherein the active region is undulating with an amplitude of at least 1 nm over a 2 μm by 2 μm region.

[0203] 106. The device of 1-103, wherein the active region is undulating with an amplitude of at least 2 nm over a 2 μm by 2 μm region.

[0204] 107. The device of 1-103, wherein the active region is undulating with an amplitude of at least 5 nm over a 2 μm by 2 μm region.

[0205] 108. The device of 1-107, wherein the active region surface has a disc-hillock morphology with an RMS roughness of between 0.5 to 15 nm over a 2 μm by 2 μm region, but comprises local regions at least 200 nm by 200 nm in size with an RMS roughness of less than 1 nm.

[0206] 109. The device of 1-107, wherein the active region surface has a disc-hillock morphology with an RMS roughness of between 0.5 to 10 nm over a 2 μm by 2 μm region, but comprises local regions at least 200 nm by 200 nm in size with an RMS roughness of less than 1 nm.

[0207] 110. The device of 1-107, wherein the active region surface has a disc-hillock morphology with an RMS roughness of between 0.5 to 10 nm over a 2 μm by 2 μm region, but comprises local regions at least 100 nm by 100 nm in size with an RMS roughness of less than 1 nm.

[0208] 111. The device of 1-107, wherein the active region surface has a disc-hillock morphology with an RMS roughness of between 1 to 7 nm over a 2 μm by 2 μm region, but comprises local regions at least 100 nm by 100 nm in size with an RMS roughness of less than 0.8 nm.

[0209] 112. The device of 108, wherein the active region surface comprises at least some islands 50-1000 nm in diameter, 1-50 nm tall.

[0210] 113. The device of 108, wherein the active region surface comprises at least some islands 100-700 nm in diameter, 1-20 nm tall.

[0211] 114. The device of 1-113, wherein a layer of reflective material is on, above, below, or around the device.

[0212] 115. The device of 114, wherein that reflective material is MgF.sub.2 or SiO.sub.2.

[0213] 116. The device of 114, wherein that reflective material is V, Al, Ni, Au, Ag, Pt, Pd, In, or any other metal.

[0214] 117. A method for the fabrication of the device of 1-116, wherein a III-nitride material is deposited on or above a substrate.

[0215] 118. The method of 117, wherein TMI is used in the growth of the device material layers.

[0216] 119. The method of 117-118, wherein a higher flow of TMI is used in the growth of the device material layers compared to the flow of TMA and TMG.

[0217] 120. The method of 117-119, wherein the flow of at least one of the metalorganic precursors is paused for at least 3 seconds in between the growth of the alternating layers in the multilayer structure.

[0218] 121. The method of 117-120, wherein the flow of ammonia is paused for at least 3 seconds in between the growth of the alternating layers in the multilayer structure.

[0219] 122. The method of 117-121, wherein the flow of at least one of the metalorganic precursors is paused for at least 3 seconds in between the growth of the different layers in the active region.

[0220] 123. The method of 117-122, wherein the flow of ammonia is paused for at least 3 seconds in between the growth of the different layers in the active region.

[0221] 124. The method of 117-123, wherein the flow of metalorganic precursor is paused for at least 3 seconds in order to create a layer of higher aluminum composition at least once in the device.

[0222] 125. The method of 117-124, wherein the flow of ammonia is paused in order to create a layer of higher aluminum composition at least once in the device.

[0223] 126. The method of 117-125, wherein the V to III ratio used in the growth of the multilayer structure is less than 500.

[0224] 127. The method of 117-126, wherein the V to III ratio used in the growth of the multilayer structure is less than 100.

[0225] 128. The method of 117-126, wherein the V to III ratio used in the growth of the multilayer structure is less than 50.

[0226] 129. The method of 117-126, wherein the V to III ratio used in the growth of the multilayer structure is less than 20.

[0227] 130. The method of 117-129, wherein the V to III ratio used in the growth of the AlGaN cladding layers in between the substrate and the interlayer is less than 500.

[0228] 131. The method of 117-129, wherein the V to III ratio used in the growth of the AlGaN cladding layers in between the substrate and the interlayer is less than 100.

[0229] 132. The method of 117-129, wherein the V to III ratio used in the growth of the AlGaN cladding layers in between the substrate and the interlayer is less than 50.

[0230] 133. The method of 117-129, wherein the V to III ratio used in the growth of the AlGaN cladding layers in between the substrate and the interlayer is less than 20.

[0231] 134. The method of 117-133, wherein the V to III ratio used in the growth of the layers in the active region is less than 500.

[0232] 135. The method of 117-133, wherein the V to III ratio used in the growth of the layers in the active region is less than 100.

[0233] 136. The method of 117-133, wherein the V to III ratio used in the growth of the layers in the active region is less than 50.

[0234] 137. The method of 117-133, wherein the V to III ratio used in the growth of the layers in the active region is less than 20.

[0235] 138. The method of 117-137, wherein the device is grown such that the principal surface of the device material is represented by a c-face, r-face, n-face, v-face, m-face, or a-face.

[0236] 139. The method of 117-138, wherein the device is grown on a patterned substrate.

[0237] 140. The method of 117-139, wherein the patterned substrate is a patterned sapphire substrate.

[0238] 141. The method of 117-140, wherein all steps of the wafer fabrication occur at a temperature below 1000 C.

[0239] 142. The method of 117-140, wherein all steps of the wafer fabrication occur at a temperature below 900 C.

[0240] 143. The method of 117-140, wherein all steps of the wafer fabrication occur at a temperature below 800 C.

[0241] 144. The method of 117-140, wherein all steps of the wafer fabrication occur at a temperature below 750 C.

[0242] 145. The method of 117-140, wherein all steps of the wafer fabrication occur at a temperature below 700 C.

[0243] 146. The method of 117-140, wherein all steps of the wafer fabrication occur at a temperature below 650 C.

[0244] 147. The method of 117-140, wherein all steps of the wafer fabrication occur at a temperature below 600 C.

CONCLUSION

[0245] This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.